1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m_store_core_reg_u32(struct target
*target
,
63 uint32_t num
, uint32_t value
);
65 static int cortexm_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
66 uint32_t *value
, int regnum
)
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
74 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
78 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
79 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
80 if (retval
!= ERROR_OK
)
82 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
83 if (retval
!= ERROR_OK
)
86 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
87 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
88 if (retval
!= ERROR_OK
)
90 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
91 if (retval
!= ERROR_OK
)
94 retval
= dap_run(swjdp
);
95 if (retval
!= ERROR_OK
)
98 /* restore DCB_DCRDR - this needs to be in a seperate
99 * transaction otherwise the emulated DCC channel breaks */
100 if (retval
== ERROR_OK
)
101 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
106 static int cortexm_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
107 uint32_t value
, int regnum
)
112 /* because the DCB_DCRDR is used for the emulated dcc channel
113 * we have to save/restore the DCB_DCRDR when used */
115 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
116 if (retval
!= ERROR_OK
)
119 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
120 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
121 if (retval
!= ERROR_OK
)
123 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
124 if (retval
!= ERROR_OK
)
127 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
128 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
129 if (retval
!= ERROR_OK
)
131 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
132 if (retval
!= ERROR_OK
)
135 retval
= dap_run(swjdp
);
136 if (retval
!= ERROR_OK
)
139 /* restore DCB_DCRDR - this needs to be in a seperate
140 * transaction otherwise the emulated DCC channel breaks */
141 if (retval
== ERROR_OK
)
142 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
147 static int cortex_m_write_debug_halt_mask(struct target
*target
,
148 uint32_t mask_on
, uint32_t mask_off
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
153 /* mask off status bits */
154 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
155 /* create new register mask */
156 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
158 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
161 static int cortex_m_clear_halt(struct target
*target
)
163 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
164 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
167 /* clear step if any */
168 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
170 /* Read Debug Fault Status Register */
171 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
172 if (retval
!= ERROR_OK
)
175 /* Clear Debug Fault Status */
176 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
177 if (retval
!= ERROR_OK
)
179 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
184 static int cortex_m_single_step_core(struct target
*target
)
186 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
187 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
191 /* backup dhcsr reg */
192 dhcsr_save
= cortex_m
->dcb_dhcsr
;
194 /* Mask interrupts before clearing halt, if done already. This avoids
195 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
196 * HALT can put the core into an unknown state.
198 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
199 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
200 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
201 if (retval
!= ERROR_OK
)
204 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
205 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
206 if (retval
!= ERROR_OK
)
210 /* restore dhcsr reg */
211 cortex_m
->dcb_dhcsr
= dhcsr_save
;
212 cortex_m_clear_halt(target
);
217 static int cortex_m_endreset_event(struct target
*target
)
222 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
223 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
224 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
225 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
226 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
228 /* REVISIT The four debug monitor bits are currently ignored... */
229 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
230 if (retval
!= ERROR_OK
)
232 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
234 /* this register is used for emulated dcc channel */
235 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
236 if (retval
!= ERROR_OK
)
239 /* Enable debug requests */
240 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
241 if (retval
!= ERROR_OK
)
243 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
244 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
245 if (retval
!= ERROR_OK
)
249 /* clear any interrupt masking */
250 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
252 /* Enable features controlled by ITM and DWT blocks, and catch only
253 * the vectors we were told to pay attention to.
255 * Target firmware is responsible for all fault handling policy
256 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
257 * or manual updates to the NVIC SHCSR and CCR registers.
259 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
260 if (retval
!= ERROR_OK
)
263 /* Paranoia: evidently some (early?) chips don't preserve all the
264 * debug state (including FBP, DWT, etc) across reset...
268 retval
= target_write_u32(target
, FP_CTRL
, 3);
269 if (retval
!= ERROR_OK
)
272 cortex_m
->fpb_enabled
= 1;
274 /* Restore FPB registers */
275 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
276 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
277 if (retval
!= ERROR_OK
)
281 /* Restore DWT registers */
282 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
283 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
285 if (retval
!= ERROR_OK
)
287 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
289 if (retval
!= ERROR_OK
)
291 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
292 dwt_list
[i
].function
);
293 if (retval
!= ERROR_OK
)
296 retval
= dap_run(swjdp
);
297 if (retval
!= ERROR_OK
)
300 register_cache_invalidate(armv7m
->arm
.core_cache
);
302 /* make sure we have latest dhcsr flags */
303 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
308 static int cortex_m_examine_debug_reason(struct target
*target
)
310 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
312 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
313 * only check the debug reason if we don't know it already */
315 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
316 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
317 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
318 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
319 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
320 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
321 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
322 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
323 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
324 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
325 else /* EXTERNAL, HALTED */
326 target
->debug_reason
= DBG_REASON_UNDEFINED
;
332 static int cortex_m_examine_exception_reason(struct target
*target
)
334 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
335 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
336 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
339 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
340 if (retval
!= ERROR_OK
)
342 switch (armv7m
->exception_number
) {
345 case 3: /* Hard Fault */
346 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
347 if (retval
!= ERROR_OK
)
349 if (except_sr
& 0x40000000) {
350 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
351 if (retval
!= ERROR_OK
)
355 case 4: /* Memory Management */
356 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
357 if (retval
!= ERROR_OK
)
359 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
360 if (retval
!= ERROR_OK
)
363 case 5: /* Bus Fault */
364 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
365 if (retval
!= ERROR_OK
)
367 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
368 if (retval
!= ERROR_OK
)
371 case 6: /* Usage Fault */
372 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
373 if (retval
!= ERROR_OK
)
376 case 11: /* SVCall */
378 case 12: /* Debug Monitor */
379 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
380 if (retval
!= ERROR_OK
)
383 case 14: /* PendSV */
385 case 15: /* SysTick */
391 retval
= dap_run(swjdp
);
392 if (retval
== ERROR_OK
)
393 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
394 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
395 armv7m_exception_string(armv7m
->exception_number
),
396 shcsr
, except_sr
, cfsr
, except_ar
);
400 static int cortex_m_debug_entry(struct target
*target
)
405 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
406 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
407 struct arm
*arm
= &armv7m
->arm
;
408 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
413 cortex_m_clear_halt(target
);
414 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
415 if (retval
!= ERROR_OK
)
418 retval
= armv7m
->examine_debug_reason(target
);
419 if (retval
!= ERROR_OK
)
422 /* Examine target state and mode
423 * First load register accessible through core debug port */
424 int num_regs
= arm
->core_cache
->num_regs
;
426 for (i
= 0; i
< num_regs
; i
++) {
427 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
429 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
433 xPSR
= buf_get_u32(r
->value
, 0, 32);
435 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
438 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
441 /* Are we in an exception handler */
443 armv7m
->exception_number
= (xPSR
& 0x1FF);
445 arm
->core_mode
= ARM_MODE_HANDLER
;
446 arm
->map
= armv7m_msp_reg_map
;
448 unsigned control
= buf_get_u32(arm
->core_cache
449 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
451 /* is this thread privileged? */
452 arm
->core_mode
= control
& 1
453 ? ARM_MODE_USER_THREAD
456 /* which stack is it using? */
458 arm
->map
= armv7m_psp_reg_map
;
460 arm
->map
= armv7m_msp_reg_map
;
462 armv7m
->exception_number
= 0;
465 if (armv7m
->exception_number
)
466 cortex_m_examine_exception_reason(target
);
468 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
469 arm_mode_name(arm
->core_mode
),
470 *(uint32_t *)(arm
->pc
->value
),
471 target_state_name(target
));
473 if (armv7m
->post_debug_entry
) {
474 retval
= armv7m
->post_debug_entry(target
);
475 if (retval
!= ERROR_OK
)
482 static int cortex_m_poll(struct target
*target
)
484 int detected_failure
= ERROR_OK
;
485 int retval
= ERROR_OK
;
486 enum target_state prev_target_state
= target
->state
;
487 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
488 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
490 /* Read from Debug Halting Control and Status Register */
491 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
492 if (retval
!= ERROR_OK
) {
493 target
->state
= TARGET_UNKNOWN
;
497 /* Recover from lockup. See ARMv7-M architecture spec,
498 * section B1.5.15 "Unrecoverable exception cases".
500 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
501 LOG_ERROR("%s -- clearing lockup after double fault",
502 target_name(target
));
503 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
504 target
->debug_reason
= DBG_REASON_DBGRQ
;
506 /* We have to execute the rest (the "finally" equivalent, but
507 * still throw this exception again).
509 detected_failure
= ERROR_FAIL
;
511 /* refresh status bits */
512 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
513 if (retval
!= ERROR_OK
)
517 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
518 /* check if still in reset */
519 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
520 if (retval
!= ERROR_OK
)
523 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
524 target
->state
= TARGET_RESET
;
529 if (target
->state
== TARGET_RESET
) {
530 /* Cannot switch context while running so endreset is
531 * called with target->state == TARGET_RESET
533 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
534 cortex_m
->dcb_dhcsr
);
535 cortex_m_endreset_event(target
);
536 target
->state
= TARGET_RUNNING
;
537 prev_target_state
= TARGET_RUNNING
;
540 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
541 target
->state
= TARGET_HALTED
;
543 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
544 retval
= cortex_m_debug_entry(target
);
545 if (retval
!= ERROR_OK
)
548 if (arm_semihosting(target
, &retval
) != 0)
551 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
553 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
555 retval
= cortex_m_debug_entry(target
);
556 if (retval
!= ERROR_OK
)
559 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
563 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
564 * How best to model low power modes?
567 if (target
->state
== TARGET_UNKNOWN
) {
568 /* check if processor is retiring instructions */
569 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
570 target
->state
= TARGET_RUNNING
;
575 /* Did we detect a failure condition that we cleared? */
576 if (detected_failure
!= ERROR_OK
)
577 retval
= detected_failure
;
581 static int cortex_m_halt(struct target
*target
)
583 LOG_DEBUG("target->state: %s",
584 target_state_name(target
));
586 if (target
->state
== TARGET_HALTED
) {
587 LOG_DEBUG("target was already halted");
591 if (target
->state
== TARGET_UNKNOWN
)
592 LOG_WARNING("target was in unknown state when halt was requested");
594 if (target
->state
== TARGET_RESET
) {
595 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
596 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
597 return ERROR_TARGET_FAILURE
;
599 /* we came here in a reset_halt or reset_init sequence
600 * debug entry was already prepared in cortex_m3_assert_reset()
602 target
->debug_reason
= DBG_REASON_DBGRQ
;
608 /* Write to Debug Halting Control and Status Register */
609 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
611 target
->debug_reason
= DBG_REASON_DBGRQ
;
616 static int cortex_m_soft_reset_halt(struct target
*target
)
618 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
619 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
620 uint32_t dcb_dhcsr
= 0;
621 int retval
, timeout
= 0;
623 /* soft_reset_halt is deprecated on cortex_m as the same functionality
624 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
625 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
626 * core, not the peripherals */
627 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
629 /* Enter debug state on reset; restore DEMCR in endreset_event() */
630 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
631 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
632 if (retval
!= ERROR_OK
)
635 /* Request a core-only reset */
636 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
637 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
638 if (retval
!= ERROR_OK
)
640 target
->state
= TARGET_RESET
;
642 /* registers are now invalid */
643 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
645 while (timeout
< 100) {
646 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
647 if (retval
== ERROR_OK
) {
648 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
649 &cortex_m
->nvic_dfsr
);
650 if (retval
!= ERROR_OK
)
652 if ((dcb_dhcsr
& S_HALT
)
653 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
654 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
656 (unsigned) dcb_dhcsr
,
657 (unsigned) cortex_m
->nvic_dfsr
);
658 cortex_m_poll(target
);
659 /* FIXME restore user's vector catch config */
662 LOG_DEBUG("waiting for system reset-halt, "
663 "DHCSR 0x%08x, %d ms",
664 (unsigned) dcb_dhcsr
, timeout
);
673 void cortex_m_enable_breakpoints(struct target
*target
)
675 struct breakpoint
*breakpoint
= target
->breakpoints
;
677 /* set any pending breakpoints */
679 if (!breakpoint
->set
)
680 cortex_m_set_breakpoint(target
, breakpoint
);
681 breakpoint
= breakpoint
->next
;
685 static int cortex_m_resume(struct target
*target
, int current
,
686 uint32_t address
, int handle_breakpoints
, int debug_execution
)
688 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
689 struct breakpoint
*breakpoint
= NULL
;
693 if (target
->state
!= TARGET_HALTED
) {
694 LOG_WARNING("target not halted");
695 return ERROR_TARGET_NOT_HALTED
;
698 if (!debug_execution
) {
699 target_free_all_working_areas(target
);
700 cortex_m_enable_breakpoints(target
);
701 cortex_m_enable_watchpoints(target
);
704 if (debug_execution
) {
705 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
707 /* Disable interrupts */
708 /* We disable interrupts in the PRIMASK register instead of
709 * masking with C_MASKINTS. This is probably the same issue
710 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
711 * in parallel with disabled interrupts can cause local faults
714 * REVISIT this clearly breaks non-debug execution, since the
715 * PRIMASK register state isn't saved/restored... workaround
716 * by never resuming app code after debug execution.
718 buf_set_u32(r
->value
, 0, 1, 1);
722 /* Make sure we are in Thumb mode */
723 r
= armv7m
->arm
.cpsr
;
724 buf_set_u32(r
->value
, 24, 1, 1);
729 /* current = 1: continue on current pc, otherwise continue at <address> */
732 buf_set_u32(r
->value
, 0, 32, address
);
737 /* if we halted last time due to a bkpt instruction
738 * then we have to manually step over it, otherwise
739 * the core will break again */
741 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
743 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
745 resume_pc
= buf_get_u32(r
->value
, 0, 32);
747 armv7m_restore_context(target
);
749 /* the front-end may request us not to handle breakpoints */
750 if (handle_breakpoints
) {
751 /* Single step past breakpoint at current address */
752 breakpoint
= breakpoint_find(target
, resume_pc
);
754 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %d)",
756 breakpoint
->unique_id
);
757 cortex_m_unset_breakpoint(target
, breakpoint
);
758 cortex_m_single_step_core(target
);
759 cortex_m_set_breakpoint(target
, breakpoint
);
764 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
766 target
->debug_reason
= DBG_REASON_NOTHALTED
;
768 /* registers are now invalid */
769 register_cache_invalidate(armv7m
->arm
.core_cache
);
771 if (!debug_execution
) {
772 target
->state
= TARGET_RUNNING
;
773 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
774 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
776 target
->state
= TARGET_DEBUG_RUNNING
;
777 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
778 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
784 /* int irqstepcount = 0; */
785 static int cortex_m_step(struct target
*target
, int current
,
786 uint32_t address
, int handle_breakpoints
)
788 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
789 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
790 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
791 struct breakpoint
*breakpoint
= NULL
;
792 struct reg
*pc
= armv7m
->arm
.pc
;
793 bool bkpt_inst_found
= false;
795 bool isr_timed_out
= false;
797 if (target
->state
!= TARGET_HALTED
) {
798 LOG_WARNING("target not halted");
799 return ERROR_TARGET_NOT_HALTED
;
802 /* current = 1: continue on current pc, otherwise continue at <address> */
804 buf_set_u32(pc
->value
, 0, 32, address
);
806 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
808 /* the front-end may request us not to handle breakpoints */
809 if (handle_breakpoints
) {
810 breakpoint
= breakpoint_find(target
, pc_value
);
812 cortex_m_unset_breakpoint(target
, breakpoint
);
815 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
817 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
819 armv7m_restore_context(target
);
821 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
823 /* if no bkpt instruction is found at pc then we can perform
824 * a normal step, otherwise we have to manually step over the bkpt
825 * instruction - as such simulate a step */
826 if (bkpt_inst_found
== false) {
827 /* Automatic ISR masking mode off: Just step over the next instruction */
828 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
))
829 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
831 /* Process interrupts during stepping in a way they don't interfere
836 * Set a temporary break point at the current pc and let the core run
837 * with interrupts enabled. Pending interrupts get served and we run
838 * into the breakpoint again afterwards. Then we step over the next
839 * instruction with interrupts disabled.
841 * If the pending interrupts don't complete within time, we leave the
842 * core running. This may happen if the interrupts trigger faster
843 * than the core can process them or the handler doesn't return.
845 * If no more breakpoints are available we simply do a step with
846 * interrupts enabled.
852 * If a break point is already set on the lower half word then a break point on
853 * the upper half word will not break again when the core is restarted. So we
854 * just step over the instruction with interrupts disabled.
856 * The documentation has no information about this, it was found by observation
857 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
858 * suffer from this problem.
860 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
861 * address has it always cleared. The former is done to indicate thumb mode
865 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
866 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
867 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
868 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
869 /* Re-enable interrupts */
870 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
874 /* Set a temporary break point */
876 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
878 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
879 bool tmp_bp_set
= (retval
== ERROR_OK
);
881 /* No more breakpoints left, just do a step */
883 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
886 LOG_DEBUG("Starting core to serve pending interrupts");
887 int64_t t_start
= timeval_ms();
888 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
890 /* Wait for pending handlers to complete or timeout */
892 retval
= mem_ap_read_atomic_u32(swjdp
,
894 &cortex_m
->dcb_dhcsr
);
895 if (retval
!= ERROR_OK
) {
896 target
->state
= TARGET_UNKNOWN
;
899 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
900 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
902 /* only remove breakpoint if we created it */
904 cortex_m_unset_breakpoint(target
, breakpoint
);
906 /* Remove the temporary breakpoint */
907 breakpoint_remove(target
, pc_value
);
911 LOG_DEBUG("Interrupt handlers didn't complete within time, "
912 "leaving target running");
914 /* Step over next instruction with interrupts disabled */
915 cortex_m_write_debug_halt_mask(target
,
918 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
919 /* Re-enable interrupts */
920 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
927 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
928 if (retval
!= ERROR_OK
)
931 /* registers are now invalid */
932 register_cache_invalidate(armv7m
->arm
.core_cache
);
935 cortex_m_set_breakpoint(target
, breakpoint
);
938 /* Leave the core running. The user has to stop execution manually. */
939 target
->debug_reason
= DBG_REASON_NOTHALTED
;
940 target
->state
= TARGET_RUNNING
;
944 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
945 " nvic_icsr = 0x%" PRIx32
,
946 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
948 retval
= cortex_m_debug_entry(target
);
949 if (retval
!= ERROR_OK
)
951 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
953 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
954 " nvic_icsr = 0x%" PRIx32
,
955 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
960 static int cortex_m_assert_reset(struct target
*target
)
962 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
963 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
964 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
966 LOG_DEBUG("target->state: %s",
967 target_state_name(target
));
969 enum reset_types jtag_reset_config
= jtag_get_reset_config();
971 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
972 /* allow scripts to override the reset event */
974 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
975 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
976 target
->state
= TARGET_RESET
;
981 /* some cores support connecting while srst is asserted
982 * use that mode is it has been configured */
984 bool srst_asserted
= false;
986 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
987 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
988 adapter_assert_reset();
989 srst_asserted
= true;
992 /* Enable debug requests */
994 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
995 if (retval
!= ERROR_OK
)
997 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
998 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
999 if (retval
!= ERROR_OK
)
1003 /* If the processor is sleeping in a WFI or WFE instruction, the
1004 * C_HALT bit must be asserted to regain control */
1005 if (cortex_m
->dcb_dhcsr
& S_SLEEP
) {
1006 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1007 if (retval
!= ERROR_OK
)
1011 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1012 if (retval
!= ERROR_OK
)
1015 if (!target
->reset_halt
) {
1016 /* Set/Clear C_MASKINTS in a separate operation */
1017 if (cortex_m
->dcb_dhcsr
& C_MASKINTS
) {
1018 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1019 DBGKEY
| C_DEBUGEN
| C_HALT
);
1020 if (retval
!= ERROR_OK
)
1024 /* clear any debug flags before resuming */
1025 cortex_m_clear_halt(target
);
1027 /* clear C_HALT in dhcsr reg */
1028 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1030 /* Halt in debug on reset; endreset_event() restores DEMCR.
1032 * REVISIT catching BUSERR presumably helps to defend against
1033 * bad vector table entries. Should this include MMERR or
1036 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1037 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1038 if (retval
!= ERROR_OK
)
1042 if (jtag_reset_config
& RESET_HAS_SRST
) {
1043 /* default to asserting srst */
1045 adapter_assert_reset();
1047 /* Use a standard Cortex-M3 software reset mechanism.
1048 * We default to using VECRESET as it is supported on all current cores.
1049 * This has the disadvantage of not resetting the peripherals, so a
1050 * reset-init event handler is needed to perform any peripheral resets.
1052 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1053 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1054 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1055 if (retval
!= ERROR_OK
)
1058 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1059 ? "SYSRESETREQ" : "VECTRESET");
1061 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1062 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1063 "handler to reset any peripherals or configure hardware srst support.");
1067 /* I do not know why this is necessary, but it
1068 * fixes strange effects (step/resume cause NMI
1069 * after reset) on LM3S6918 -- Michael Schwingen
1072 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1073 if (retval
!= ERROR_OK
)
1078 target
->state
= TARGET_RESET
;
1079 jtag_add_sleep(50000);
1081 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1083 if (target
->reset_halt
) {
1084 retval
= target_halt(target
);
1085 if (retval
!= ERROR_OK
)
1092 static int cortex_m_deassert_reset(struct target
*target
)
1094 LOG_DEBUG("target->state: %s",
1095 target_state_name(target
));
1097 /* deassert reset lines */
1098 adapter_deassert_reset();
1103 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1108 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1109 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1111 if (breakpoint
->set
) {
1112 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint
->unique_id
);
1116 if (cortex_m
->auto_bp_type
)
1117 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1119 if (breakpoint
->type
== BKPT_HARD
) {
1120 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1122 if (fp_num
>= cortex_m
->fp_num_code
) {
1123 LOG_ERROR("Can not find free FPB Comparator!");
1126 breakpoint
->set
= fp_num
+ 1;
1127 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1128 comparator_list
[fp_num
].used
= 1;
1129 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1130 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1131 comparator_list
[fp_num
].fpcr_value
);
1132 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1134 comparator_list
[fp_num
].fpcr_value
);
1135 if (!cortex_m
->fpb_enabled
) {
1136 LOG_DEBUG("FPB wasn't enabled, do it now");
1137 target_write_u32(target
, FP_CTRL
, 3);
1139 } else if (breakpoint
->type
== BKPT_SOFT
) {
1142 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1143 * semihosting; don't use that. Otherwise the BKPT
1144 * parameter is arbitrary.
1146 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1147 retval
= target_read_memory(target
,
1148 breakpoint
->address
& 0xFFFFFFFE,
1149 breakpoint
->length
, 1,
1150 breakpoint
->orig_instr
);
1151 if (retval
!= ERROR_OK
)
1153 retval
= target_write_memory(target
,
1154 breakpoint
->address
& 0xFFFFFFFE,
1155 breakpoint
->length
, 1,
1157 if (retval
!= ERROR_OK
)
1159 breakpoint
->set
= true;
1162 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1163 breakpoint
->unique_id
,
1164 (int)(breakpoint
->type
),
1165 breakpoint
->address
,
1172 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1175 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1176 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1178 if (!breakpoint
->set
) {
1179 LOG_WARNING("breakpoint not set");
1183 LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1184 breakpoint
->unique_id
,
1185 (int)(breakpoint
->type
),
1186 breakpoint
->address
,
1190 if (breakpoint
->type
== BKPT_HARD
) {
1191 int fp_num
= breakpoint
->set
- 1;
1192 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1193 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1196 comparator_list
[fp_num
].used
= 0;
1197 comparator_list
[fp_num
].fpcr_value
= 0;
1198 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1199 comparator_list
[fp_num
].fpcr_value
);
1201 /* restore original instruction (kept in target endianness) */
1202 if (breakpoint
->length
== 4) {
1203 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1204 breakpoint
->orig_instr
);
1205 if (retval
!= ERROR_OK
)
1208 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1209 breakpoint
->orig_instr
);
1210 if (retval
!= ERROR_OK
)
1214 breakpoint
->set
= false;
1219 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1221 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1223 if (cortex_m
->auto_bp_type
)
1224 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1226 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1227 if (breakpoint
->type
== BKPT_HARD
) {
1228 LOG_INFO("flash patch comparator requested outside code memory region");
1229 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1232 if (breakpoint
->type
== BKPT_SOFT
) {
1233 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1234 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1238 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m
->fp_code_available
< 1)) {
1239 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1240 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1243 if ((breakpoint
->length
!= 2)) {
1244 LOG_INFO("only breakpoints of two bytes length supported");
1245 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1248 if (breakpoint
->type
== BKPT_HARD
)
1249 cortex_m
->fp_code_available
--;
1251 return cortex_m_set_breakpoint(target
, breakpoint
);
1254 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1256 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1258 /* REVISIT why check? FBP can be updated with core running ... */
1259 if (target
->state
!= TARGET_HALTED
) {
1260 LOG_WARNING("target not halted");
1261 return ERROR_TARGET_NOT_HALTED
;
1264 if (cortex_m
->auto_bp_type
)
1265 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1267 if (breakpoint
->set
)
1268 cortex_m_unset_breakpoint(target
, breakpoint
);
1270 if (breakpoint
->type
== BKPT_HARD
)
1271 cortex_m
->fp_code_available
++;
1276 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1279 uint32_t mask
, temp
;
1280 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1282 /* watchpoint params were validated earlier */
1284 temp
= watchpoint
->length
;
1291 /* REVISIT Don't fully trust these "not used" records ... users
1292 * may set up breakpoints by hand, e.g. dual-address data value
1293 * watchpoint using comparator #1; comparator #0 matching cycle
1294 * count; send data trace info through ITM and TPIU; etc
1296 struct cortex_m_dwt_comparator
*comparator
;
1298 for (comparator
= cortex_m
->dwt_comparator_list
;
1299 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1300 comparator
++, dwt_num
++)
1302 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1303 LOG_ERROR("Can not find free DWT Comparator");
1306 comparator
->used
= 1;
1307 watchpoint
->set
= dwt_num
+ 1;
1309 comparator
->comp
= watchpoint
->address
;
1310 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1313 comparator
->mask
= mask
;
1314 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1317 switch (watchpoint
->rw
) {
1319 comparator
->function
= 5;
1322 comparator
->function
= 6;
1325 comparator
->function
= 7;
1328 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1329 comparator
->function
);
1331 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1332 watchpoint
->unique_id
, dwt_num
,
1333 (unsigned) comparator
->comp
,
1334 (unsigned) comparator
->mask
,
1335 (unsigned) comparator
->function
);
1339 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1341 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1342 struct cortex_m_dwt_comparator
*comparator
;
1345 if (!watchpoint
->set
) {
1346 LOG_WARNING("watchpoint (wpid: %d) not set",
1347 watchpoint
->unique_id
);
1351 dwt_num
= watchpoint
->set
- 1;
1353 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1354 watchpoint
->unique_id
, dwt_num
,
1355 (unsigned) watchpoint
->address
);
1357 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1358 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1362 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1363 comparator
->used
= 0;
1364 comparator
->function
= 0;
1365 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1366 comparator
->function
);
1368 watchpoint
->set
= false;
1373 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1375 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1377 if (cortex_m
->dwt_comp_available
< 1) {
1378 LOG_DEBUG("no comparators?");
1379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1382 /* hardware doesn't support data value masking */
1383 if (watchpoint
->mask
!= ~(uint32_t)0) {
1384 LOG_DEBUG("watchpoint value masks not supported");
1385 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1388 /* hardware allows address masks of up to 32K */
1391 for (mask
= 0; mask
< 16; mask
++) {
1392 if ((1u << mask
) == watchpoint
->length
)
1396 LOG_DEBUG("unsupported watchpoint length");
1397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1399 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1400 LOG_DEBUG("watchpoint address is unaligned");
1401 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1404 /* Caller doesn't seem to be able to describe watching for data
1405 * values of zero; that flags "no value".
1407 * REVISIT This DWT may well be able to watch for specific data
1408 * values. Requires comparator #1 to set DATAVMATCH and match
1409 * the data, and another comparator (DATAVADDR0) matching addr.
1411 if (watchpoint
->value
) {
1412 LOG_DEBUG("data value watchpoint not YET supported");
1413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1416 cortex_m
->dwt_comp_available
--;
1417 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1422 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1424 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1426 /* REVISIT why check? DWT can be updated with core running ... */
1427 if (target
->state
!= TARGET_HALTED
) {
1428 LOG_WARNING("target not halted");
1429 return ERROR_TARGET_NOT_HALTED
;
1432 if (watchpoint
->set
)
1433 cortex_m_unset_watchpoint(target
, watchpoint
);
1435 cortex_m
->dwt_comp_available
++;
1436 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1441 void cortex_m_enable_watchpoints(struct target
*target
)
1443 struct watchpoint
*watchpoint
= target
->watchpoints
;
1445 /* set any pending watchpoints */
1446 while (watchpoint
) {
1447 if (!watchpoint
->set
)
1448 cortex_m_set_watchpoint(target
, watchpoint
);
1449 watchpoint
= watchpoint
->next
;
1453 static int cortex_m_load_core_reg_u32(struct target
*target
,
1454 uint32_t num
, uint32_t *value
)
1457 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1458 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1460 /* NOTE: we "know" here that the register identifiers used
1461 * in the v7m header match the Cortex-M3 Debug Core Register
1462 * Selector values for R0..R15, xPSR, MSP, and PSP.
1466 /* read a normal core register */
1467 retval
= cortexm_dap_read_coreregister_u32(swjdp
, value
, num
);
1469 if (retval
!= ERROR_OK
) {
1470 LOG_ERROR("JTAG failure %i", retval
);
1471 return ERROR_JTAG_DEVICE_ERROR
;
1473 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1476 case ARMV7M_PRIMASK
:
1477 case ARMV7M_BASEPRI
:
1478 case ARMV7M_FAULTMASK
:
1479 case ARMV7M_CONTROL
:
1480 /* Cortex-M3 packages these four registers as bitfields
1481 * in one Debug Core register. So say r0 and r2 docs;
1482 * it was removed from r1 docs, but still works.
1484 cortexm_dap_read_coreregister_u32(swjdp
, value
, 20);
1487 case ARMV7M_PRIMASK
:
1488 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1491 case ARMV7M_BASEPRI
:
1492 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1495 case ARMV7M_FAULTMASK
:
1496 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1499 case ARMV7M_CONTROL
:
1500 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1504 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1508 return ERROR_COMMAND_SYNTAX_ERROR
;
1514 static int cortex_m_store_core_reg_u32(struct target
*target
,
1515 uint32_t num
, uint32_t value
)
1519 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1520 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1522 /* NOTE: we "know" here that the register identifiers used
1523 * in the v7m header match the Cortex-M3 Debug Core Register
1524 * Selector values for R0..R15, xPSR, MSP, and PSP.
1528 retval
= cortexm_dap_write_coreregister_u32(swjdp
, value
, num
);
1529 if (retval
!= ERROR_OK
) {
1532 LOG_ERROR("JTAG failure");
1533 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1534 r
->dirty
= r
->valid
;
1535 return ERROR_JTAG_DEVICE_ERROR
;
1537 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1540 case ARMV7M_PRIMASK
:
1541 case ARMV7M_BASEPRI
:
1542 case ARMV7M_FAULTMASK
:
1543 case ARMV7M_CONTROL
:
1544 /* Cortex-M3 packages these four registers as bitfields
1545 * in one Debug Core register. So say r0 and r2 docs;
1546 * it was removed from r1 docs, but still works.
1548 cortexm_dap_read_coreregister_u32(swjdp
, ®
, 20);
1551 case ARMV7M_PRIMASK
:
1552 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1555 case ARMV7M_BASEPRI
:
1556 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1559 case ARMV7M_FAULTMASK
:
1560 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1563 case ARMV7M_CONTROL
:
1564 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1568 cortexm_dap_write_coreregister_u32(swjdp
, reg
, 20);
1570 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1574 return ERROR_COMMAND_SYNTAX_ERROR
;
1580 static int cortex_m_read_memory(struct target
*target
, uint32_t address
,
1581 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1583 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1584 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1586 if (armv7m
->arm
.is_armv6m
) {
1587 /* armv6m does not handle unaligned memory access */
1588 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1589 return ERROR_TARGET_UNALIGNED_ACCESS
;
1592 return mem_ap_read(swjdp
, buffer
, size
, count
, address
, true);
1595 static int cortex_m_write_memory(struct target
*target
, uint32_t address
,
1596 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1598 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1599 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1601 if (armv7m
->arm
.is_armv6m
) {
1602 /* armv6m does not handle unaligned memory access */
1603 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1604 return ERROR_TARGET_UNALIGNED_ACCESS
;
1607 return mem_ap_write(swjdp
, buffer
, size
, count
, address
, true);
1610 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1611 struct target
*target
)
1613 armv7m_build_reg_cache(target
);
1617 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1618 * on r/w if the core is not running, and clear on resume or reset ... or
1619 * at least, in a post_restore_context() method.
1622 struct dwt_reg_state
{
1623 struct target
*target
;
1625 uint32_t value
; /* scratch/cache */
1628 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1630 struct dwt_reg_state
*state
= reg
->arch_info
;
1632 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1635 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1637 struct dwt_reg_state
*state
= reg
->arch_info
;
1639 return target_write_u32(state
->target
, state
->addr
,
1640 buf_get_u32(buf
, 0, reg
->size
));
1649 static struct dwt_reg dwt_base_regs
[] = {
1650 { DWT_CTRL
, "dwt_ctrl", 32, },
1651 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1652 * increments while the core is asleep.
1654 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1655 /* plus some 8 bit counters, useful for profiling with TPIU */
1658 static struct dwt_reg dwt_comp
[] = {
1659 #define DWT_COMPARATOR(i) \
1660 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1661 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1662 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1667 #undef DWT_COMPARATOR
1670 static const struct reg_arch_type dwt_reg_type
= {
1671 .get
= cortex_m_dwt_get_reg
,
1672 .set
= cortex_m_dwt_set_reg
,
1675 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1677 struct dwt_reg_state
*state
;
1679 state
= calloc(1, sizeof *state
);
1682 state
->addr
= d
->addr
;
1687 r
->value
= &state
->value
;
1688 r
->arch_info
= state
;
1689 r
->type
= &dwt_reg_type
;
1692 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1695 struct reg_cache
*cache
;
1696 struct cortex_m_dwt_comparator
*comparator
;
1699 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1701 LOG_DEBUG("no DWT");
1705 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1706 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1707 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1708 sizeof(struct cortex_m_dwt_comparator
));
1709 if (!cm
->dwt_comparator_list
) {
1711 cm
->dwt_num_comp
= 0;
1712 LOG_ERROR("out of mem");
1716 cache
= calloc(1, sizeof *cache
);
1719 free(cm
->dwt_comparator_list
);
1722 cache
->name
= "cortex-m3 dwt registers";
1723 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1724 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1725 if (!cache
->reg_list
) {
1730 for (reg
= 0; reg
< 2; reg
++)
1731 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1732 dwt_base_regs
+ reg
);
1734 comparator
= cm
->dwt_comparator_list
;
1735 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1738 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1739 for (j
= 0; j
< 3; j
++, reg
++)
1740 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1741 dwt_comp
+ 3 * i
+ j
);
1743 /* make sure we clear any watchpoints enabled on the target */
1744 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1747 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1748 cm
->dwt_cache
= cache
;
1750 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1751 dwtcr
, cm
->dwt_num_comp
,
1752 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1754 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1755 * implement single-address data value watchpoints ... so we
1756 * won't need to check it later, when asked to set one up.
1760 #define MVFR0 0xe000ef40
1761 #define MVFR1 0xe000ef44
1763 #define MVFR0_DEFAULT_M4 0x10110021
1764 #define MVFR1_DEFAULT_M4 0x11000011
1766 int cortex_m_examine(struct target
*target
)
1769 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1771 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1772 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1773 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1775 /* stlink shares the examine handler but does not support
1777 if (!armv7m
->stlink
) {
1778 retval
= ahbap_debugport_init(swjdp
);
1779 if (retval
!= ERROR_OK
)
1783 if (!target_was_examined(target
)) {
1784 target_set_examined(target
);
1786 /* Read from Device Identification Registers */
1787 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1788 if (retval
!= ERROR_OK
)
1792 i
= (cpuid
>> 4) & 0xf;
1794 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1795 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1796 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1798 /* test for floating point feature on cortex-m4 */
1800 target_read_u32(target
, MVFR0
, &mvfr0
);
1801 target_read_u32(target
, MVFR1
, &mvfr1
);
1803 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1804 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1805 armv7m
->fp_feature
= FPv4_SP
;
1807 } else if (i
== 0) {
1808 /* Cortex-M0 does not support unaligned memory access */
1809 armv7m
->arm
.is_armv6m
= true;
1812 if (i
== 4 || i
== 3) {
1813 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1814 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1817 /* NOTE: FPB and DWT are both optional. */
1820 target_read_u32(target
, FP_CTRL
, &fpcr
);
1821 cortex_m
->auto_bp_type
= 1;
1822 /* bits [14:12] and [7:4] */
1823 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
1824 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1825 cortex_m
->fp_code_available
= cortex_m
->fp_num_code
;
1826 cortex_m
->fp_comparator_list
= calloc(
1827 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
1828 sizeof(struct cortex_m_fp_comparator
));
1829 cortex_m
->fpb_enabled
= fpcr
& 1;
1830 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
1831 cortex_m
->fp_comparator_list
[i
].type
=
1832 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1833 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1835 /* make sure we clear any breakpoints enabled on the target */
1836 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
1838 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1840 cortex_m
->fp_num_code
,
1841 cortex_m
->fp_num_lit
);
1844 cortex_m_dwt_setup(cortex_m
, target
);
1846 /* These hardware breakpoints only work for code in flash! */
1847 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1848 target_name(target
),
1849 cortex_m
->fp_num_code
,
1850 cortex_m
->dwt_num_comp
);
1856 static int cortex_m_dcc_read(struct adiv5_dap
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
1861 mem_ap_read_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 2, DCB_DCRDR
);
1862 *ctrl
= (uint8_t)dcrdr
;
1863 *value
= (uint8_t)(dcrdr
>> 8);
1865 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1867 /* write ack back to software dcc register
1868 * signify we have read data */
1869 if (dcrdr
& (1 << 0)) {
1871 retval
= mem_ap_write_buf_u16(swjdp
, (uint8_t *)&dcrdr
, 2, DCB_DCRDR
);
1872 if (retval
!= ERROR_OK
)
1879 static int cortex_m_target_request_data(struct target
*target
,
1880 uint32_t size
, uint8_t *buffer
)
1882 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1883 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1888 for (i
= 0; i
< (size
* 4); i
++) {
1889 cortex_m_dcc_read(swjdp
, &data
, &ctrl
);
1896 static int cortex_m_handle_target_request(void *priv
)
1898 struct target
*target
= priv
;
1899 if (!target_was_examined(target
))
1901 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1902 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1904 if (!target
->dbg_msg_enabled
)
1907 if (target
->state
== TARGET_RUNNING
) {
1911 cortex_m_dcc_read(swjdp
, &data
, &ctrl
);
1913 /* check if we have data */
1914 if (ctrl
& (1 << 0)) {
1917 /* we assume target is quick enough */
1919 cortex_m_dcc_read(swjdp
, &data
, &ctrl
);
1920 request
|= (data
<< 8);
1921 cortex_m_dcc_read(swjdp
, &data
, &ctrl
);
1922 request
|= (data
<< 16);
1923 cortex_m_dcc_read(swjdp
, &data
, &ctrl
);
1924 request
|= (data
<< 24);
1925 target_request(target
, request
);
1932 static int cortex_m_init_arch_info(struct target
*target
,
1933 struct cortex_m_common
*cortex_m
, struct jtag_tap
*tap
)
1936 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1938 armv7m_init_arch_info(target
, armv7m
);
1940 /* prepare JTAG information for the new target */
1941 cortex_m
->jtag_info
.tap
= tap
;
1942 cortex_m
->jtag_info
.scann_size
= 4;
1944 /* default reset mode is to use srst if fitted
1945 * if not it will use CORTEX_M3_RESET_VECTRESET */
1946 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
1948 armv7m
->arm
.dap
= &armv7m
->dap
;
1950 /* Leave (only) generic DAP stuff for debugport_init(); */
1951 armv7m
->dap
.jtag_info
= &cortex_m
->jtag_info
;
1952 armv7m
->dap
.memaccess_tck
= 8;
1954 /* Cortex-M3/M4 has 4096 bytes autoincrement range
1955 * but set a safe default to 1024 to support Cortex-M0
1956 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
1957 armv7m
->dap
.tar_autoincr_block
= (1 << 10);
1959 /* register arch-specific functions */
1960 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
1962 armv7m
->post_debug_entry
= NULL
;
1964 armv7m
->pre_restore_context
= NULL
;
1966 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
1967 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
1969 target_register_timer_callback(cortex_m_handle_target_request
, 1, 1, target
);
1971 retval
= arm_jtag_setup_connection(&cortex_m
->jtag_info
);
1972 if (retval
!= ERROR_OK
)
1978 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
1980 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
1982 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
1983 cortex_m_init_arch_info(target
, cortex_m
, target
->tap
);
1988 /*--------------------------------------------------------------------------*/
1990 static int cortex_m_verify_pointer(struct command_context
*cmd_ctx
,
1991 struct cortex_m_common
*cm
)
1993 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
1994 command_print(cmd_ctx
, "target is not a Cortex-M");
1995 return ERROR_TARGET_INVALID
;
2001 * Only stuff below this line should need to verify that its target
2002 * is a Cortex-M3. Everything else should have indirected through the
2003 * cortexm3_target structure, which is only used with CM3 targets.
2006 static const struct {
2010 { "hard_err", VC_HARDERR
, },
2011 { "int_err", VC_INTERR
, },
2012 { "bus_err", VC_BUSERR
, },
2013 { "state_err", VC_STATERR
, },
2014 { "chk_err", VC_CHKERR
, },
2015 { "nocp_err", VC_NOCPERR
, },
2016 { "mm_err", VC_MMERR
, },
2017 { "reset", VC_CORERESET
, },
2020 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2022 struct target
*target
= get_current_target(CMD_CTX
);
2023 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2024 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2025 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
2029 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2030 if (retval
!= ERROR_OK
)
2033 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2034 if (retval
!= ERROR_OK
)
2040 if (CMD_ARGC
== 1) {
2041 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2042 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2043 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2044 | VC_MMERR
| VC_CORERESET
;
2046 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2049 while (CMD_ARGC
-- > 0) {
2051 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2052 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2054 catch |= vec_ids
[i
].mask
;
2057 if (i
== ARRAY_SIZE(vec_ids
)) {
2058 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2059 return ERROR_COMMAND_SYNTAX_ERROR
;
2063 /* For now, armv7m->demcr only stores vector catch flags. */
2064 armv7m
->demcr
= catch;
2069 /* write, but don't assume it stuck (why not??) */
2070 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2071 if (retval
!= ERROR_OK
)
2073 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2074 if (retval
!= ERROR_OK
)
2077 /* FIXME be sure to clear DEMCR on clean server shutdown.
2078 * Otherwise the vector catch hardware could fire when there's
2079 * no debugger hooked up, causing much confusion...
2083 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2084 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2085 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2091 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2093 struct target
*target
= get_current_target(CMD_CTX
);
2094 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2097 static const Jim_Nvp nvp_maskisr_modes
[] = {
2098 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2099 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2100 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2101 { .name
= NULL
, .value
= -1 },
2106 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2107 if (retval
!= ERROR_OK
)
2110 if (target
->state
!= TARGET_HALTED
) {
2111 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2116 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2117 if (n
->name
== NULL
)
2118 return ERROR_COMMAND_SYNTAX_ERROR
;
2119 cortex_m
->isrmasking_mode
= n
->value
;
2122 if (cortex_m
->isrmasking_mode
== CORTEX_M_ISRMASK_ON
)
2123 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2125 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2128 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2129 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2134 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2136 struct target
*target
= get_current_target(CMD_CTX
);
2137 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2141 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2142 if (retval
!= ERROR_OK
)
2146 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2147 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2148 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2149 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2152 switch (cortex_m
->soft_reset_config
) {
2153 case CORTEX_M_RESET_SYSRESETREQ
:
2154 reset_config
= "sysresetreq";
2157 case CORTEX_M_RESET_VECTRESET
:
2158 reset_config
= "vectreset";
2162 reset_config
= "unknown";
2166 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2171 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2174 .handler
= handle_cortex_m_mask_interrupts_command
,
2175 .mode
= COMMAND_EXEC
,
2176 .help
= "mask cortex_m interrupts",
2177 .usage
= "['auto'|'on'|'off']",
2180 .name
= "vector_catch",
2181 .handler
= handle_cortex_m_vector_catch_command
,
2182 .mode
= COMMAND_EXEC
,
2183 .help
= "configure hardware vectors to trigger debug entry",
2184 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2187 .name
= "reset_config",
2188 .handler
= handle_cortex_m_reset_config_command
,
2189 .mode
= COMMAND_ANY
,
2190 .help
= "configure software reset handling",
2191 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2193 COMMAND_REGISTRATION_DONE
2195 static const struct command_registration cortex_m_command_handlers
[] = {
2197 .chain
= armv7m_command_handlers
,
2201 .mode
= COMMAND_EXEC
,
2202 .help
= "Cortex-M command group",
2204 .chain
= cortex_m_exec_command_handlers
,
2206 COMMAND_REGISTRATION_DONE
2209 struct target_type cortexm_target
= {
2211 .deprecated_name
= "cortex_m3",
2213 .poll
= cortex_m_poll
,
2214 .arch_state
= armv7m_arch_state
,
2216 .target_request_data
= cortex_m_target_request_data
,
2218 .halt
= cortex_m_halt
,
2219 .resume
= cortex_m_resume
,
2220 .step
= cortex_m_step
,
2222 .assert_reset
= cortex_m_assert_reset
,
2223 .deassert_reset
= cortex_m_deassert_reset
,
2224 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2226 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2228 .read_memory
= cortex_m_read_memory
,
2229 .write_memory
= cortex_m_write_memory
,
2230 .checksum_memory
= armv7m_checksum_memory
,
2231 .blank_check_memory
= armv7m_blank_check_memory
,
2233 .run_algorithm
= armv7m_run_algorithm
,
2234 .start_algorithm
= armv7m_start_algorithm
,
2235 .wait_algorithm
= armv7m_wait_algorithm
,
2237 .add_breakpoint
= cortex_m_add_breakpoint
,
2238 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2239 .add_watchpoint
= cortex_m_add_watchpoint
,
2240 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2242 .commands
= cortex_m_command_handlers
,
2243 .target_create
= cortex_m_target_create
,
2244 .init_target
= cortex_m_init_target
,
2245 .examine
= cortex_m_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)