jtag_tap_t -> struct jtag_tap
[openocd.git] / src / target / cortex_a8.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifndef CORTEX_A8_H
30 #define CORTEX_A8_H
31
32 #include "register.h"
33 #include "target.h"
34 #include "armv7a.h"
35 #include "arm7_9_common.h"
36
37 extern char* cortex_a8_state_strings[];
38
39 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
40
41 #define CPUID 0x54011D00
42 /* Debug Control Block */
43 #define CPUDBG_DIDR 0x000
44 #define CPUDBG_WFAR 0x018
45 #define CPUDBG_VCR 0x01C
46 #define CPUDBG_ECR 0x024
47 #define CPUDBG_DSCCR 0x028
48 #define CPUDBG_DTRRX 0x080
49 #define CPUDBG_ITR 0x084
50 #define CPUDBG_DSCR 0x088
51 #define CPUDBG_DTRTX 0x08c
52 #define CPUDBG_DRCR 0x090
53 #define CPUDBG_BVR_BASE 0x100
54 #define CPUDBG_BCR_BASE 0x140
55 #define CPUDBG_WVR_BASE 0x180
56 #define CPUDBG_WCR_BASE 0x1C0
57
58 #define CPUDBG_OSLAR 0x300
59 #define CPUDBG_OSLSR 0x304
60 #define CPUDBG_OSSRR 0x308
61
62 #define CPUDBG_PRCR 0x310
63 #define CPUDBG_PRSR 0x314
64
65 #define CPUDBG_CPUID 0xD00
66 #define CPUDBG_CTYPR 0xD04
67 #define CPUDBG_TTYPR 0xD0C
68 #define CPUDBG_LOCKACCESS 0xFB0
69 #define CPUDBG_LOCKSTATUS 0xFB4
70 #define CPUDBG_AUTHSTATUS 0xFB8
71
72 #define BRP_NORMAL 0
73 #define BRP_CONTEXT 1
74
75 /* DSCR Bit offset */
76 #define DSCR_CORE_HALTED 0
77 #define DSCR_CORE_RESTARTED 1
78 #define DSCR_EXT_INT_EN 13
79 #define DSCR_HALT_DBG_MODE 14
80 #define DSCR_MON_DBG_MODE 15
81 #define DSCR_INSTR_COMP 24
82 #define DSCR_DTR_TX_FULL 29
83 #define DSCR_DTR_RX_FULL 30
84
85 typedef struct cortex_a8_brp_s
86 {
87 int used;
88 int type;
89 uint32_t value;
90 uint32_t control;
91 uint8_t BRPn;
92 } cortex_a8_brp_t;
93
94 typedef struct cortex_a8_wrp_s
95 {
96 int used;
97 int type;
98 uint32_t value;
99 uint32_t control;
100 uint8_t WRPn;
101 } cortex_a8_wrp_t;
102
103 typedef struct cortex_a8_common_s
104 {
105 int common_magic;
106 arm_jtag_t jtag_info;
107
108 /* Context information */
109 uint32_t cpudbg_dscr;
110 uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
111 uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
112
113 /* Saved cp15 registers */
114 uint32_t cp15_control_reg;
115 uint32_t cp15_aux_control_reg;
116
117 /* Breakpoint register pairs */
118 int brp_num_context;
119 int brp_num;
120 int brp_num_available;
121 // int brp_enabled;
122 cortex_a8_brp_t *brp_list;
123
124 /* Watchpoint register pairs */
125 int wrp_num;
126 int wrp_num_available;
127 cortex_a8_wrp_t *wrp_list;
128
129 /* Interrupts */
130 int intlinesnum;
131 uint32_t *intsetenable;
132
133 /* Use cortex_a8_read_regs_through_mem for fast register reads */
134 int fast_reg_read;
135
136 armv7a_common_t armv7a_common;
137 } cortex_a8_common_t;
138
139 static inline struct cortex_a8_common_s *
140 target_to_cortex_a8(struct target_s *target)
141 {
142 return container_of(target->arch_info, struct cortex_a8_common_s,
143 armv7a_common.armv4_5_common);
144 }
145
146 int cortex_a8_init_arch_info(target_t *target,
147 cortex_a8_common_t *cortex_a8, struct jtag_tap *tap);
148
149 #endif /* CORTEX_A8_H */