build: cleanup src/target directory
[openocd.git] / src / target / cortex_a.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29
30 #ifndef CORTEX_A8_H
31 #define CORTEX_A8_H
32
33 #include "armv7a.h"
34
35 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
36
37 #define CPUDBG_CPUID 0xD00
38 #define CPUDBG_CTYPR 0xD04
39 #define CPUDBG_TTYPR 0xD0C
40 #define CPUDBG_LOCKACCESS 0xFB0
41 #define CPUDBG_LOCKSTATUS 0xFB4
42
43 #define BRP_NORMAL 0
44 #define BRP_CONTEXT 1
45
46 #define CORTEX_A8_PADDRDBG_CPU_SHIFT 13
47
48 struct cortex_a8_brp {
49 int used;
50 int type;
51 uint32_t value;
52 uint32_t control;
53 uint8_t BRPn;
54 };
55
56 struct cortex_a8_common {
57 int common_magic;
58 struct arm_jtag jtag_info;
59
60 /* Context information */
61 uint32_t cpudbg_dscr;
62
63 /* Saved cp15 registers */
64 uint32_t cp15_control_reg;
65 /* latest cp15 register value written and cpsr processor mode */
66 uint32_t cp15_control_reg_curr;
67 enum arm_mode curr_mode;
68
69
70 /* Breakpoint register pairs */
71 int brp_num_context;
72 int brp_num;
73 int brp_num_available;
74 struct cortex_a8_brp *brp_list;
75
76 /* Use cortex_a8_read_regs_through_mem for fast register reads */
77 int fast_reg_read;
78
79 struct armv7a_common armv7a_common;
80
81 };
82
83 static inline struct cortex_a8_common *
84 target_to_cortex_a8(struct target *target)
85 {
86 return container_of(target->arch_info, struct cortex_a8_common, armv7a_common.arm);
87 }
88
89 #endif /* CORTEX_A8_H */