1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
77 static int cortex_a_virt2phys(struct target
*target
,
78 uint32_t virt
, uint32_t *phys
);
79 static int cortex_a_read_cpu_memory(struct target
*target
,
80 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
83 /* restore cp15_control_reg at resume */
84 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
86 int retval
= ERROR_OK
;
87 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
88 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
90 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
91 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
92 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
93 retval
= armv7a
->arm
.mcr(target
, 15,
96 cortex_a
->cp15_control_reg
);
102 * Set up ARM core for memory access.
103 * If !phys_access, switch to SVC mode and make sure MMU is on
104 * If phys_access, switch off mmu
106 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
108 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
109 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
112 if (phys_access
== 0) {
113 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
114 cortex_a_mmu(target
, &mmu_enabled
);
116 cortex_a_mmu_modify(target
, 1);
117 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
118 /* overwrite DACR to all-manager */
119 armv7a
->arm
.mcr(target
, 15,
124 cortex_a_mmu(target
, &mmu_enabled
);
126 cortex_a_mmu_modify(target
, 0);
132 * Restore ARM core after memory access.
133 * If !phys_access, switch to previous mode
134 * If phys_access, restore MMU setting
136 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
138 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
139 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
141 if (phys_access
== 0) {
142 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
144 armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_dacr_reg
);
148 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
151 cortex_a_mmu(target
, &mmu_enabled
);
153 cortex_a_mmu_modify(target
, 1);
159 /* modify cp15_control_reg in order to enable or disable mmu for :
160 * - virt2phys address conversion
161 * - read or write memory in phys or virt address */
162 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
164 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
165 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
166 int retval
= ERROR_OK
;
170 /* if mmu enabled at target stop and mmu not enable */
171 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
172 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
175 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
176 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
180 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
181 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
187 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
188 enable
? "enable mmu" : "disable mmu",
189 cortex_a
->cp15_control_reg_curr
);
191 retval
= armv7a
->arm
.mcr(target
, 15,
194 cortex_a
->cp15_control_reg_curr
);
200 * Cortex-A Basic debug access, very low level assumes state is saved
202 static int cortex_a_init_debug_access(struct target
*target
)
204 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
207 /* lock memory-mapped access to debug registers to prevent
208 * software interference */
209 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
210 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0);
211 if (retval
!= ERROR_OK
)
214 /* Disable cacheline fills and force cache write-through in debug state */
215 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
216 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
217 if (retval
!= ERROR_OK
)
220 /* Disable TLB lookup and refill/eviction in debug state */
221 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
222 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
223 if (retval
!= ERROR_OK
)
226 /* Enabling of instruction execution in debug mode is done in debug_entry code */
228 /* Resync breakpoint registers */
230 /* Since this is likely called from init or reset, update target state information*/
231 return cortex_a_poll(target
);
234 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
236 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
237 * Writes final value of DSCR into *dscr. Pass force to force always
238 * reading DSCR at least once. */
239 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
240 int64_t then
= timeval_ms();
241 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
243 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
244 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
245 if (retval
!= ERROR_OK
) {
246 LOG_ERROR("Could not read DSCR register");
249 if (timeval_ms() > then
+ 1000) {
250 LOG_ERROR("Timeout waiting for InstrCompl=1");
257 /* To reduce needless round-trips, pass in a pointer to the current
258 * DSCR value. Initialize it to zero if you just need to know the
259 * value on return from this function; or DSCR_INSTR_COMP if you
260 * happen to know that no instruction is pending.
262 static int cortex_a_exec_opcode(struct target
*target
,
263 uint32_t opcode
, uint32_t *dscr_p
)
267 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
269 dscr
= dscr_p
? *dscr_p
: 0;
271 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
273 /* Wait for InstrCompl bit to be set */
274 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
275 if (retval
!= ERROR_OK
)
278 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
279 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
280 if (retval
!= ERROR_OK
)
283 int64_t then
= timeval_ms();
285 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
286 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
287 if (retval
!= ERROR_OK
) {
288 LOG_ERROR("Could not read DSCR register");
291 if (timeval_ms() > then
+ 1000) {
292 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
295 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
303 /**************************************************************************
304 Read core register with very few exec_opcode, fast but needs work_area.
305 This can cause problems with MMU active.
306 **************************************************************************/
307 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
310 int retval
= ERROR_OK
;
311 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
313 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
314 if (retval
!= ERROR_OK
)
316 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
317 if (retval
!= ERROR_OK
)
319 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
320 if (retval
!= ERROR_OK
)
323 retval
= mem_ap_read_buf(armv7a
->memory_ap
,
324 (uint8_t *)(®file
[1]), 4, 15, address
);
329 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
330 uint32_t *value
, int regnum
)
332 int retval
= ERROR_OK
;
333 uint8_t reg
= regnum
&0xFF;
335 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
341 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
342 retval
= cortex_a_exec_opcode(target
,
343 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
345 if (retval
!= ERROR_OK
)
347 } else if (reg
== 15) {
348 /* "MOV r0, r15"; then move r0 to DCCTX */
349 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
350 if (retval
!= ERROR_OK
)
352 retval
= cortex_a_exec_opcode(target
,
353 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
355 if (retval
!= ERROR_OK
)
358 /* "MRS r0, CPSR" or "MRS r0, SPSR"
359 * then move r0 to DCCTX
361 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
362 if (retval
!= ERROR_OK
)
364 retval
= cortex_a_exec_opcode(target
,
365 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
367 if (retval
!= ERROR_OK
)
371 /* Wait for DTRRXfull then read DTRRTX */
372 int64_t then
= timeval_ms();
373 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
374 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
375 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
376 if (retval
!= ERROR_OK
)
378 if (timeval_ms() > then
+ 1000) {
379 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
384 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
385 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
386 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
391 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
392 uint32_t value
, int regnum
)
394 int retval
= ERROR_OK
;
395 uint8_t Rd
= regnum
&0xFF;
397 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
399 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
401 /* Check that DCCRX is not full */
402 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
403 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
404 if (retval
!= ERROR_OK
)
406 if (dscr
& DSCR_DTR_RX_FULL
) {
407 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
408 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
409 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
411 if (retval
!= ERROR_OK
)
418 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
419 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
420 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
421 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
422 if (retval
!= ERROR_OK
)
426 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
427 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
430 if (retval
!= ERROR_OK
)
432 } else if (Rd
== 15) {
433 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
436 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
438 if (retval
!= ERROR_OK
)
440 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
441 if (retval
!= ERROR_OK
)
444 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
445 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
447 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
449 if (retval
!= ERROR_OK
)
451 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
453 if (retval
!= ERROR_OK
)
456 /* "Prefetch flush" after modifying execution status in CPSR */
458 retval
= cortex_a_exec_opcode(target
,
459 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
461 if (retval
!= ERROR_OK
)
469 /* Write to memory mapped registers directly with no cache or mmu handling */
470 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
475 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
477 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
483 * Cortex-A implementation of Debug Programmer's Model
485 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
486 * so there's no need to poll for it before executing an instruction.
488 * NOTE that in several of these cases the "stall" mode might be useful.
489 * It'd let us queue a few operations together... prepare/finish might
490 * be the places to enable/disable that mode.
493 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
495 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
498 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
500 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
501 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
502 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
505 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
508 uint32_t dscr
= DSCR_INSTR_COMP
;
514 /* Wait for DTRRXfull */
515 int64_t then
= timeval_ms();
516 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
517 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
518 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
520 if (retval
!= ERROR_OK
)
522 if (timeval_ms() > then
+ 1000) {
523 LOG_ERROR("Timeout waiting for read dcc");
528 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
529 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
530 if (retval
!= ERROR_OK
)
532 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
540 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
542 struct cortex_a_common
*a
= dpm_to_a(dpm
);
546 /* set up invariant: INSTR_COMP is set after ever DPM operation */
547 int64_t then
= timeval_ms();
549 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
550 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
552 if (retval
!= ERROR_OK
)
554 if ((dscr
& DSCR_INSTR_COMP
) != 0)
556 if (timeval_ms() > then
+ 1000) {
557 LOG_ERROR("Timeout waiting for dpm prepare");
562 /* this "should never happen" ... */
563 if (dscr
& DSCR_DTR_RX_FULL
) {
564 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
566 retval
= cortex_a_exec_opcode(
567 a
->armv7a_common
.arm
.target
,
568 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
570 if (retval
!= ERROR_OK
)
577 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
579 /* REVISIT what could be done here? */
583 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
584 uint32_t opcode
, uint32_t data
)
586 struct cortex_a_common
*a
= dpm_to_a(dpm
);
588 uint32_t dscr
= DSCR_INSTR_COMP
;
590 retval
= cortex_a_write_dcc(a
, data
);
591 if (retval
!= ERROR_OK
)
594 return cortex_a_exec_opcode(
595 a
->armv7a_common
.arm
.target
,
600 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
601 uint32_t opcode
, uint32_t data
)
603 struct cortex_a_common
*a
= dpm_to_a(dpm
);
604 uint32_t dscr
= DSCR_INSTR_COMP
;
607 retval
= cortex_a_write_dcc(a
, data
);
608 if (retval
!= ERROR_OK
)
611 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
612 retval
= cortex_a_exec_opcode(
613 a
->armv7a_common
.arm
.target
,
614 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
616 if (retval
!= ERROR_OK
)
619 /* then the opcode, taking data from R0 */
620 retval
= cortex_a_exec_opcode(
621 a
->armv7a_common
.arm
.target
,
628 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
630 struct target
*target
= dpm
->arm
->target
;
631 uint32_t dscr
= DSCR_INSTR_COMP
;
633 /* "Prefetch flush" after modifying execution status in CPSR */
634 return cortex_a_exec_opcode(target
,
635 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
639 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
640 uint32_t opcode
, uint32_t *data
)
642 struct cortex_a_common
*a
= dpm_to_a(dpm
);
644 uint32_t dscr
= DSCR_INSTR_COMP
;
646 /* the opcode, writing data to DCC */
647 retval
= cortex_a_exec_opcode(
648 a
->armv7a_common
.arm
.target
,
651 if (retval
!= ERROR_OK
)
654 return cortex_a_read_dcc(a
, data
, &dscr
);
658 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
659 uint32_t opcode
, uint32_t *data
)
661 struct cortex_a_common
*a
= dpm_to_a(dpm
);
662 uint32_t dscr
= DSCR_INSTR_COMP
;
665 /* the opcode, writing data to R0 */
666 retval
= cortex_a_exec_opcode(
667 a
->armv7a_common
.arm
.target
,
670 if (retval
!= ERROR_OK
)
673 /* write R0 to DCC */
674 retval
= cortex_a_exec_opcode(
675 a
->armv7a_common
.arm
.target
,
676 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
678 if (retval
!= ERROR_OK
)
681 return cortex_a_read_dcc(a
, data
, &dscr
);
684 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
685 uint32_t addr
, uint32_t control
)
687 struct cortex_a_common
*a
= dpm_to_a(dpm
);
688 uint32_t vr
= a
->armv7a_common
.debug_base
;
689 uint32_t cr
= a
->armv7a_common
.debug_base
;
693 case 0 ... 15: /* breakpoints */
694 vr
+= CPUDBG_BVR_BASE
;
695 cr
+= CPUDBG_BCR_BASE
;
697 case 16 ... 31: /* watchpoints */
698 vr
+= CPUDBG_WVR_BASE
;
699 cr
+= CPUDBG_WCR_BASE
;
708 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
709 (unsigned) vr
, (unsigned) cr
);
711 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
713 if (retval
!= ERROR_OK
)
715 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
720 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
722 struct cortex_a_common
*a
= dpm_to_a(dpm
);
727 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
730 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
738 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
740 /* clear control register */
741 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
744 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
746 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
749 dpm
->arm
= &a
->armv7a_common
.arm
;
752 dpm
->prepare
= cortex_a_dpm_prepare
;
753 dpm
->finish
= cortex_a_dpm_finish
;
755 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
756 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
757 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
759 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
760 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
762 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
763 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
765 retval
= arm_dpm_setup(dpm
);
766 if (retval
== ERROR_OK
)
767 retval
= arm_dpm_initialize(dpm
);
771 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
773 struct target_list
*head
;
777 while (head
!= (struct target_list
*)NULL
) {
779 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
785 static int cortex_a_halt(struct target
*target
);
787 static int cortex_a_halt_smp(struct target
*target
)
790 struct target_list
*head
;
793 while (head
!= (struct target_list
*)NULL
) {
795 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
796 && target_was_examined(curr
))
797 retval
+= cortex_a_halt(curr
);
803 static int update_halt_gdb(struct target
*target
)
806 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
807 target
->gdb_service
->target
= target
;
808 target
->gdb_service
->core
[0] = target
->coreid
;
809 retval
+= cortex_a_halt_smp(target
);
815 * Cortex-A Run control
818 static int cortex_a_poll(struct target
*target
)
820 int retval
= ERROR_OK
;
822 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
823 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
824 enum target_state prev_target_state
= target
->state
;
825 /* toggle to another core is done by gdb as follow */
826 /* maint packet J core_id */
828 /* the next polling trigger an halt event sent to gdb */
829 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
830 (target
->gdb_service
) &&
831 (target
->gdb_service
->target
== NULL
)) {
832 target
->gdb_service
->target
=
833 get_cortex_a(target
, target
->gdb_service
->core
[1]);
834 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
837 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
838 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
839 if (retval
!= ERROR_OK
)
841 cortex_a
->cpudbg_dscr
= dscr
;
843 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
844 if (prev_target_state
!= TARGET_HALTED
) {
845 /* We have a halting debug event */
846 LOG_DEBUG("Target halted");
847 target
->state
= TARGET_HALTED
;
848 if ((prev_target_state
== TARGET_RUNNING
)
849 || (prev_target_state
== TARGET_UNKNOWN
)
850 || (prev_target_state
== TARGET_RESET
)) {
851 retval
= cortex_a_debug_entry(target
);
852 if (retval
!= ERROR_OK
)
855 retval
= update_halt_gdb(target
);
856 if (retval
!= ERROR_OK
)
860 if (arm_semihosting(target
, &retval
) != 0)
863 target_call_event_callbacks(target
,
864 TARGET_EVENT_HALTED
);
866 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
869 retval
= cortex_a_debug_entry(target
);
870 if (retval
!= ERROR_OK
)
873 retval
= update_halt_gdb(target
);
874 if (retval
!= ERROR_OK
)
878 target_call_event_callbacks(target
,
879 TARGET_EVENT_DEBUG_HALTED
);
882 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
883 target
->state
= TARGET_RUNNING
;
885 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
886 target
->state
= TARGET_UNKNOWN
;
892 static int cortex_a_halt(struct target
*target
)
894 int retval
= ERROR_OK
;
896 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
899 * Tell the core to be halted by writing DRCR with 0x1
900 * and then wait for the core to be halted.
902 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
903 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
904 if (retval
!= ERROR_OK
)
908 * enter halting debug mode
910 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
911 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
912 if (retval
!= ERROR_OK
)
915 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
916 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
917 if (retval
!= ERROR_OK
)
920 int64_t then
= timeval_ms();
922 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
923 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
924 if (retval
!= ERROR_OK
)
926 if ((dscr
& DSCR_CORE_HALTED
) != 0)
928 if (timeval_ms() > then
+ 1000) {
929 LOG_ERROR("Timeout waiting for halt");
934 target
->debug_reason
= DBG_REASON_DBGRQ
;
939 static int cortex_a_internal_restore(struct target
*target
, int current
,
940 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
942 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
943 struct arm
*arm
= &armv7a
->arm
;
947 if (!debug_execution
)
948 target_free_all_working_areas(target
);
951 if (debug_execution
) {
952 /* Disable interrupts */
953 /* We disable interrupts in the PRIMASK register instead of
954 * masking with C_MASKINTS,
955 * This is probably the same issue as Cortex-M3 Errata 377493:
956 * C_MASKINTS in parallel with disabled interrupts can cause
957 * local faults to not be taken. */
958 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
959 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
960 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
962 /* Make sure we are in Thumb mode */
963 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
964 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
966 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
967 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
971 /* current = 1: continue on current pc, otherwise continue at <address> */
972 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
974 resume_pc
= *address
;
976 *address
= resume_pc
;
978 /* Make sure that the Armv7 gdb thumb fixups does not
979 * kill the return address
981 switch (arm
->core_state
) {
983 resume_pc
&= 0xFFFFFFFC;
985 case ARM_STATE_THUMB
:
986 case ARM_STATE_THUMB_EE
:
987 /* When the return address is loaded into PC
988 * bit 0 must be 1 to stay in Thumb state
992 case ARM_STATE_JAZELLE
:
993 LOG_ERROR("How do I resume into Jazelle state??");
996 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
997 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1001 /* restore dpm_mode at system halt */
1002 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1003 /* called it now before restoring context because it uses cpu
1004 * register r0 for restoring cp15 control register */
1005 retval
= cortex_a_restore_cp15_control_reg(target
);
1006 if (retval
!= ERROR_OK
)
1008 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1009 if (retval
!= ERROR_OK
)
1011 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1012 target
->state
= TARGET_RUNNING
;
1014 /* registers are now invalid */
1015 register_cache_invalidate(arm
->core_cache
);
1018 /* the front-end may request us not to handle breakpoints */
1019 if (handle_breakpoints
) {
1020 /* Single step past breakpoint at current address */
1021 breakpoint
= breakpoint_find(target
, resume_pc
);
1023 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1024 cortex_m3_unset_breakpoint(target
, breakpoint
);
1025 cortex_m3_single_step_core(target
);
1026 cortex_m3_set_breakpoint(target
, breakpoint
);
1034 static int cortex_a_internal_restart(struct target
*target
)
1036 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1037 struct arm
*arm
= &armv7a
->arm
;
1041 * * Restart core and wait for it to be started. Clear ITRen and sticky
1042 * * exception flags: see ARMv7 ARM, C5.9.
1044 * REVISIT: for single stepping, we probably want to
1045 * disable IRQs by default, with optional override...
1048 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1049 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1050 if (retval
!= ERROR_OK
)
1053 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1054 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1056 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1057 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1058 if (retval
!= ERROR_OK
)
1061 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1062 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1063 DRCR_CLEAR_EXCEPTIONS
);
1064 if (retval
!= ERROR_OK
)
1067 int64_t then
= timeval_ms();
1069 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1070 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1071 if (retval
!= ERROR_OK
)
1073 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1075 if (timeval_ms() > then
+ 1000) {
1076 LOG_ERROR("Timeout waiting for resume");
1081 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1082 target
->state
= TARGET_RUNNING
;
1084 /* registers are now invalid */
1085 register_cache_invalidate(arm
->core_cache
);
1090 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1093 struct target_list
*head
;
1094 struct target
*curr
;
1096 head
= target
->head
;
1097 while (head
!= (struct target_list
*)NULL
) {
1098 curr
= head
->target
;
1099 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
1100 && target_was_examined(curr
)) {
1101 /* resume current address , not in step mode */
1102 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1103 handle_breakpoints
, 0);
1104 retval
+= cortex_a_internal_restart(curr
);
1112 static int cortex_a_resume(struct target
*target
, int current
,
1113 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1116 /* dummy resume for smp toggle in order to reduce gdb impact */
1117 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1118 /* simulate a start and halt of target */
1119 target
->gdb_service
->target
= NULL
;
1120 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1121 /* fake resume at next poll we play the target core[1], see poll*/
1122 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1125 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1127 target
->gdb_service
->core
[0] = -1;
1128 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1129 if (retval
!= ERROR_OK
)
1132 cortex_a_internal_restart(target
);
1134 if (!debug_execution
) {
1135 target
->state
= TARGET_RUNNING
;
1136 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1137 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1139 target
->state
= TARGET_DEBUG_RUNNING
;
1140 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1141 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1147 static int cortex_a_debug_entry(struct target
*target
)
1150 uint32_t regfile
[16], cpsr
, spsr
, dscr
;
1151 int retval
= ERROR_OK
;
1152 struct working_area
*regfile_working_area
= NULL
;
1153 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1154 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1155 struct arm
*arm
= &armv7a
->arm
;
1158 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1160 /* REVISIT surely we should not re-read DSCR !! */
1161 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1162 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1163 if (retval
!= ERROR_OK
)
1166 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1167 * imprecise data aborts get discarded by issuing a Data
1168 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1171 /* Enable the ITR execution once we are in debug mode */
1172 dscr
|= DSCR_ITR_EN
;
1173 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1174 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1175 if (retval
!= ERROR_OK
)
1178 /* Examine debug reason */
1179 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1181 /* save address of instruction that triggered the watchpoint? */
1182 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1185 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1186 armv7a
->debug_base
+ CPUDBG_WFAR
,
1188 if (retval
!= ERROR_OK
)
1190 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1193 /* REVISIT fast_reg_read is never set ... */
1195 /* Examine target state and mode */
1196 if (cortex_a
->fast_reg_read
)
1197 target_alloc_working_area(target
, 64, ®file_working_area
);
1200 /* First load register acessible through core debug port*/
1201 if (!regfile_working_area
)
1202 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1204 retval
= cortex_a_read_regs_through_mem(target
,
1205 regfile_working_area
->address
, regfile
);
1207 target_free_working_area(target
, regfile_working_area
);
1208 if (retval
!= ERROR_OK
)
1211 /* read Current PSR */
1212 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1213 /* store current cpsr */
1214 if (retval
!= ERROR_OK
)
1217 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1219 arm_set_cpsr(arm
, cpsr
);
1222 for (i
= 0; i
<= ARM_PC
; i
++) {
1223 reg
= arm_reg_current(arm
, i
);
1225 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1230 /* Fixup PC Resume Address */
1231 if (cpsr
& (1 << 5)) {
1232 /* T bit set for Thumb or ThumbEE state */
1233 regfile
[ARM_PC
] -= 4;
1236 regfile
[ARM_PC
] -= 8;
1240 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1241 reg
->dirty
= reg
->valid
;
1245 /* read Saved PSR */
1246 retval
= cortex_a_dap_read_coreregister_u32(target
, &spsr
, 17);
1247 /* store current spsr */
1248 if (retval
!= ERROR_OK
)
1252 buf_set_u32(reg
->value
, 0, 32, spsr
);
1258 /* TODO, Move this */
1259 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1260 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1261 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1263 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1264 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1266 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1267 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1270 /* Are we in an exception handler */
1271 /* armv4_5->exception_number = 0; */
1272 if (armv7a
->post_debug_entry
) {
1273 retval
= armv7a
->post_debug_entry(target
);
1274 if (retval
!= ERROR_OK
)
1281 static int cortex_a_post_debug_entry(struct target
*target
)
1283 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1284 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1287 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1288 retval
= armv7a
->arm
.mrc(target
, 15,
1289 0, 0, /* op1, op2 */
1290 1, 0, /* CRn, CRm */
1291 &cortex_a
->cp15_control_reg
);
1292 if (retval
!= ERROR_OK
)
1294 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1295 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1297 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1298 armv7a_identify_cache(target
);
1300 if (armv7a
->is_armv7r
) {
1301 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1303 armv7a
->armv7a_mmu
.mmu_enabled
=
1304 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1306 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1307 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1308 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1309 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1310 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1312 /* switch to SVC mode to read DACR */
1313 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1314 armv7a
->arm
.mrc(target
, 15,
1316 &cortex_a
->cp15_dacr_reg
);
1318 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1319 cortex_a
->cp15_dacr_reg
);
1321 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1325 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1327 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1331 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1332 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1333 if (ERROR_OK
!= retval
)
1336 /* clear bitfield */
1339 dscr
|= value
& bit_mask
;
1341 /* write new DSCR */
1342 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1343 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1347 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1348 int handle_breakpoints
)
1350 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1351 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1352 struct arm
*arm
= &armv7a
->arm
;
1353 struct breakpoint
*breakpoint
= NULL
;
1354 struct breakpoint stepbreakpoint
;
1358 if (target
->state
!= TARGET_HALTED
) {
1359 LOG_WARNING("target not halted");
1360 return ERROR_TARGET_NOT_HALTED
;
1363 /* current = 1: continue on current pc, otherwise continue at <address> */
1366 buf_set_u32(r
->value
, 0, 32, address
);
1368 address
= buf_get_u32(r
->value
, 0, 32);
1370 /* The front-end may request us not to handle breakpoints.
1371 * But since Cortex-A uses breakpoint for single step,
1372 * we MUST handle breakpoints.
1374 handle_breakpoints
= 1;
1375 if (handle_breakpoints
) {
1376 breakpoint
= breakpoint_find(target
, address
);
1378 cortex_a_unset_breakpoint(target
, breakpoint
);
1381 /* Setup single step breakpoint */
1382 stepbreakpoint
.address
= address
;
1383 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1385 stepbreakpoint
.type
= BKPT_HARD
;
1386 stepbreakpoint
.set
= 0;
1388 /* Disable interrupts during single step if requested */
1389 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1390 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1391 if (ERROR_OK
!= retval
)
1395 /* Break on IVA mismatch */
1396 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1398 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1400 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1401 if (retval
!= ERROR_OK
)
1404 int64_t then
= timeval_ms();
1405 while (target
->state
!= TARGET_HALTED
) {
1406 retval
= cortex_a_poll(target
);
1407 if (retval
!= ERROR_OK
)
1409 if (timeval_ms() > then
+ 1000) {
1410 LOG_ERROR("timeout waiting for target halt");
1415 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1417 /* Re-enable interrupts if they were disabled */
1418 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1419 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1420 if (ERROR_OK
!= retval
)
1425 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1428 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1430 if (target
->state
!= TARGET_HALTED
)
1431 LOG_DEBUG("target stepped");
1436 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1438 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1442 if (armv7a
->pre_restore_context
)
1443 armv7a
->pre_restore_context(target
);
1445 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1449 * Cortex-A Breakpoint and watchpoint functions
1452 /* Setup hardware Breakpoint Register Pair */
1453 static int cortex_a_set_breakpoint(struct target
*target
,
1454 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1459 uint8_t byte_addr_select
= 0x0F;
1460 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1461 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1462 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1464 if (breakpoint
->set
) {
1465 LOG_WARNING("breakpoint already set");
1469 if (breakpoint
->type
== BKPT_HARD
) {
1470 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1472 if (brp_i
>= cortex_a
->brp_num
) {
1473 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1474 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1476 breakpoint
->set
= brp_i
+ 1;
1477 if (breakpoint
->length
== 2)
1478 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1479 control
= ((matchmode
& 0x7) << 20)
1480 | (byte_addr_select
<< 5)
1482 brp_list
[brp_i
].used
= 1;
1483 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1484 brp_list
[brp_i
].control
= control
;
1485 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1486 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1487 brp_list
[brp_i
].value
);
1488 if (retval
!= ERROR_OK
)
1490 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1491 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1492 brp_list
[brp_i
].control
);
1493 if (retval
!= ERROR_OK
)
1495 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1496 brp_list
[brp_i
].control
,
1497 brp_list
[brp_i
].value
);
1498 } else if (breakpoint
->type
== BKPT_SOFT
) {
1500 if (breakpoint
->length
== 2)
1501 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1503 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1504 retval
= target_read_memory(target
,
1505 breakpoint
->address
& 0xFFFFFFFE,
1506 breakpoint
->length
, 1,
1507 breakpoint
->orig_instr
);
1508 if (retval
!= ERROR_OK
)
1511 /* make sure data cache is cleaned & invalidated down to PoC */
1512 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1513 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1514 breakpoint
->length
);
1517 retval
= target_write_memory(target
,
1518 breakpoint
->address
& 0xFFFFFFFE,
1519 breakpoint
->length
, 1, code
);
1520 if (retval
!= ERROR_OK
)
1523 /* update i-cache at breakpoint location */
1524 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1525 breakpoint
->length
);
1526 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1527 breakpoint
->length
);
1529 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1535 static int cortex_a_set_context_breakpoint(struct target
*target
,
1536 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1538 int retval
= ERROR_FAIL
;
1541 uint8_t byte_addr_select
= 0x0F;
1542 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1543 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1544 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1546 if (breakpoint
->set
) {
1547 LOG_WARNING("breakpoint already set");
1550 /*check available context BRPs*/
1551 while ((brp_list
[brp_i
].used
||
1552 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1555 if (brp_i
>= cortex_a
->brp_num
) {
1556 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1560 breakpoint
->set
= brp_i
+ 1;
1561 control
= ((matchmode
& 0x7) << 20)
1562 | (byte_addr_select
<< 5)
1564 brp_list
[brp_i
].used
= 1;
1565 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1566 brp_list
[brp_i
].control
= control
;
1567 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1568 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1569 brp_list
[brp_i
].value
);
1570 if (retval
!= ERROR_OK
)
1572 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1573 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1574 brp_list
[brp_i
].control
);
1575 if (retval
!= ERROR_OK
)
1577 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1578 brp_list
[brp_i
].control
,
1579 brp_list
[brp_i
].value
);
1584 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1586 int retval
= ERROR_FAIL
;
1587 int brp_1
= 0; /* holds the contextID pair */
1588 int brp_2
= 0; /* holds the IVA pair */
1589 uint32_t control_CTX
, control_IVA
;
1590 uint8_t CTX_byte_addr_select
= 0x0F;
1591 uint8_t IVA_byte_addr_select
= 0x0F;
1592 uint8_t CTX_machmode
= 0x03;
1593 uint8_t IVA_machmode
= 0x01;
1594 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1595 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1596 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1598 if (breakpoint
->set
) {
1599 LOG_WARNING("breakpoint already set");
1602 /*check available context BRPs*/
1603 while ((brp_list
[brp_1
].used
||
1604 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1607 printf("brp(CTX) found num: %d\n", brp_1
);
1608 if (brp_1
>= cortex_a
->brp_num
) {
1609 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1613 while ((brp_list
[brp_2
].used
||
1614 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1617 printf("brp(IVA) found num: %d\n", brp_2
);
1618 if (brp_2
>= cortex_a
->brp_num
) {
1619 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1623 breakpoint
->set
= brp_1
+ 1;
1624 breakpoint
->linked_BRP
= brp_2
;
1625 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1628 | (CTX_byte_addr_select
<< 5)
1630 brp_list
[brp_1
].used
= 1;
1631 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1632 brp_list
[brp_1
].control
= control_CTX
;
1633 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1634 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1635 brp_list
[brp_1
].value
);
1636 if (retval
!= ERROR_OK
)
1638 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1639 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1640 brp_list
[brp_1
].control
);
1641 if (retval
!= ERROR_OK
)
1644 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1646 | (IVA_byte_addr_select
<< 5)
1648 brp_list
[brp_2
].used
= 1;
1649 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1650 brp_list
[brp_2
].control
= control_IVA
;
1651 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1652 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1653 brp_list
[brp_2
].value
);
1654 if (retval
!= ERROR_OK
)
1656 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1657 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1658 brp_list
[brp_2
].control
);
1659 if (retval
!= ERROR_OK
)
1665 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1668 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1669 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1670 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1672 if (!breakpoint
->set
) {
1673 LOG_WARNING("breakpoint not set");
1677 if (breakpoint
->type
== BKPT_HARD
) {
1678 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1679 int brp_i
= breakpoint
->set
- 1;
1680 int brp_j
= breakpoint
->linked_BRP
;
1681 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1682 LOG_DEBUG("Invalid BRP number in breakpoint");
1685 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1686 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1687 brp_list
[brp_i
].used
= 0;
1688 brp_list
[brp_i
].value
= 0;
1689 brp_list
[brp_i
].control
= 0;
1690 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1691 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1692 brp_list
[brp_i
].control
);
1693 if (retval
!= ERROR_OK
)
1695 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1696 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1697 brp_list
[brp_i
].value
);
1698 if (retval
!= ERROR_OK
)
1700 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1701 LOG_DEBUG("Invalid BRP number in breakpoint");
1704 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1705 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1706 brp_list
[brp_j
].used
= 0;
1707 brp_list
[brp_j
].value
= 0;
1708 brp_list
[brp_j
].control
= 0;
1709 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1710 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1711 brp_list
[brp_j
].control
);
1712 if (retval
!= ERROR_OK
)
1714 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1715 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1716 brp_list
[brp_j
].value
);
1717 if (retval
!= ERROR_OK
)
1719 breakpoint
->linked_BRP
= 0;
1720 breakpoint
->set
= 0;
1724 int brp_i
= breakpoint
->set
- 1;
1725 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1726 LOG_DEBUG("Invalid BRP number in breakpoint");
1729 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1730 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1731 brp_list
[brp_i
].used
= 0;
1732 brp_list
[brp_i
].value
= 0;
1733 brp_list
[brp_i
].control
= 0;
1734 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1735 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1736 brp_list
[brp_i
].control
);
1737 if (retval
!= ERROR_OK
)
1739 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1740 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1741 brp_list
[brp_i
].value
);
1742 if (retval
!= ERROR_OK
)
1744 breakpoint
->set
= 0;
1749 /* make sure data cache is cleaned & invalidated down to PoC */
1750 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1751 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1752 breakpoint
->length
);
1755 /* restore original instruction (kept in target endianness) */
1756 if (breakpoint
->length
== 4) {
1757 retval
= target_write_memory(target
,
1758 breakpoint
->address
& 0xFFFFFFFE,
1759 4, 1, breakpoint
->orig_instr
);
1760 if (retval
!= ERROR_OK
)
1763 retval
= target_write_memory(target
,
1764 breakpoint
->address
& 0xFFFFFFFE,
1765 2, 1, breakpoint
->orig_instr
);
1766 if (retval
!= ERROR_OK
)
1770 /* update i-cache at breakpoint location */
1771 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1772 breakpoint
->length
);
1773 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1774 breakpoint
->length
);
1776 breakpoint
->set
= 0;
1781 static int cortex_a_add_breakpoint(struct target
*target
,
1782 struct breakpoint
*breakpoint
)
1784 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1786 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1787 LOG_INFO("no hardware breakpoint available");
1788 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1791 if (breakpoint
->type
== BKPT_HARD
)
1792 cortex_a
->brp_num_available
--;
1794 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1797 static int cortex_a_add_context_breakpoint(struct target
*target
,
1798 struct breakpoint
*breakpoint
)
1800 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1802 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1803 LOG_INFO("no hardware breakpoint available");
1804 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1807 if (breakpoint
->type
== BKPT_HARD
)
1808 cortex_a
->brp_num_available
--;
1810 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1813 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1814 struct breakpoint
*breakpoint
)
1816 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1818 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1819 LOG_INFO("no hardware breakpoint available");
1820 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1823 if (breakpoint
->type
== BKPT_HARD
)
1824 cortex_a
->brp_num_available
--;
1826 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1830 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1832 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1835 /* It is perfectly possible to remove breakpoints while the target is running */
1836 if (target
->state
!= TARGET_HALTED
) {
1837 LOG_WARNING("target not halted");
1838 return ERROR_TARGET_NOT_HALTED
;
1842 if (breakpoint
->set
) {
1843 cortex_a_unset_breakpoint(target
, breakpoint
);
1844 if (breakpoint
->type
== BKPT_HARD
)
1845 cortex_a
->brp_num_available
++;
1853 * Cortex-A Reset functions
1856 static int cortex_a_assert_reset(struct target
*target
)
1858 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1862 /* FIXME when halt is requested, make it work somehow... */
1864 /* This function can be called in "target not examined" state */
1866 /* Issue some kind of warm reset. */
1867 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1868 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1869 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1870 /* REVISIT handle "pulls" cases, if there's
1871 * hardware that needs them to work.
1875 * FIXME: fix reset when transport is SWD. This is a temporary
1876 * work-around for release v0.10 that is not intended to stay!
1878 if (transport_is_swd() ||
1879 (target
->reset_halt
&& (jtag_get_reset_config() & RESET_SRST_NO_GATING
)))
1880 jtag_add_reset(0, 1);
1883 LOG_ERROR("%s: how to reset?", target_name(target
));
1887 /* registers are now invalid */
1888 if (target_was_examined(target
))
1889 register_cache_invalidate(armv7a
->arm
.core_cache
);
1891 target
->state
= TARGET_RESET
;
1896 static int cortex_a_deassert_reset(struct target
*target
)
1902 /* be certain SRST is off */
1903 jtag_add_reset(0, 0);
1905 if (target_was_examined(target
)) {
1906 retval
= cortex_a_poll(target
);
1907 if (retval
!= ERROR_OK
)
1911 if (target
->reset_halt
) {
1912 if (target
->state
!= TARGET_HALTED
) {
1913 LOG_WARNING("%s: ran after reset and before halt ...",
1914 target_name(target
));
1915 if (target_was_examined(target
)) {
1916 retval
= target_halt(target
);
1917 if (retval
!= ERROR_OK
)
1920 target
->state
= TARGET_UNKNOWN
;
1927 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1929 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1930 * New desired mode must be in mode. Current value of DSCR must be in
1931 * *dscr, which is updated with new value.
1933 * This function elides actually sending the mode-change over the debug
1934 * interface if the mode is already set as desired.
1936 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1937 if (new_dscr
!= *dscr
) {
1938 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1939 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1940 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1941 if (retval
== ERROR_OK
)
1949 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1950 uint32_t value
, uint32_t *dscr
)
1952 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1953 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1954 int64_t then
= timeval_ms();
1957 while ((*dscr
& mask
) != value
) {
1958 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1959 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1960 if (retval
!= ERROR_OK
)
1962 if (timeval_ms() > then
+ 1000) {
1963 LOG_ERROR("timeout waiting for DSCR bit change");
1970 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1971 uint32_t *data
, uint32_t *dscr
)
1974 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1976 /* Move from coprocessor to R0. */
1977 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1978 if (retval
!= ERROR_OK
)
1981 /* Move from R0 to DTRTX. */
1982 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1983 if (retval
!= ERROR_OK
)
1986 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1987 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1988 * must also check TXfull_l). Most of the time this will be free
1989 * because TXfull_l will be set immediately and cached in dscr. */
1990 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1991 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1992 if (retval
!= ERROR_OK
)
1995 /* Read the value transferred to DTRTX. */
1996 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1997 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1998 if (retval
!= ERROR_OK
)
2004 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
2005 uint32_t *dfsr
, uint32_t *dscr
)
2010 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2011 if (retval
!= ERROR_OK
)
2016 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2017 if (retval
!= ERROR_OK
)
2024 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2025 uint32_t data
, uint32_t *dscr
)
2028 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2030 /* Write the value into DTRRX. */
2031 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2032 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2033 if (retval
!= ERROR_OK
)
2036 /* Move from DTRRX to R0. */
2037 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2038 if (retval
!= ERROR_OK
)
2041 /* Move from R0 to coprocessor. */
2042 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2043 if (retval
!= ERROR_OK
)
2046 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2047 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2048 * check RXfull_l). Most of the time this will be free because RXfull_l
2049 * will be cleared immediately and cached in dscr. */
2050 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2051 if (retval
!= ERROR_OK
)
2057 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2058 uint32_t dfsr
, uint32_t *dscr
)
2062 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2063 if (retval
!= ERROR_OK
)
2066 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2067 if (retval
!= ERROR_OK
)
2073 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2075 uint32_t status
, upper4
;
2077 if (dfsr
& (1 << 9)) {
2079 status
= dfsr
& 0x3f;
2080 upper4
= status
>> 2;
2081 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2082 return ERROR_TARGET_TRANSLATION_FAULT
;
2083 else if (status
== 33)
2084 return ERROR_TARGET_UNALIGNED_ACCESS
;
2086 return ERROR_TARGET_DATA_ABORT
;
2088 /* Normal format. */
2089 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2091 return ERROR_TARGET_UNALIGNED_ACCESS
;
2092 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2093 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2094 return ERROR_TARGET_TRANSLATION_FAULT
;
2096 return ERROR_TARGET_DATA_ABORT
;
2100 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
2101 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2103 /* Writes count objects of size size from *buffer. Old value of DSCR must
2104 * be in *dscr; updated to new value. This is slow because it works for
2105 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2106 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2109 * - Address is in R0.
2110 * - R0 is marked dirty.
2112 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2113 struct arm
*arm
= &armv7a
->arm
;
2116 /* Mark register R1 as dirty, to use for transferring data. */
2117 arm_reg_current(arm
, 1)->dirty
= true;
2119 /* Switch to non-blocking mode if not already in that mode. */
2120 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2121 if (retval
!= ERROR_OK
)
2124 /* Go through the objects. */
2126 /* Write the value to store into DTRRX. */
2127 uint32_t data
, opcode
;
2131 data
= target_buffer_get_u16(target
, buffer
);
2133 data
= target_buffer_get_u32(target
, buffer
);
2134 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2135 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2136 if (retval
!= ERROR_OK
)
2139 /* Transfer the value from DTRRX to R1. */
2140 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2141 if (retval
!= ERROR_OK
)
2144 /* Write the value transferred to R1 into memory. */
2146 opcode
= ARMV4_5_STRB_IP(1, 0);
2148 opcode
= ARMV4_5_STRH_IP(1, 0);
2150 opcode
= ARMV4_5_STRW_IP(1, 0);
2151 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2152 if (retval
!= ERROR_OK
)
2155 /* Check for faults and return early. */
2156 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2157 return ERROR_OK
; /* A data fault is not considered a system failure. */
2159 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2160 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2161 * must also check RXfull_l). Most of the time this will be free
2162 * because RXfull_l will be cleared immediately and cached in dscr. */
2163 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2164 if (retval
!= ERROR_OK
)
2175 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
2176 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2178 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2179 * in *dscr; updated to new value. This is fast but only works for
2180 * word-sized objects at aligned addresses.
2182 * - Address is in R0 and must be a multiple of 4.
2183 * - R0 is marked dirty.
2185 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2188 /* Switch to fast mode if not already in that mode. */
2189 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2190 if (retval
!= ERROR_OK
)
2193 /* Latch STC instruction. */
2194 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2195 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2196 if (retval
!= ERROR_OK
)
2199 /* Transfer all the data and issue all the instructions. */
2200 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
2201 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2204 static int cortex_a_write_cpu_memory(struct target
*target
,
2205 uint32_t address
, uint32_t size
,
2206 uint32_t count
, const uint8_t *buffer
)
2208 /* Write memory through the CPU. */
2209 int retval
, final_retval
;
2210 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2211 struct arm
*arm
= &armv7a
->arm
;
2212 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2214 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2215 address
, size
, count
);
2216 if (target
->state
!= TARGET_HALTED
) {
2217 LOG_WARNING("target not halted");
2218 return ERROR_TARGET_NOT_HALTED
;
2224 /* Clear any abort. */
2225 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2226 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2227 if (retval
!= ERROR_OK
)
2231 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2232 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2233 if (retval
!= ERROR_OK
)
2236 /* Switch to non-blocking mode if not already in that mode. */
2237 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2238 if (retval
!= ERROR_OK
)
2241 /* Mark R0 as dirty. */
2242 arm_reg_current(arm
, 0)->dirty
= true;
2244 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2245 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2246 if (retval
!= ERROR_OK
)
2249 /* Get the memory address into R0. */
2250 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2251 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2252 if (retval
!= ERROR_OK
)
2254 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2255 if (retval
!= ERROR_OK
)
2258 if (size
== 4 && (address
% 4) == 0) {
2259 /* We are doing a word-aligned transfer, so use fast mode. */
2260 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2262 /* Use slow path. */
2263 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2267 final_retval
= retval
;
2269 /* Switch to non-blocking mode if not already in that mode. */
2270 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2271 if (final_retval
== ERROR_OK
)
2272 final_retval
= retval
;
2274 /* Wait for last issued instruction to complete. */
2275 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2276 if (final_retval
== ERROR_OK
)
2277 final_retval
= retval
;
2279 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2280 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2281 * check RXfull_l). Most of the time this will be free because RXfull_l
2282 * will be cleared immediately and cached in dscr. However, don't do this
2283 * if there is fault, because then the instruction might not have completed
2285 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2286 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2287 if (retval
!= ERROR_OK
)
2291 /* If there were any sticky abort flags, clear them. */
2292 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2294 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2295 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2296 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2301 /* Handle synchronous data faults. */
2302 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2303 if (final_retval
== ERROR_OK
) {
2304 /* Final return value will reflect cause of fault. */
2305 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2306 if (retval
== ERROR_OK
) {
2307 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2308 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2310 final_retval
= retval
;
2312 /* Fault destroyed DFAR/DFSR; restore them. */
2313 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2314 if (retval
!= ERROR_OK
)
2315 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2318 /* Handle asynchronous data faults. */
2319 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2320 if (final_retval
== ERROR_OK
)
2321 /* No other error has been recorded so far, so keep this one. */
2322 final_retval
= ERROR_TARGET_DATA_ABORT
;
2325 /* If the DCC is nonempty, clear it. */
2326 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2328 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2329 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2330 if (final_retval
== ERROR_OK
)
2331 final_retval
= retval
;
2333 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2334 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2335 if (final_retval
== ERROR_OK
)
2336 final_retval
= retval
;
2340 return final_retval
;
2343 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2344 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2346 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2347 * in *dscr; updated to new value. This is slow because it works for
2348 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2349 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2352 * - Address is in R0.
2353 * - R0 is marked dirty.
2355 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2356 struct arm
*arm
= &armv7a
->arm
;
2359 /* Mark register R1 as dirty, to use for transferring data. */
2360 arm_reg_current(arm
, 1)->dirty
= true;
2362 /* Switch to non-blocking mode if not already in that mode. */
2363 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2364 if (retval
!= ERROR_OK
)
2367 /* Go through the objects. */
2369 /* Issue a load of the appropriate size to R1. */
2370 uint32_t opcode
, data
;
2372 opcode
= ARMV4_5_LDRB_IP(1, 0);
2374 opcode
= ARMV4_5_LDRH_IP(1, 0);
2376 opcode
= ARMV4_5_LDRW_IP(1, 0);
2377 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2378 if (retval
!= ERROR_OK
)
2381 /* Issue a write of R1 to DTRTX. */
2382 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2383 if (retval
!= ERROR_OK
)
2386 /* Check for faults and return early. */
2387 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2388 return ERROR_OK
; /* A data fault is not considered a system failure. */
2390 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2391 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2392 * must also check TXfull_l). Most of the time this will be free
2393 * because TXfull_l will be set immediately and cached in dscr. */
2394 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2395 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2396 if (retval
!= ERROR_OK
)
2399 /* Read the value transferred to DTRTX into the buffer. */
2400 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2401 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2402 if (retval
!= ERROR_OK
)
2405 *buffer
= (uint8_t) data
;
2407 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2409 target_buffer_set_u32(target
, buffer
, data
);
2419 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2420 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2422 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2423 * *dscr; updated to new value. This is fast but only works for word-sized
2424 * objects at aligned addresses.
2426 * - Address is in R0 and must be a multiple of 4.
2427 * - R0 is marked dirty.
2429 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2433 /* Switch to non-blocking mode if not already in that mode. */
2434 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2435 if (retval
!= ERROR_OK
)
2438 /* Issue the LDC instruction via a write to ITR. */
2439 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2440 if (retval
!= ERROR_OK
)
2446 /* Switch to fast mode if not already in that mode. */
2447 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2448 if (retval
!= ERROR_OK
)
2451 /* Latch LDC instruction. */
2452 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2453 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2454 if (retval
!= ERROR_OK
)
2457 /* Read the value transferred to DTRTX into the buffer. Due to fast
2458 * mode rules, this blocks until the instruction finishes executing and
2459 * then reissues the read instruction to read the next word from
2460 * memory. The last read of DTRTX in this call reads the second-to-last
2461 * word from memory and issues the read instruction for the last word.
2463 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2464 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2465 if (retval
!= ERROR_OK
)
2469 buffer
+= count
* 4;
2472 /* Wait for last issued instruction to complete. */
2473 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2474 if (retval
!= ERROR_OK
)
2477 /* Switch to non-blocking mode if not already in that mode. */
2478 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2479 if (retval
!= ERROR_OK
)
2482 /* Check for faults and return early. */
2483 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2484 return ERROR_OK
; /* A data fault is not considered a system failure. */
2486 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2487 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2488 * check TXfull_l). Most of the time this will be free because TXfull_l
2489 * will be set immediately and cached in dscr. */
2490 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2491 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2492 if (retval
!= ERROR_OK
)
2495 /* Read the value transferred to DTRTX into the buffer. This is the last
2497 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2498 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2499 if (retval
!= ERROR_OK
)
2501 target_buffer_set_u32(target
, buffer
, u32
);
2506 static int cortex_a_read_cpu_memory(struct target
*target
,
2507 uint32_t address
, uint32_t size
,
2508 uint32_t count
, uint8_t *buffer
)
2510 /* Read memory through the CPU. */
2511 int retval
, final_retval
;
2512 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2513 struct arm
*arm
= &armv7a
->arm
;
2514 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2516 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2517 address
, size
, count
);
2518 if (target
->state
!= TARGET_HALTED
) {
2519 LOG_WARNING("target not halted");
2520 return ERROR_TARGET_NOT_HALTED
;
2526 /* Clear any abort. */
2527 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2528 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2529 if (retval
!= ERROR_OK
)
2533 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2534 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2535 if (retval
!= ERROR_OK
)
2538 /* Switch to non-blocking mode if not already in that mode. */
2539 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2540 if (retval
!= ERROR_OK
)
2543 /* Mark R0 as dirty. */
2544 arm_reg_current(arm
, 0)->dirty
= true;
2546 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2547 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2548 if (retval
!= ERROR_OK
)
2551 /* Get the memory address into R0. */
2552 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2553 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2554 if (retval
!= ERROR_OK
)
2556 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2557 if (retval
!= ERROR_OK
)
2560 if (size
== 4 && (address
% 4) == 0) {
2561 /* We are doing a word-aligned transfer, so use fast mode. */
2562 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2564 /* Use slow path. */
2565 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2569 final_retval
= retval
;
2571 /* Switch to non-blocking mode if not already in that mode. */
2572 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2573 if (final_retval
== ERROR_OK
)
2574 final_retval
= retval
;
2576 /* Wait for last issued instruction to complete. */
2577 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2578 if (final_retval
== ERROR_OK
)
2579 final_retval
= retval
;
2581 /* If there were any sticky abort flags, clear them. */
2582 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2584 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2585 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2586 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2591 /* Handle synchronous data faults. */
2592 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2593 if (final_retval
== ERROR_OK
) {
2594 /* Final return value will reflect cause of fault. */
2595 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2596 if (retval
== ERROR_OK
) {
2597 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2598 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2600 final_retval
= retval
;
2602 /* Fault destroyed DFAR/DFSR; restore them. */
2603 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2604 if (retval
!= ERROR_OK
)
2605 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2608 /* Handle asynchronous data faults. */
2609 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2610 if (final_retval
== ERROR_OK
)
2611 /* No other error has been recorded so far, so keep this one. */
2612 final_retval
= ERROR_TARGET_DATA_ABORT
;
2615 /* If the DCC is nonempty, clear it. */
2616 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2618 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2619 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2620 if (final_retval
== ERROR_OK
)
2621 final_retval
= retval
;
2623 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2624 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2625 if (final_retval
== ERROR_OK
)
2626 final_retval
= retval
;
2630 return final_retval
;
2635 * Cortex-A Memory access
2637 * This is same Cortex-M3 but we must also use the correct
2638 * ap number for every access.
2641 static int cortex_a_read_phys_memory(struct target
*target
,
2642 uint32_t address
, uint32_t size
,
2643 uint32_t count
, uint8_t *buffer
)
2645 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2646 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2647 uint8_t apsel
= swjdp
->apsel
;
2650 if (!count
|| !buffer
)
2651 return ERROR_COMMAND_SYNTAX_ERROR
;
2653 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2654 address
, size
, count
);
2656 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2657 return mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2659 /* read memory through the CPU */
2660 cortex_a_prep_memaccess(target
, 1);
2661 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2662 cortex_a_post_memaccess(target
, 1);
2667 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2668 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2672 /* cortex_a handles unaligned memory access */
2673 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2676 cortex_a_prep_memaccess(target
, 0);
2677 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2678 cortex_a_post_memaccess(target
, 0);
2683 static int cortex_a_read_memory_ahb(struct target
*target
, uint32_t address
,
2684 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2686 int mmu_enabled
= 0;
2687 uint32_t virt
, phys
;
2689 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2690 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2691 uint8_t apsel
= swjdp
->apsel
;
2693 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2694 return target_read_memory(target
, address
, size
, count
, buffer
);
2696 /* cortex_a handles unaligned memory access */
2697 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2700 /* determine if MMU was enabled on target stop */
2701 if (!armv7a
->is_armv7r
) {
2702 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2703 if (retval
!= ERROR_OK
)
2709 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2710 if (retval
!= ERROR_OK
)
2713 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2718 if (!count
|| !buffer
)
2719 return ERROR_COMMAND_SYNTAX_ERROR
;
2721 retval
= mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2726 static int cortex_a_write_phys_memory(struct target
*target
,
2727 uint32_t address
, uint32_t size
,
2728 uint32_t count
, const uint8_t *buffer
)
2730 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2731 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2732 uint8_t apsel
= swjdp
->apsel
;
2735 if (!count
|| !buffer
)
2736 return ERROR_COMMAND_SYNTAX_ERROR
;
2738 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2741 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2742 return mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2744 /* write memory through the CPU */
2745 cortex_a_prep_memaccess(target
, 1);
2746 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2747 cortex_a_post_memaccess(target
, 1);
2752 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2753 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2757 /* cortex_a handles unaligned memory access */
2758 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2761 /* memory writes bypass the caches, must flush before writing */
2762 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2764 cortex_a_prep_memaccess(target
, 0);
2765 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2766 cortex_a_post_memaccess(target
, 0);
2770 static int cortex_a_write_memory_ahb(struct target
*target
, uint32_t address
,
2771 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2773 int mmu_enabled
= 0;
2774 uint32_t virt
, phys
;
2776 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2777 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2778 uint8_t apsel
= swjdp
->apsel
;
2780 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2781 return target_write_memory(target
, address
, size
, count
, buffer
);
2783 /* cortex_a handles unaligned memory access */
2784 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2787 /* determine if MMU was enabled on target stop */
2788 if (!armv7a
->is_armv7r
) {
2789 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2790 if (retval
!= ERROR_OK
)
2796 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2797 if (retval
!= ERROR_OK
)
2800 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2806 if (!count
|| !buffer
)
2807 return ERROR_COMMAND_SYNTAX_ERROR
;
2809 retval
= mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2814 static int cortex_a_read_buffer(struct target
*target
, uint32_t address
,
2815 uint32_t count
, uint8_t *buffer
)
2819 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2820 * will have something to do with the size we leave to it. */
2821 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2822 if (address
& size
) {
2823 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2824 if (retval
!= ERROR_OK
)
2832 /* Read the data with as large access size as possible. */
2833 for (; size
> 0; size
/= 2) {
2834 uint32_t aligned
= count
- count
% size
;
2836 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2837 if (retval
!= ERROR_OK
)
2848 static int cortex_a_write_buffer(struct target
*target
, uint32_t address
,
2849 uint32_t count
, const uint8_t *buffer
)
2853 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2854 * will have something to do with the size we leave to it. */
2855 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2856 if (address
& size
) {
2857 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2858 if (retval
!= ERROR_OK
)
2866 /* Write the data with as large access size as possible. */
2867 for (; size
> 0; size
/= 2) {
2868 uint32_t aligned
= count
- count
% size
;
2870 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2871 if (retval
!= ERROR_OK
)
2882 static int cortex_a_handle_target_request(void *priv
)
2884 struct target
*target
= priv
;
2885 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2888 if (!target_was_examined(target
))
2890 if (!target
->dbg_msg_enabled
)
2893 if (target
->state
== TARGET_RUNNING
) {
2896 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2897 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2899 /* check if we have data */
2900 int64_t then
= timeval_ms();
2901 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2902 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2903 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2904 if (retval
== ERROR_OK
) {
2905 target_request(target
, request
);
2906 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2907 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2909 if (timeval_ms() > then
+ 1000) {
2910 LOG_ERROR("Timeout waiting for dtr tx full");
2920 * Cortex-A target information and configuration
2923 static int cortex_a_examine_first(struct target
*target
)
2925 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2926 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2927 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2930 int retval
= ERROR_OK
;
2931 uint32_t didr
, cpuid
, dbg_osreg
;
2933 retval
= dap_dp_init(swjdp
);
2934 if (retval
!= ERROR_OK
) {
2935 LOG_ERROR("Could not initialize the debug port");
2939 /* Search for the APB-AP - it is needed for access to debug registers */
2940 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2941 if (retval
!= ERROR_OK
) {
2942 LOG_ERROR("Could not find APB-AP for debug access");
2946 retval
= mem_ap_init(armv7a
->debug_ap
);
2947 if (retval
!= ERROR_OK
) {
2948 LOG_ERROR("Could not initialize the APB-AP");
2952 armv7a
->debug_ap
->memaccess_tck
= 80;
2954 /* Search for the AHB-AB.
2955 * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
2956 * can access system memory. */
2957 armv7a
->memory_ap_available
= false;
2958 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2959 if (retval
== ERROR_OK
) {
2960 retval
= mem_ap_init(armv7a
->memory_ap
);
2961 if (retval
== ERROR_OK
)
2962 armv7a
->memory_ap_available
= true;
2964 if (retval
!= ERROR_OK
) {
2965 /* AHB-AP not found or unavailable - use the CPU */
2966 LOG_DEBUG("No AHB-AP available for memory access");
2969 if (!target
->dbgbase_set
) {
2971 /* Get ROM Table base */
2973 int32_t coreidx
= target
->coreid
;
2974 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2976 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
2977 if (retval
!= ERROR_OK
)
2979 /* Lookup 0x15 -- Processor DAP */
2980 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
2981 &armv7a
->debug_base
, &coreidx
);
2982 if (retval
!= ERROR_OK
) {
2983 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2987 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2988 target
->coreid
, armv7a
->debug_base
);
2990 armv7a
->debug_base
= target
->dbgbase
;
2992 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2993 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2994 if (retval
!= ERROR_OK
) {
2995 LOG_DEBUG("Examine %s failed", "DIDR");
2999 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3000 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
3001 if (retval
!= ERROR_OK
) {
3002 LOG_DEBUG("Examine %s failed", "CPUID");
3006 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
3007 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3009 cortex_a
->didr
= didr
;
3010 cortex_a
->cpuid
= cpuid
;
3012 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3013 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3014 if (retval
!= ERROR_OK
)
3016 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3018 if ((dbg_osreg
& PRSR_POWERUP_STATUS
) == 0) {
3019 LOG_ERROR("target->coreid %" PRId32
" powered down!", target
->coreid
);
3020 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3021 return ERROR_TARGET_INIT_FAILED
;
3024 if (dbg_osreg
& PRSR_STICKY_RESET_STATUS
)
3025 LOG_DEBUG("target->coreid %" PRId32
" was reset!", target
->coreid
);
3027 /* Read DBGOSLSR and check if OSLK is implemented */
3028 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3029 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3030 if (retval
!= ERROR_OK
)
3032 LOG_DEBUG("target->coreid %" PRId32
" DBGOSLSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3034 /* check if OS Lock is implemented */
3035 if ((dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM0
|| (dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM1
) {
3036 /* check if OS Lock is set */
3037 if (dbg_osreg
& OSLSR_OSLK
) {
3038 LOG_DEBUG("target->coreid %" PRId32
" OSLock set! Trying to unlock", target
->coreid
);
3040 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
3041 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3043 if (retval
== ERROR_OK
)
3044 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3045 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3047 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
3048 if (retval
!= ERROR_OK
|| (dbg_osreg
& OSLSR_OSLK
) != 0) {
3049 LOG_ERROR("target->coreid %" PRId32
" OSLock sticky, core not powered?",
3051 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3052 return ERROR_TARGET_INIT_FAILED
;
3057 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3059 /* Avoid recreating the registers cache */
3060 if (!target_was_examined(target
)) {
3061 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3062 if (retval
!= ERROR_OK
)
3066 /* Setup Breakpoint Register Pairs */
3067 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3068 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3069 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3070 free(cortex_a
->brp_list
);
3071 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3072 /* cortex_a->brb_enabled = ????; */
3073 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3074 cortex_a
->brp_list
[i
].used
= 0;
3075 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3076 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3078 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3079 cortex_a
->brp_list
[i
].value
= 0;
3080 cortex_a
->brp_list
[i
].control
= 0;
3081 cortex_a
->brp_list
[i
].BRPn
= i
;
3084 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3086 /* select debug_ap as default */
3087 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
3089 target_set_examined(target
);
3093 static int cortex_a_examine(struct target
*target
)
3095 int retval
= ERROR_OK
;
3097 /* Reestablish communication after target reset */
3098 retval
= cortex_a_examine_first(target
);
3100 /* Configure core debug access */
3101 if (retval
== ERROR_OK
)
3102 retval
= cortex_a_init_debug_access(target
);
3108 * Cortex-A target creation and initialization
3111 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3112 struct target
*target
)
3114 /* examine_first() does a bunch of this */
3115 arm_semihosting_init(target
);
3119 static int cortex_a_init_arch_info(struct target
*target
,
3120 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3122 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3124 /* Setup struct cortex_a_common */
3125 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3127 /* tap has no dap initialized */
3129 tap
->dap
= dap_init();
3131 /* Leave (only) generic DAP stuff for debugport_init() */
3132 tap
->dap
->tap
= tap
;
3135 armv7a
->arm
.dap
= tap
->dap
;
3137 cortex_a
->fast_reg_read
= 0;
3139 /* register arch-specific functions */
3140 armv7a
->examine_debug_reason
= NULL
;
3142 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3144 armv7a
->pre_restore_context
= NULL
;
3146 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3149 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3151 /* REVISIT v7a setup should be in a v7a-specific routine */
3152 armv7a_init_arch_info(target
, armv7a
);
3153 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3158 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3160 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3162 cortex_a
->armv7a_common
.is_armv7r
= false;
3164 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3167 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3169 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3171 cortex_a
->armv7a_common
.is_armv7r
= true;
3173 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3176 static void cortex_a_deinit_target(struct target
*target
)
3178 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3179 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3181 free(cortex_a
->brp_list
);
3187 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3189 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3191 if (target
->state
!= TARGET_HALTED
) {
3192 LOG_ERROR("%s: target not halted", __func__
);
3193 return ERROR_TARGET_INVALID
;
3196 if (armv7a
->is_armv7r
)
3199 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3204 static int cortex_a_virt2phys(struct target
*target
,
3205 uint32_t virt
, uint32_t *phys
)
3207 int retval
= ERROR_FAIL
;
3208 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3209 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3210 uint8_t apsel
= swjdp
->apsel
;
3211 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
)) {
3213 retval
= armv7a_mmu_translate_va(target
,
3215 if (retval
!= ERROR_OK
)
3218 } else {/* use this method if armv7a->memory_ap not selected
3219 * mmu must be enable in order to get a correct translation */
3220 retval
= cortex_a_mmu_modify(target
, 1);
3221 if (retval
!= ERROR_OK
)
3223 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
3229 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3231 struct target
*target
= get_current_target(CMD_CTX
);
3232 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3234 return armv7a_handle_cache_info_command(CMD_CTX
,
3235 &armv7a
->armv7a_mmu
.armv7a_cache
);
3239 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3241 struct target
*target
= get_current_target(CMD_CTX
);
3242 if (!target_was_examined(target
)) {
3243 LOG_ERROR("target not examined yet");
3247 return cortex_a_init_debug_access(target
);
3249 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3251 struct target
*target
= get_current_target(CMD_CTX
);
3252 /* check target is an smp target */
3253 struct target_list
*head
;
3254 struct target
*curr
;
3255 head
= target
->head
;
3257 if (head
!= (struct target_list
*)NULL
) {
3258 while (head
!= (struct target_list
*)NULL
) {
3259 curr
= head
->target
;
3263 /* fixes the target display to the debugger */
3264 target
->gdb_service
->target
= target
;
3269 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3271 struct target
*target
= get_current_target(CMD_CTX
);
3272 struct target_list
*head
;
3273 struct target
*curr
;
3274 head
= target
->head
;
3275 if (head
!= (struct target_list
*)NULL
) {
3277 while (head
!= (struct target_list
*)NULL
) {
3278 curr
= head
->target
;
3286 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3288 struct target
*target
= get_current_target(CMD_CTX
);
3289 int retval
= ERROR_OK
;
3290 struct target_list
*head
;
3291 head
= target
->head
;
3292 if (head
!= (struct target_list
*)NULL
) {
3293 if (CMD_ARGC
== 1) {
3295 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3296 if (ERROR_OK
!= retval
)
3298 target
->gdb_service
->core
[1] = coreid
;
3301 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3302 , target
->gdb_service
->core
[1]);
3307 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3309 struct target
*target
= get_current_target(CMD_CTX
);
3310 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3312 static const Jim_Nvp nvp_maskisr_modes
[] = {
3313 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3314 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3315 { .name
= NULL
, .value
= -1 },
3320 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3321 if (n
->name
== NULL
) {
3322 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
3323 return ERROR_COMMAND_SYNTAX_ERROR
;
3326 cortex_a
->isrmasking_mode
= n
->value
;
3329 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3330 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3335 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
3337 struct target
*target
= get_current_target(CMD_CTX
);
3338 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3340 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
3341 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
3342 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
3343 { .name
= NULL
, .value
= -1 },
3348 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
3349 if (n
->name
== NULL
)
3350 return ERROR_COMMAND_SYNTAX_ERROR
;
3351 cortex_a
->dacrfixup_mode
= n
->value
;
3355 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
3356 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3361 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3363 .name
= "cache_info",
3364 .handler
= cortex_a_handle_cache_info_command
,
3365 .mode
= COMMAND_EXEC
,
3366 .help
= "display information about target caches",
3371 .handler
= cortex_a_handle_dbginit_command
,
3372 .mode
= COMMAND_EXEC
,
3373 .help
= "Initialize core debug",
3376 { .name
= "smp_off",
3377 .handler
= cortex_a_handle_smp_off_command
,
3378 .mode
= COMMAND_EXEC
,
3379 .help
= "Stop smp handling",
3383 .handler
= cortex_a_handle_smp_on_command
,
3384 .mode
= COMMAND_EXEC
,
3385 .help
= "Restart smp handling",
3390 .handler
= cortex_a_handle_smp_gdb_command
,
3391 .mode
= COMMAND_EXEC
,
3392 .help
= "display/fix current core played to gdb",
3397 .handler
= handle_cortex_a_mask_interrupts_command
,
3398 .mode
= COMMAND_ANY
,
3399 .help
= "mask cortex_a interrupts",
3400 .usage
= "['on'|'off']",
3403 .name
= "dacrfixup",
3404 .handler
= handle_cortex_a_dacrfixup_command
,
3405 .mode
= COMMAND_EXEC
,
3406 .help
= "set domain access control (DACR) to all-manager "
3408 .usage
= "['on'|'off']",
3411 COMMAND_REGISTRATION_DONE
3413 static const struct command_registration cortex_a_command_handlers
[] = {
3415 .chain
= arm_command_handlers
,
3418 .chain
= armv7a_command_handlers
,
3422 .mode
= COMMAND_ANY
,
3423 .help
= "Cortex-A command group",
3425 .chain
= cortex_a_exec_command_handlers
,
3427 COMMAND_REGISTRATION_DONE
3430 struct target_type cortexa_target
= {
3432 .deprecated_name
= "cortex_a8",
3434 .poll
= cortex_a_poll
,
3435 .arch_state
= armv7a_arch_state
,
3437 .halt
= cortex_a_halt
,
3438 .resume
= cortex_a_resume
,
3439 .step
= cortex_a_step
,
3441 .assert_reset
= cortex_a_assert_reset
,
3442 .deassert_reset
= cortex_a_deassert_reset
,
3444 /* REVISIT allow exporting VFP3 registers ... */
3445 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3447 .read_memory
= cortex_a_read_memory
,
3448 .write_memory
= cortex_a_write_memory
,
3450 .read_buffer
= cortex_a_read_buffer
,
3451 .write_buffer
= cortex_a_write_buffer
,
3453 .checksum_memory
= arm_checksum_memory
,
3454 .blank_check_memory
= arm_blank_check_memory
,
3456 .run_algorithm
= armv4_5_run_algorithm
,
3458 .add_breakpoint
= cortex_a_add_breakpoint
,
3459 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3460 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3461 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3462 .add_watchpoint
= NULL
,
3463 .remove_watchpoint
= NULL
,
3465 .commands
= cortex_a_command_handlers
,
3466 .target_create
= cortex_a_target_create
,
3467 .init_target
= cortex_a_init_target
,
3468 .examine
= cortex_a_examine
,
3469 .deinit_target
= cortex_a_deinit_target
,
3471 .read_phys_memory
= cortex_a_read_phys_memory
,
3472 .write_phys_memory
= cortex_a_write_phys_memory
,
3473 .mmu
= cortex_a_mmu
,
3474 .virt2phys
= cortex_a_virt2phys
,
3477 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3479 .name
= "cache_info",
3480 .handler
= cortex_a_handle_cache_info_command
,
3481 .mode
= COMMAND_EXEC
,
3482 .help
= "display information about target caches",
3487 .handler
= cortex_a_handle_dbginit_command
,
3488 .mode
= COMMAND_EXEC
,
3489 .help
= "Initialize core debug",
3494 .handler
= handle_cortex_a_mask_interrupts_command
,
3495 .mode
= COMMAND_EXEC
,
3496 .help
= "mask cortex_r4 interrupts",
3497 .usage
= "['on'|'off']",
3500 COMMAND_REGISTRATION_DONE
3502 static const struct command_registration cortex_r4_command_handlers
[] = {
3504 .chain
= arm_command_handlers
,
3507 .chain
= armv7a_command_handlers
,
3510 .name
= "cortex_r4",
3511 .mode
= COMMAND_ANY
,
3512 .help
= "Cortex-R4 command group",
3514 .chain
= cortex_r4_exec_command_handlers
,
3516 COMMAND_REGISTRATION_DONE
3519 struct target_type cortexr4_target
= {
3520 .name
= "cortex_r4",
3522 .poll
= cortex_a_poll
,
3523 .arch_state
= armv7a_arch_state
,
3525 .halt
= cortex_a_halt
,
3526 .resume
= cortex_a_resume
,
3527 .step
= cortex_a_step
,
3529 .assert_reset
= cortex_a_assert_reset
,
3530 .deassert_reset
= cortex_a_deassert_reset
,
3532 /* REVISIT allow exporting VFP3 registers ... */
3533 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3535 .read_memory
= cortex_a_read_phys_memory
,
3536 .write_memory
= cortex_a_write_phys_memory
,
3538 .checksum_memory
= arm_checksum_memory
,
3539 .blank_check_memory
= arm_blank_check_memory
,
3541 .run_algorithm
= armv4_5_run_algorithm
,
3543 .add_breakpoint
= cortex_a_add_breakpoint
,
3544 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3545 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3546 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3547 .add_watchpoint
= NULL
,
3548 .remove_watchpoint
= NULL
,
3550 .commands
= cortex_r4_command_handlers
,
3551 .target_create
= cortex_r4_target_create
,
3552 .init_target
= cortex_a_init_target
,
3553 .examine
= cortex_a_examine
,
3554 .deinit_target
= cortex_a_deinit_target
,