1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program; if not, write to the *
38 * Free Software Foundation, Inc., *
39 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
41 * Cortex-A8(tm) TRM, ARM DDI 0344H *
42 * Cortex-A9(tm) TRM, ARM DDI 0407F *
43 * Cortex-A4(tm) TRM, ARM DDI 0363E *
44 * Cortex-A15(tm)TRM, ARM DDI 0438C *
46 ***************************************************************************/
52 #include "breakpoints.h"
55 #include "target_request.h"
56 #include "target_type.h"
57 #include "arm_opcodes.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_virt2phys(struct target
*target
,
77 uint32_t virt
, uint32_t *phys
);
78 static int cortex_a_read_apb_ab_memory(struct target
*target
,
79 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
82 /* restore cp15_control_reg at resume */
83 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
85 int retval
= ERROR_OK
;
86 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
87 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
89 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
90 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
91 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
92 retval
= armv7a
->arm
.mcr(target
, 15,
95 cortex_a
->cp15_control_reg
);
100 /* check address before cortex_a_apb read write access with mmu on
101 * remove apb predictible data abort */
102 static int cortex_a_check_address(struct target
*target
, uint32_t address
)
104 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
105 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
106 uint32_t os_border
= armv7a
->armv7a_mmu
.os_border
;
107 if ((address
< os_border
) &&
108 (armv7a
->arm
.core_mode
== ARM_MODE_SVC
)) {
109 LOG_ERROR("%" PRIx32
" access in userspace and target in supervisor", address
);
112 if ((address
>= os_border
) &&
113 (cortex_a
->curr_mode
!= ARM_MODE_SVC
)) {
114 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
115 cortex_a
->curr_mode
= ARM_MODE_SVC
;
116 LOG_INFO("%" PRIx32
" access in kernel space and target not in supervisor",
120 if ((address
< os_border
) &&
121 (cortex_a
->curr_mode
== ARM_MODE_SVC
)) {
122 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
123 cortex_a
->curr_mode
= ARM_MODE_ANY
;
127 /* modify cp15_control_reg in order to enable or disable mmu for :
128 * - virt2phys address conversion
129 * - read or write memory in phys or virt address */
130 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
132 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
133 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
134 int retval
= ERROR_OK
;
136 /* if mmu enabled at target stop and mmu not enable */
137 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
138 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
141 if (!(cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
142 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
143 retval
= armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_control_reg_curr
);
149 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
)) {
150 if (cortex_a
->cp15_control_reg_curr
& 0x4U
) {
151 /* data cache is active */
152 cortex_a
->cp15_control_reg_curr
&= ~0x4U
;
153 /* flush data cache armv7 function to be called */
154 if (armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
)
155 armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache(target
);
157 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
158 retval
= armv7a
->arm
.mcr(target
, 15,
161 cortex_a
->cp15_control_reg_curr
);
168 * Cortex-A Basic debug access, very low level assumes state is saved
170 static int cortex_a8_init_debug_access(struct target
*target
)
172 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
173 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
178 /* Unlocking the debug registers for modification
179 * The debugport might be uninitialised so try twice */
180 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
181 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
182 if (retval
!= ERROR_OK
) {
184 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
185 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
186 if (retval
== ERROR_OK
)
188 "Locking debug access failed on first, but succeeded on second try.");
195 * Cortex-A Basic debug access, very low level assumes state is saved
197 static int cortex_a_init_debug_access(struct target
*target
)
199 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
200 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
203 uint32_t cortex_part_num
;
204 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
207 cortex_part_num
= (cortex_a
->cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >>
208 CORTEX_A_MIDR_PARTNUM_SHIFT
;
210 switch (cortex_part_num
) {
211 case CORTEX_A7_PARTNUM
:
212 case CORTEX_A15_PARTNUM
:
213 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
214 armv7a
->debug_base
+ CPUDBG_OSLSR
,
216 if (retval
!= ERROR_OK
)
219 LOG_DEBUG("DBGOSLSR 0x%" PRIx32
, dbg_osreg
);
221 if (dbg_osreg
& CPUDBG_OSLAR_LK_MASK
)
222 /* Unlocking the DEBUG OS registers for modification */
223 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
224 armv7a
->debug_base
+ CPUDBG_OSLAR
,
228 case CORTEX_A5_PARTNUM
:
229 case CORTEX_A8_PARTNUM
:
230 case CORTEX_A9_PARTNUM
:
232 retval
= cortex_a8_init_debug_access(target
);
235 if (retval
!= ERROR_OK
)
237 /* Clear Sticky Power Down status Bit in PRSR to enable access to
238 the registers in the Core Power Domain */
239 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
240 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
241 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
243 if (retval
!= ERROR_OK
)
246 /* Enabling of instruction execution in debug mode is done in debug_entry code */
248 /* Resync breakpoint registers */
250 /* Since this is likely called from init or reset, update target state information*/
251 return cortex_a_poll(target
);
254 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
256 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
257 * Writes final value of DSCR into *dscr. Pass force to force always
258 * reading DSCR at least once. */
259 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
260 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
261 long long then
= timeval_ms();
262 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
264 int retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
265 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
266 if (retval
!= ERROR_OK
) {
267 LOG_ERROR("Could not read DSCR register");
270 if (timeval_ms() > then
+ 1000) {
271 LOG_ERROR("Timeout waiting for InstrCompl=1");
278 /* To reduce needless round-trips, pass in a pointer to the current
279 * DSCR value. Initialize it to zero if you just need to know the
280 * value on return from this function; or DSCR_INSTR_COMP if you
281 * happen to know that no instruction is pending.
283 static int cortex_a_exec_opcode(struct target
*target
,
284 uint32_t opcode
, uint32_t *dscr_p
)
288 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
289 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
291 dscr
= dscr_p
? *dscr_p
: 0;
293 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
295 /* Wait for InstrCompl bit to be set */
296 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
297 if (retval
!= ERROR_OK
)
300 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
301 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
302 if (retval
!= ERROR_OK
)
305 long long then
= timeval_ms();
307 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
308 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
309 if (retval
!= ERROR_OK
) {
310 LOG_ERROR("Could not read DSCR register");
313 if (timeval_ms() > then
+ 1000) {
314 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
317 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
325 /**************************************************************************
326 Read core register with very few exec_opcode, fast but needs work_area.
327 This can cause problems with MMU active.
328 **************************************************************************/
329 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
332 int retval
= ERROR_OK
;
333 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
334 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
336 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
337 if (retval
!= ERROR_OK
)
339 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
340 if (retval
!= ERROR_OK
)
342 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
343 if (retval
!= ERROR_OK
)
346 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
,
347 (uint8_t *)(®file
[1]), 4, 15, address
);
352 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
353 uint32_t *value
, int regnum
)
355 int retval
= ERROR_OK
;
356 uint8_t reg
= regnum
&0xFF;
358 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
359 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
365 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
366 retval
= cortex_a_exec_opcode(target
,
367 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
369 if (retval
!= ERROR_OK
)
371 } else if (reg
== 15) {
372 /* "MOV r0, r15"; then move r0 to DCCTX */
373 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
374 if (retval
!= ERROR_OK
)
376 retval
= cortex_a_exec_opcode(target
,
377 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
379 if (retval
!= ERROR_OK
)
382 /* "MRS r0, CPSR" or "MRS r0, SPSR"
383 * then move r0 to DCCTX
385 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
386 if (retval
!= ERROR_OK
)
388 retval
= cortex_a_exec_opcode(target
,
389 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
391 if (retval
!= ERROR_OK
)
395 /* Wait for DTRRXfull then read DTRRTX */
396 long long then
= timeval_ms();
397 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
398 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
399 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
400 if (retval
!= ERROR_OK
)
402 if (timeval_ms() > then
+ 1000) {
403 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
408 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
409 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
410 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
415 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
416 uint32_t value
, int regnum
)
418 int retval
= ERROR_OK
;
419 uint8_t Rd
= regnum
&0xFF;
421 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
422 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
424 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
426 /* Check that DCCRX is not full */
427 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
428 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
429 if (retval
!= ERROR_OK
)
431 if (dscr
& DSCR_DTR_RX_FULL
) {
432 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
433 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
434 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
436 if (retval
!= ERROR_OK
)
443 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
444 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
445 retval
= mem_ap_sel_write_u32(swjdp
, armv7a
->debug_ap
,
446 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
447 if (retval
!= ERROR_OK
)
451 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
452 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
455 if (retval
!= ERROR_OK
)
457 } else if (Rd
== 15) {
458 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
461 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
463 if (retval
!= ERROR_OK
)
465 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
466 if (retval
!= ERROR_OK
)
469 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
470 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
472 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
474 if (retval
!= ERROR_OK
)
476 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
478 if (retval
!= ERROR_OK
)
481 /* "Prefetch flush" after modifying execution status in CPSR */
483 retval
= cortex_a_exec_opcode(target
,
484 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
486 if (retval
!= ERROR_OK
)
494 /* Write to memory mapped registers directly with no cache or mmu handling */
495 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
500 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
501 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
503 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
, address
, value
);
509 * Cortex-A implementation of Debug Programmer's Model
511 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
512 * so there's no need to poll for it before executing an instruction.
514 * NOTE that in several of these cases the "stall" mode might be useful.
515 * It'd let us queue a few operations together... prepare/finish might
516 * be the places to enable/disable that mode.
519 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
521 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
524 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
526 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
527 return mem_ap_sel_write_u32(a
->armv7a_common
.arm
.dap
,
528 a
->armv7a_common
.debug_ap
, a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
531 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
534 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
535 uint32_t dscr
= DSCR_INSTR_COMP
;
541 /* Wait for DTRRXfull */
542 long long then
= timeval_ms();
543 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
544 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
545 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
547 if (retval
!= ERROR_OK
)
549 if (timeval_ms() > then
+ 1000) {
550 LOG_ERROR("Timeout waiting for read dcc");
555 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
556 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
557 if (retval
!= ERROR_OK
)
559 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
567 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
569 struct cortex_a_common
*a
= dpm_to_a(dpm
);
570 struct adiv5_dap
*swjdp
= a
->armv7a_common
.arm
.dap
;
574 /* set up invariant: INSTR_COMP is set after ever DPM operation */
575 long long then
= timeval_ms();
577 retval
= mem_ap_sel_read_atomic_u32(swjdp
, a
->armv7a_common
.debug_ap
,
578 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
580 if (retval
!= ERROR_OK
)
582 if ((dscr
& DSCR_INSTR_COMP
) != 0)
584 if (timeval_ms() > then
+ 1000) {
585 LOG_ERROR("Timeout waiting for dpm prepare");
590 /* this "should never happen" ... */
591 if (dscr
& DSCR_DTR_RX_FULL
) {
592 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
594 retval
= cortex_a_exec_opcode(
595 a
->armv7a_common
.arm
.target
,
596 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
598 if (retval
!= ERROR_OK
)
605 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
607 /* REVISIT what could be done here? */
611 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
612 uint32_t opcode
, uint32_t data
)
614 struct cortex_a_common
*a
= dpm_to_a(dpm
);
616 uint32_t dscr
= DSCR_INSTR_COMP
;
618 retval
= cortex_a_write_dcc(a
, data
);
619 if (retval
!= ERROR_OK
)
622 return cortex_a_exec_opcode(
623 a
->armv7a_common
.arm
.target
,
628 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
629 uint32_t opcode
, uint32_t data
)
631 struct cortex_a_common
*a
= dpm_to_a(dpm
);
632 uint32_t dscr
= DSCR_INSTR_COMP
;
635 retval
= cortex_a_write_dcc(a
, data
);
636 if (retval
!= ERROR_OK
)
639 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
640 retval
= cortex_a_exec_opcode(
641 a
->armv7a_common
.arm
.target
,
642 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
644 if (retval
!= ERROR_OK
)
647 /* then the opcode, taking data from R0 */
648 retval
= cortex_a_exec_opcode(
649 a
->armv7a_common
.arm
.target
,
656 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
658 struct target
*target
= dpm
->arm
->target
;
659 uint32_t dscr
= DSCR_INSTR_COMP
;
661 /* "Prefetch flush" after modifying execution status in CPSR */
662 return cortex_a_exec_opcode(target
,
663 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
667 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
668 uint32_t opcode
, uint32_t *data
)
670 struct cortex_a_common
*a
= dpm_to_a(dpm
);
672 uint32_t dscr
= DSCR_INSTR_COMP
;
674 /* the opcode, writing data to DCC */
675 retval
= cortex_a_exec_opcode(
676 a
->armv7a_common
.arm
.target
,
679 if (retval
!= ERROR_OK
)
682 return cortex_a_read_dcc(a
, data
, &dscr
);
686 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
687 uint32_t opcode
, uint32_t *data
)
689 struct cortex_a_common
*a
= dpm_to_a(dpm
);
690 uint32_t dscr
= DSCR_INSTR_COMP
;
693 /* the opcode, writing data to R0 */
694 retval
= cortex_a_exec_opcode(
695 a
->armv7a_common
.arm
.target
,
698 if (retval
!= ERROR_OK
)
701 /* write R0 to DCC */
702 retval
= cortex_a_exec_opcode(
703 a
->armv7a_common
.arm
.target
,
704 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
706 if (retval
!= ERROR_OK
)
709 return cortex_a_read_dcc(a
, data
, &dscr
);
712 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
713 uint32_t addr
, uint32_t control
)
715 struct cortex_a_common
*a
= dpm_to_a(dpm
);
716 uint32_t vr
= a
->armv7a_common
.debug_base
;
717 uint32_t cr
= a
->armv7a_common
.debug_base
;
721 case 0 ... 15: /* breakpoints */
722 vr
+= CPUDBG_BVR_BASE
;
723 cr
+= CPUDBG_BCR_BASE
;
725 case 16 ... 31: /* watchpoints */
726 vr
+= CPUDBG_WVR_BASE
;
727 cr
+= CPUDBG_WCR_BASE
;
736 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
737 (unsigned) vr
, (unsigned) cr
);
739 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
741 if (retval
!= ERROR_OK
)
743 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
748 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
750 struct cortex_a_common
*a
= dpm_to_a(dpm
);
755 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
758 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
766 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
768 /* clear control register */
769 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
772 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
774 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
777 dpm
->arm
= &a
->armv7a_common
.arm
;
780 dpm
->prepare
= cortex_a_dpm_prepare
;
781 dpm
->finish
= cortex_a_dpm_finish
;
783 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
784 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
785 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
787 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
788 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
790 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
791 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
793 retval
= arm_dpm_setup(dpm
);
794 if (retval
== ERROR_OK
)
795 retval
= arm_dpm_initialize(dpm
);
799 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
801 struct target_list
*head
;
805 while (head
!= (struct target_list
*)NULL
) {
807 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
813 static int cortex_a_halt(struct target
*target
);
815 static int cortex_a_halt_smp(struct target
*target
)
818 struct target_list
*head
;
821 while (head
!= (struct target_list
*)NULL
) {
823 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
824 retval
+= cortex_a_halt(curr
);
830 static int update_halt_gdb(struct target
*target
)
833 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
834 target
->gdb_service
->target
= target
;
835 target
->gdb_service
->core
[0] = target
->coreid
;
836 retval
+= cortex_a_halt_smp(target
);
842 * Cortex-A Run control
845 static int cortex_a_poll(struct target
*target
)
847 int retval
= ERROR_OK
;
849 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
850 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
851 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
852 enum target_state prev_target_state
= target
->state
;
853 /* toggle to another core is done by gdb as follow */
854 /* maint packet J core_id */
856 /* the next polling trigger an halt event sent to gdb */
857 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
858 (target
->gdb_service
) &&
859 (target
->gdb_service
->target
== NULL
)) {
860 target
->gdb_service
->target
=
861 get_cortex_a(target
, target
->gdb_service
->core
[1]);
862 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
865 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
866 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
867 if (retval
!= ERROR_OK
)
869 cortex_a
->cpudbg_dscr
= dscr
;
871 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
872 if (prev_target_state
!= TARGET_HALTED
) {
873 /* We have a halting debug event */
874 LOG_DEBUG("Target halted");
875 target
->state
= TARGET_HALTED
;
876 if ((prev_target_state
== TARGET_RUNNING
)
877 || (prev_target_state
== TARGET_UNKNOWN
)
878 || (prev_target_state
== TARGET_RESET
)) {
879 retval
= cortex_a_debug_entry(target
);
880 if (retval
!= ERROR_OK
)
883 retval
= update_halt_gdb(target
);
884 if (retval
!= ERROR_OK
)
887 target_call_event_callbacks(target
,
888 TARGET_EVENT_HALTED
);
890 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
893 retval
= cortex_a_debug_entry(target
);
894 if (retval
!= ERROR_OK
)
897 retval
= update_halt_gdb(target
);
898 if (retval
!= ERROR_OK
)
902 target_call_event_callbacks(target
,
903 TARGET_EVENT_DEBUG_HALTED
);
906 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
907 target
->state
= TARGET_RUNNING
;
909 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
910 target
->state
= TARGET_UNKNOWN
;
916 static int cortex_a_halt(struct target
*target
)
918 int retval
= ERROR_OK
;
920 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
921 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
924 * Tell the core to be halted by writing DRCR with 0x1
925 * and then wait for the core to be halted.
927 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
928 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
929 if (retval
!= ERROR_OK
)
933 * enter halting debug mode
935 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
936 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
937 if (retval
!= ERROR_OK
)
940 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
941 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
942 if (retval
!= ERROR_OK
)
945 long long then
= timeval_ms();
947 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
948 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
949 if (retval
!= ERROR_OK
)
951 if ((dscr
& DSCR_CORE_HALTED
) != 0)
953 if (timeval_ms() > then
+ 1000) {
954 LOG_ERROR("Timeout waiting for halt");
959 target
->debug_reason
= DBG_REASON_DBGRQ
;
964 static int cortex_a_internal_restore(struct target
*target
, int current
,
965 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
967 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
968 struct arm
*arm
= &armv7a
->arm
;
972 if (!debug_execution
)
973 target_free_all_working_areas(target
);
976 if (debug_execution
) {
977 /* Disable interrupts */
978 /* We disable interrupts in the PRIMASK register instead of
979 * masking with C_MASKINTS,
980 * This is probably the same issue as Cortex-M3 Errata 377493:
981 * C_MASKINTS in parallel with disabled interrupts can cause
982 * local faults to not be taken. */
983 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
984 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
985 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
987 /* Make sure we are in Thumb mode */
988 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
989 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
991 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
992 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
996 /* current = 1: continue on current pc, otherwise continue at <address> */
997 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
999 resume_pc
= *address
;
1001 *address
= resume_pc
;
1003 /* Make sure that the Armv7 gdb thumb fixups does not
1004 * kill the return address
1006 switch (arm
->core_state
) {
1008 resume_pc
&= 0xFFFFFFFC;
1010 case ARM_STATE_THUMB
:
1011 case ARM_STATE_THUMB_EE
:
1012 /* When the return address is loaded into PC
1013 * bit 0 must be 1 to stay in Thumb state
1017 case ARM_STATE_JAZELLE
:
1018 LOG_ERROR("How do I resume into Jazelle state??");
1021 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1022 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1025 /* restore dpm_mode at system halt */
1026 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1027 /* called it now before restoring context because it uses cpu
1028 * register r0 for restoring cp15 control register */
1029 retval
= cortex_a_restore_cp15_control_reg(target
);
1030 if (retval
!= ERROR_OK
)
1032 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1033 if (retval
!= ERROR_OK
)
1035 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1036 target
->state
= TARGET_RUNNING
;
1038 /* registers are now invalid */
1039 register_cache_invalidate(arm
->core_cache
);
1042 /* the front-end may request us not to handle breakpoints */
1043 if (handle_breakpoints
) {
1044 /* Single step past breakpoint at current address */
1045 breakpoint
= breakpoint_find(target
, resume_pc
);
1047 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1048 cortex_m3_unset_breakpoint(target
, breakpoint
);
1049 cortex_m3_single_step_core(target
);
1050 cortex_m3_set_breakpoint(target
, breakpoint
);
1058 static int cortex_a_internal_restart(struct target
*target
)
1060 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1061 struct arm
*arm
= &armv7a
->arm
;
1062 struct adiv5_dap
*swjdp
= arm
->dap
;
1066 * * Restart core and wait for it to be started. Clear ITRen and sticky
1067 * * exception flags: see ARMv7 ARM, C5.9.
1069 * REVISIT: for single stepping, we probably want to
1070 * disable IRQs by default, with optional override...
1073 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1074 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1075 if (retval
!= ERROR_OK
)
1078 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1079 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1081 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1082 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1083 if (retval
!= ERROR_OK
)
1086 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1087 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1088 DRCR_CLEAR_EXCEPTIONS
);
1089 if (retval
!= ERROR_OK
)
1092 long long then
= timeval_ms();
1094 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1095 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1096 if (retval
!= ERROR_OK
)
1098 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1100 if (timeval_ms() > then
+ 1000) {
1101 LOG_ERROR("Timeout waiting for resume");
1106 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1107 target
->state
= TARGET_RUNNING
;
1109 /* registers are now invalid */
1110 register_cache_invalidate(arm
->core_cache
);
1115 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1118 struct target_list
*head
;
1119 struct target
*curr
;
1121 head
= target
->head
;
1122 while (head
!= (struct target_list
*)NULL
) {
1123 curr
= head
->target
;
1124 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
1125 /* resume current address , not in step mode */
1126 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1127 handle_breakpoints
, 0);
1128 retval
+= cortex_a_internal_restart(curr
);
1136 static int cortex_a_resume(struct target
*target
, int current
,
1137 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1140 /* dummy resume for smp toggle in order to reduce gdb impact */
1141 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1142 /* simulate a start and halt of target */
1143 target
->gdb_service
->target
= NULL
;
1144 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1145 /* fake resume at next poll we play the target core[1], see poll*/
1146 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1149 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1151 target
->gdb_service
->core
[0] = -1;
1152 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1153 if (retval
!= ERROR_OK
)
1156 cortex_a_internal_restart(target
);
1158 if (!debug_execution
) {
1159 target
->state
= TARGET_RUNNING
;
1160 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1161 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1163 target
->state
= TARGET_DEBUG_RUNNING
;
1164 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1165 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1171 static int cortex_a_debug_entry(struct target
*target
)
1174 uint32_t regfile
[16], cpsr
, dscr
;
1175 int retval
= ERROR_OK
;
1176 struct working_area
*regfile_working_area
= NULL
;
1177 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1178 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1179 struct arm
*arm
= &armv7a
->arm
;
1180 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1183 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1185 /* REVISIT surely we should not re-read DSCR !! */
1186 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1187 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1188 if (retval
!= ERROR_OK
)
1191 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1192 * imprecise data aborts get discarded by issuing a Data
1193 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1196 /* Enable the ITR execution once we are in debug mode */
1197 dscr
|= DSCR_ITR_EN
;
1198 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1199 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1200 if (retval
!= ERROR_OK
)
1203 /* Examine debug reason */
1204 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1206 /* save address of instruction that triggered the watchpoint? */
1207 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1210 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1211 armv7a
->debug_base
+ CPUDBG_WFAR
,
1213 if (retval
!= ERROR_OK
)
1215 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1218 /* REVISIT fast_reg_read is never set ... */
1220 /* Examine target state and mode */
1221 if (cortex_a
->fast_reg_read
)
1222 target_alloc_working_area(target
, 64, ®file_working_area
);
1224 /* First load register acessible through core debug port*/
1225 if (!regfile_working_area
)
1226 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1228 retval
= cortex_a_read_regs_through_mem(target
,
1229 regfile_working_area
->address
, regfile
);
1231 target_free_working_area(target
, regfile_working_area
);
1232 if (retval
!= ERROR_OK
)
1235 /* read Current PSR */
1236 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1237 /* store current cpsr */
1238 if (retval
!= ERROR_OK
)
1241 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1243 arm_set_cpsr(arm
, cpsr
);
1246 for (i
= 0; i
<= ARM_PC
; i
++) {
1247 reg
= arm_reg_current(arm
, i
);
1249 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1254 /* Fixup PC Resume Address */
1255 if (cpsr
& (1 << 5)) {
1256 /* T bit set for Thumb or ThumbEE state */
1257 regfile
[ARM_PC
] -= 4;
1260 regfile
[ARM_PC
] -= 8;
1264 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1265 reg
->dirty
= reg
->valid
;
1269 /* TODO, Move this */
1270 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1271 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1272 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1274 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1275 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1277 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1278 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1281 /* Are we in an exception handler */
1282 /* armv4_5->exception_number = 0; */
1283 if (armv7a
->post_debug_entry
) {
1284 retval
= armv7a
->post_debug_entry(target
);
1285 if (retval
!= ERROR_OK
)
1292 static int cortex_a_post_debug_entry(struct target
*target
)
1294 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1295 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1298 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1299 retval
= armv7a
->arm
.mrc(target
, 15,
1300 0, 0, /* op1, op2 */
1301 1, 0, /* CRn, CRm */
1302 &cortex_a
->cp15_control_reg
);
1303 if (retval
!= ERROR_OK
)
1305 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1306 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1308 if (armv7a
->armv7a_mmu
.armv7a_cache
.ctype
== -1)
1309 armv7a_identify_cache(target
);
1311 if (armv7a
->is_armv7r
) {
1312 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1314 armv7a
->armv7a_mmu
.mmu_enabled
=
1315 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1317 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1318 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1319 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1320 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1321 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1326 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1328 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1329 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1333 int retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1334 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1335 if (ERROR_OK
!= retval
)
1338 /* clear bitfield */
1341 dscr
|= value
& bit_mask
;
1343 /* write new DSCR */
1344 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1345 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1349 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1350 int handle_breakpoints
)
1352 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1353 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1354 struct arm
*arm
= &armv7a
->arm
;
1355 struct breakpoint
*breakpoint
= NULL
;
1356 struct breakpoint stepbreakpoint
;
1360 if (target
->state
!= TARGET_HALTED
) {
1361 LOG_WARNING("target not halted");
1362 return ERROR_TARGET_NOT_HALTED
;
1365 /* current = 1: continue on current pc, otherwise continue at <address> */
1368 buf_set_u32(r
->value
, 0, 32, address
);
1370 address
= buf_get_u32(r
->value
, 0, 32);
1372 /* The front-end may request us not to handle breakpoints.
1373 * But since Cortex-A uses breakpoint for single step,
1374 * we MUST handle breakpoints.
1376 handle_breakpoints
= 1;
1377 if (handle_breakpoints
) {
1378 breakpoint
= breakpoint_find(target
, address
);
1380 cortex_a_unset_breakpoint(target
, breakpoint
);
1383 /* Setup single step breakpoint */
1384 stepbreakpoint
.address
= address
;
1385 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1387 stepbreakpoint
.type
= BKPT_HARD
;
1388 stepbreakpoint
.set
= 0;
1390 /* Disable interrupts during single step if requested */
1391 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1392 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1393 if (ERROR_OK
!= retval
)
1397 /* Break on IVA mismatch */
1398 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1400 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1402 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1403 if (retval
!= ERROR_OK
)
1406 long long then
= timeval_ms();
1407 while (target
->state
!= TARGET_HALTED
) {
1408 retval
= cortex_a_poll(target
);
1409 if (retval
!= ERROR_OK
)
1411 if (timeval_ms() > then
+ 1000) {
1412 LOG_ERROR("timeout waiting for target halt");
1417 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1419 /* Re-enable interrupts if they were disabled */
1420 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1421 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1422 if (ERROR_OK
!= retval
)
1427 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1430 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1432 if (target
->state
!= TARGET_HALTED
)
1433 LOG_DEBUG("target stepped");
1438 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1440 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1444 if (armv7a
->pre_restore_context
)
1445 armv7a
->pre_restore_context(target
);
1447 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1451 * Cortex-A Breakpoint and watchpoint functions
1454 /* Setup hardware Breakpoint Register Pair */
1455 static int cortex_a_set_breakpoint(struct target
*target
,
1456 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1461 uint8_t byte_addr_select
= 0x0F;
1462 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1463 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1464 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1466 if (breakpoint
->set
) {
1467 LOG_WARNING("breakpoint already set");
1471 if (breakpoint
->type
== BKPT_HARD
) {
1472 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1474 if (brp_i
>= cortex_a
->brp_num
) {
1475 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1476 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1478 breakpoint
->set
= brp_i
+ 1;
1479 if (breakpoint
->length
== 2)
1480 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1481 control
= ((matchmode
& 0x7) << 20)
1482 | (byte_addr_select
<< 5)
1484 brp_list
[brp_i
].used
= 1;
1485 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1486 brp_list
[brp_i
].control
= control
;
1487 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1488 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1489 brp_list
[brp_i
].value
);
1490 if (retval
!= ERROR_OK
)
1492 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1493 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1494 brp_list
[brp_i
].control
);
1495 if (retval
!= ERROR_OK
)
1497 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1498 brp_list
[brp_i
].control
,
1499 brp_list
[brp_i
].value
);
1500 } else if (breakpoint
->type
== BKPT_SOFT
) {
1502 if (breakpoint
->length
== 2)
1503 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1505 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1506 retval
= target_read_memory(target
,
1507 breakpoint
->address
& 0xFFFFFFFE,
1508 breakpoint
->length
, 1,
1509 breakpoint
->orig_instr
);
1510 if (retval
!= ERROR_OK
)
1512 retval
= target_write_memory(target
,
1513 breakpoint
->address
& 0xFFFFFFFE,
1514 breakpoint
->length
, 1, code
);
1515 if (retval
!= ERROR_OK
)
1517 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1523 static int cortex_a_set_context_breakpoint(struct target
*target
,
1524 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1526 int retval
= ERROR_FAIL
;
1529 uint8_t byte_addr_select
= 0x0F;
1530 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1531 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1532 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1534 if (breakpoint
->set
) {
1535 LOG_WARNING("breakpoint already set");
1538 /*check available context BRPs*/
1539 while ((brp_list
[brp_i
].used
||
1540 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1543 if (brp_i
>= cortex_a
->brp_num
) {
1544 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1548 breakpoint
->set
= brp_i
+ 1;
1549 control
= ((matchmode
& 0x7) << 20)
1550 | (byte_addr_select
<< 5)
1552 brp_list
[brp_i
].used
= 1;
1553 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1554 brp_list
[brp_i
].control
= control
;
1555 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1556 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1557 brp_list
[brp_i
].value
);
1558 if (retval
!= ERROR_OK
)
1560 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1561 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1562 brp_list
[brp_i
].control
);
1563 if (retval
!= ERROR_OK
)
1565 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1566 brp_list
[brp_i
].control
,
1567 brp_list
[brp_i
].value
);
1572 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1574 int retval
= ERROR_FAIL
;
1575 int brp_1
= 0; /* holds the contextID pair */
1576 int brp_2
= 0; /* holds the IVA pair */
1577 uint32_t control_CTX
, control_IVA
;
1578 uint8_t CTX_byte_addr_select
= 0x0F;
1579 uint8_t IVA_byte_addr_select
= 0x0F;
1580 uint8_t CTX_machmode
= 0x03;
1581 uint8_t IVA_machmode
= 0x01;
1582 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1583 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1584 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1586 if (breakpoint
->set
) {
1587 LOG_WARNING("breakpoint already set");
1590 /*check available context BRPs*/
1591 while ((brp_list
[brp_1
].used
||
1592 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1595 printf("brp(CTX) found num: %d\n", brp_1
);
1596 if (brp_1
>= cortex_a
->brp_num
) {
1597 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1601 while ((brp_list
[brp_2
].used
||
1602 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1605 printf("brp(IVA) found num: %d\n", brp_2
);
1606 if (brp_2
>= cortex_a
->brp_num
) {
1607 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1611 breakpoint
->set
= brp_1
+ 1;
1612 breakpoint
->linked_BRP
= brp_2
;
1613 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1616 | (CTX_byte_addr_select
<< 5)
1618 brp_list
[brp_1
].used
= 1;
1619 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1620 brp_list
[brp_1
].control
= control_CTX
;
1621 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1622 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1623 brp_list
[brp_1
].value
);
1624 if (retval
!= ERROR_OK
)
1626 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1627 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1628 brp_list
[brp_1
].control
);
1629 if (retval
!= ERROR_OK
)
1632 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1634 | (IVA_byte_addr_select
<< 5)
1636 brp_list
[brp_2
].used
= 1;
1637 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1638 brp_list
[brp_2
].control
= control_IVA
;
1639 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1640 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1641 brp_list
[brp_2
].value
);
1642 if (retval
!= ERROR_OK
)
1644 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1645 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1646 brp_list
[brp_2
].control
);
1647 if (retval
!= ERROR_OK
)
1653 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1656 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1657 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1658 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1660 if (!breakpoint
->set
) {
1661 LOG_WARNING("breakpoint not set");
1665 if (breakpoint
->type
== BKPT_HARD
) {
1666 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1667 int brp_i
= breakpoint
->set
- 1;
1668 int brp_j
= breakpoint
->linked_BRP
;
1669 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1670 LOG_DEBUG("Invalid BRP number in breakpoint");
1673 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1674 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1675 brp_list
[brp_i
].used
= 0;
1676 brp_list
[brp_i
].value
= 0;
1677 brp_list
[brp_i
].control
= 0;
1678 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1679 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1680 brp_list
[brp_i
].control
);
1681 if (retval
!= ERROR_OK
)
1683 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1684 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1685 brp_list
[brp_i
].value
);
1686 if (retval
!= ERROR_OK
)
1688 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1689 LOG_DEBUG("Invalid BRP number in breakpoint");
1692 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1693 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1694 brp_list
[brp_j
].used
= 0;
1695 brp_list
[brp_j
].value
= 0;
1696 brp_list
[brp_j
].control
= 0;
1697 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1698 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1699 brp_list
[brp_j
].control
);
1700 if (retval
!= ERROR_OK
)
1702 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1703 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1704 brp_list
[brp_j
].value
);
1705 if (retval
!= ERROR_OK
)
1707 breakpoint
->linked_BRP
= 0;
1708 breakpoint
->set
= 0;
1712 int brp_i
= breakpoint
->set
- 1;
1713 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1714 LOG_DEBUG("Invalid BRP number in breakpoint");
1717 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1718 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1719 brp_list
[brp_i
].used
= 0;
1720 brp_list
[brp_i
].value
= 0;
1721 brp_list
[brp_i
].control
= 0;
1722 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1723 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1724 brp_list
[brp_i
].control
);
1725 if (retval
!= ERROR_OK
)
1727 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1728 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1729 brp_list
[brp_i
].value
);
1730 if (retval
!= ERROR_OK
)
1732 breakpoint
->set
= 0;
1736 /* restore original instruction (kept in target endianness) */
1737 if (breakpoint
->length
== 4) {
1738 retval
= target_write_memory(target
,
1739 breakpoint
->address
& 0xFFFFFFFE,
1740 4, 1, breakpoint
->orig_instr
);
1741 if (retval
!= ERROR_OK
)
1744 retval
= target_write_memory(target
,
1745 breakpoint
->address
& 0xFFFFFFFE,
1746 2, 1, breakpoint
->orig_instr
);
1747 if (retval
!= ERROR_OK
)
1751 breakpoint
->set
= 0;
1756 static int cortex_a_add_breakpoint(struct target
*target
,
1757 struct breakpoint
*breakpoint
)
1759 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1761 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1762 LOG_INFO("no hardware breakpoint available");
1763 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1766 if (breakpoint
->type
== BKPT_HARD
)
1767 cortex_a
->brp_num_available
--;
1769 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1772 static int cortex_a_add_context_breakpoint(struct target
*target
,
1773 struct breakpoint
*breakpoint
)
1775 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1777 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1778 LOG_INFO("no hardware breakpoint available");
1779 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1782 if (breakpoint
->type
== BKPT_HARD
)
1783 cortex_a
->brp_num_available
--;
1785 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1788 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1789 struct breakpoint
*breakpoint
)
1791 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1793 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1794 LOG_INFO("no hardware breakpoint available");
1795 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1798 if (breakpoint
->type
== BKPT_HARD
)
1799 cortex_a
->brp_num_available
--;
1801 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1805 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1807 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1810 /* It is perfectly possible to remove breakpoints while the target is running */
1811 if (target
->state
!= TARGET_HALTED
) {
1812 LOG_WARNING("target not halted");
1813 return ERROR_TARGET_NOT_HALTED
;
1817 if (breakpoint
->set
) {
1818 cortex_a_unset_breakpoint(target
, breakpoint
);
1819 if (breakpoint
->type
== BKPT_HARD
)
1820 cortex_a
->brp_num_available
++;
1828 * Cortex-A Reset functions
1831 static int cortex_a_assert_reset(struct target
*target
)
1833 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1837 /* FIXME when halt is requested, make it work somehow... */
1839 /* Issue some kind of warm reset. */
1840 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1841 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1842 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1843 /* REVISIT handle "pulls" cases, if there's
1844 * hardware that needs them to work.
1846 jtag_add_reset(0, 1);
1848 LOG_ERROR("%s: how to reset?", target_name(target
));
1852 /* registers are now invalid */
1853 register_cache_invalidate(armv7a
->arm
.core_cache
);
1855 target
->state
= TARGET_RESET
;
1860 static int cortex_a_deassert_reset(struct target
*target
)
1866 /* be certain SRST is off */
1867 jtag_add_reset(0, 0);
1869 retval
= cortex_a_poll(target
);
1870 if (retval
!= ERROR_OK
)
1873 if (target
->reset_halt
) {
1874 if (target
->state
!= TARGET_HALTED
) {
1875 LOG_WARNING("%s: ran after reset and before halt ...",
1876 target_name(target
));
1877 retval
= target_halt(target
);
1878 if (retval
!= ERROR_OK
)
1886 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1888 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1889 * New desired mode must be in mode. Current value of DSCR must be in
1890 * *dscr, which is updated with new value.
1892 * This function elides actually sending the mode-change over the debug
1893 * interface if the mode is already set as desired.
1895 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1896 if (new_dscr
!= *dscr
) {
1897 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1898 int retval
= mem_ap_sel_write_atomic_u32(armv7a
->arm
.dap
,
1899 armv7a
->debug_ap
, armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1900 if (retval
== ERROR_OK
)
1908 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1909 uint32_t value
, uint32_t *dscr
)
1911 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1912 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1913 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1914 long long then
= timeval_ms();
1917 while ((*dscr
& mask
) != value
) {
1918 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1919 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1920 if (retval
!= ERROR_OK
)
1922 if (timeval_ms() > then
+ 1000) {
1923 LOG_ERROR("timeout waiting for DSCR bit change");
1930 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1931 uint32_t *data
, uint32_t *dscr
)
1934 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1935 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1937 /* Move from coprocessor to R0. */
1938 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1939 if (retval
!= ERROR_OK
)
1942 /* Move from R0 to DTRTX. */
1943 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1944 if (retval
!= ERROR_OK
)
1947 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1948 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1949 * must also check TXfull_l). Most of the time this will be free
1950 * because TXfull_l will be set immediately and cached in dscr. */
1951 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1952 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1953 if (retval
!= ERROR_OK
)
1956 /* Read the value transferred to DTRTX. */
1957 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
1958 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1959 if (retval
!= ERROR_OK
)
1965 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
1966 uint32_t *dfsr
, uint32_t *dscr
)
1971 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
1972 if (retval
!= ERROR_OK
)
1977 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
1978 if (retval
!= ERROR_OK
)
1985 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
1986 uint32_t data
, uint32_t *dscr
)
1989 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1990 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
1992 /* Write the value into DTRRX. */
1993 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
1994 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
1995 if (retval
!= ERROR_OK
)
1998 /* Move from DTRRX to R0. */
1999 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2000 if (retval
!= ERROR_OK
)
2003 /* Move from R0 to coprocessor. */
2004 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2005 if (retval
!= ERROR_OK
)
2008 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2009 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2010 * check RXfull_l). Most of the time this will be free because RXfull_l
2011 * will be cleared immediately and cached in dscr. */
2012 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2013 if (retval
!= ERROR_OK
)
2019 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2020 uint32_t dfsr
, uint32_t *dscr
)
2024 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2025 if (retval
!= ERROR_OK
)
2028 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2029 if (retval
!= ERROR_OK
)
2035 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2037 uint32_t status
, upper4
;
2039 if (dfsr
& (1 << 9)) {
2041 status
= dfsr
& 0x3f;
2042 upper4
= status
>> 2;
2043 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2044 return ERROR_TARGET_TRANSLATION_FAULT
;
2045 else if (status
== 33)
2046 return ERROR_TARGET_UNALIGNED_ACCESS
;
2048 return ERROR_TARGET_DATA_ABORT
;
2050 /* Normal format. */
2051 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2053 return ERROR_TARGET_UNALIGNED_ACCESS
;
2054 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2055 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2056 return ERROR_TARGET_TRANSLATION_FAULT
;
2058 return ERROR_TARGET_DATA_ABORT
;
2062 static int cortex_a_write_apb_ab_memory_slow(struct target
*target
,
2063 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2065 /* Writes count objects of size size from *buffer. Old value of DSCR must
2066 * be in *dscr; updated to new value. This is slow because it works for
2067 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2068 * the address is aligned, cortex_a_write_apb_ab_memory_fast should be
2071 * - Address is in R0.
2072 * - R0 is marked dirty.
2074 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2075 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2076 struct arm
*arm
= &armv7a
->arm
;
2079 /* Mark register R1 as dirty, to use for transferring data. */
2080 arm_reg_current(arm
, 1)->dirty
= true;
2082 /* Switch to non-blocking mode if not already in that mode. */
2083 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2084 if (retval
!= ERROR_OK
)
2087 /* Go through the objects. */
2089 /* Write the value to store into DTRRX. */
2090 uint32_t data
, opcode
;
2094 data
= target_buffer_get_u16(target
, buffer
);
2096 data
= target_buffer_get_u32(target
, buffer
);
2097 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2098 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2099 if (retval
!= ERROR_OK
)
2102 /* Transfer the value from DTRRX to R1. */
2103 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2104 if (retval
!= ERROR_OK
)
2107 /* Write the value transferred to R1 into memory. */
2109 opcode
= ARMV4_5_STRB_IP(1, 0);
2111 opcode
= ARMV4_5_STRH_IP(1, 0);
2113 opcode
= ARMV4_5_STRW_IP(1, 0);
2114 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2115 if (retval
!= ERROR_OK
)
2118 /* Check for faults and return early. */
2119 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2120 return ERROR_OK
; /* A data fault is not considered a system failure. */
2122 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2123 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2124 * must also check RXfull_l). Most of the time this will be free
2125 * because RXfull_l will be cleared immediately and cached in dscr. */
2126 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2127 if (retval
!= ERROR_OK
)
2138 static int cortex_a_write_apb_ab_memory_fast(struct target
*target
,
2139 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2141 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2142 * in *dscr; updated to new value. This is fast but only works for
2143 * word-sized objects at aligned addresses.
2145 * - Address is in R0 and must be a multiple of 4.
2146 * - R0 is marked dirty.
2148 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2149 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2152 /* Switch to fast mode if not already in that mode. */
2153 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2154 if (retval
!= ERROR_OK
)
2157 /* Latch STC instruction. */
2158 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2159 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2160 if (retval
!= ERROR_OK
)
2163 /* Transfer all the data and issue all the instructions. */
2164 return mem_ap_sel_write_buf_noincr(swjdp
, armv7a
->debug_ap
, buffer
,
2165 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2168 static int cortex_a_write_apb_ab_memory(struct target
*target
,
2169 uint32_t address
, uint32_t size
,
2170 uint32_t count
, const uint8_t *buffer
)
2172 /* Write memory through APB-AP. */
2173 int retval
, final_retval
;
2174 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2175 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2176 struct arm
*arm
= &armv7a
->arm
;
2177 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2179 LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2180 address
, size
, count
);
2181 if (target
->state
!= TARGET_HALTED
) {
2182 LOG_WARNING("target not halted");
2183 return ERROR_TARGET_NOT_HALTED
;
2189 /* Clear any abort. */
2190 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2191 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2192 if (retval
!= ERROR_OK
)
2196 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2197 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2198 if (retval
!= ERROR_OK
)
2201 /* Switch to non-blocking mode if not already in that mode. */
2202 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2203 if (retval
!= ERROR_OK
)
2206 /* Mark R0 as dirty. */
2207 arm_reg_current(arm
, 0)->dirty
= true;
2209 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2210 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2211 if (retval
!= ERROR_OK
)
2214 /* Get the memory address into R0. */
2215 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2216 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2217 if (retval
!= ERROR_OK
)
2219 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2220 if (retval
!= ERROR_OK
)
2223 if (size
== 4 && (address
% 4) == 0) {
2224 /* We are doing a word-aligned transfer, so use fast mode. */
2225 retval
= cortex_a_write_apb_ab_memory_fast(target
, count
, buffer
, &dscr
);
2227 /* Use slow path. */
2228 retval
= cortex_a_write_apb_ab_memory_slow(target
, size
, count
, buffer
, &dscr
);
2232 final_retval
= retval
;
2234 /* Switch to non-blocking mode if not already in that mode. */
2235 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2236 if (final_retval
== ERROR_OK
)
2237 final_retval
= retval
;
2239 /* Wait for last issued instruction to complete. */
2240 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2241 if (final_retval
== ERROR_OK
)
2242 final_retval
= retval
;
2244 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2245 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2246 * check RXfull_l). Most of the time this will be free because RXfull_l
2247 * will be cleared immediately and cached in dscr. However, don’t do this
2248 * if there is fault, because then the instruction might not have completed
2250 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2251 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2252 if (retval
!= ERROR_OK
)
2256 /* If there were any sticky abort flags, clear them. */
2257 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2259 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2260 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2261 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2266 /* Handle synchronous data faults. */
2267 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2268 if (final_retval
== ERROR_OK
) {
2269 /* Final return value will reflect cause of fault. */
2270 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2271 if (retval
== ERROR_OK
) {
2272 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2273 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2275 final_retval
= retval
;
2277 /* Fault destroyed DFAR/DFSR; restore them. */
2278 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2279 if (retval
!= ERROR_OK
)
2280 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2283 /* Handle asynchronous data faults. */
2284 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2285 if (final_retval
== ERROR_OK
)
2286 /* No other error has been recorded so far, so keep this one. */
2287 final_retval
= ERROR_TARGET_DATA_ABORT
;
2290 /* If the DCC is nonempty, clear it. */
2291 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2293 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2294 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2295 if (final_retval
== ERROR_OK
)
2296 final_retval
= retval
;
2298 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2299 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2300 if (final_retval
== ERROR_OK
)
2301 final_retval
= retval
;
2305 return final_retval
;
2308 static int cortex_a_read_apb_ab_memory_slow(struct target
*target
,
2309 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2311 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2312 * in *dscr; updated to new value. This is slow because it works for
2313 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2314 * the address is aligned, cortex_a_read_apb_ab_memory_fast should be
2317 * - Address is in R0.
2318 * - R0 is marked dirty.
2320 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2321 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2322 struct arm
*arm
= &armv7a
->arm
;
2325 /* Mark register R1 as dirty, to use for transferring data. */
2326 arm_reg_current(arm
, 1)->dirty
= true;
2328 /* Switch to non-blocking mode if not already in that mode. */
2329 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2330 if (retval
!= ERROR_OK
)
2333 /* Go through the objects. */
2335 /* Issue a load of the appropriate size to R1. */
2336 uint32_t opcode
, data
;
2338 opcode
= ARMV4_5_LDRB_IP(1, 0);
2340 opcode
= ARMV4_5_LDRH_IP(1, 0);
2342 opcode
= ARMV4_5_LDRW_IP(1, 0);
2343 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2344 if (retval
!= ERROR_OK
)
2347 /* Issue a write of R1 to DTRTX. */
2348 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2349 if (retval
!= ERROR_OK
)
2352 /* Check for faults and return early. */
2353 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2354 return ERROR_OK
; /* A data fault is not considered a system failure. */
2356 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2357 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2358 * must also check TXfull_l). Most of the time this will be free
2359 * because TXfull_l will be set immediately and cached in dscr. */
2360 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2361 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2362 if (retval
!= ERROR_OK
)
2365 /* Read the value transferred to DTRTX into the buffer. */
2366 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2367 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2368 if (retval
!= ERROR_OK
)
2371 *buffer
= (uint8_t) data
;
2373 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2375 target_buffer_set_u32(target
, buffer
, data
);
2385 static int cortex_a_read_apb_ab_memory_fast(struct target
*target
,
2386 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2388 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2389 * *dscr; updated to new value. This is fast but only works for word-sized
2390 * objects at aligned addresses.
2392 * - Address is in R0 and must be a multiple of 4.
2393 * - R0 is marked dirty.
2395 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2396 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2397 uint32_t new_dscr
, u32
;
2400 /* Switch to non-blocking mode if not already in that mode. */
2401 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2402 if (retval
!= ERROR_OK
)
2406 /* Consecutively issue the LDC instruction via a write to ITR and
2407 * change to fast mode, in a single bulk copy since DSCR == ITR + 4.
2408 * The instruction is issued into the core before the mode switch. */
2410 target_buffer_set_u32(target
, command
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2411 new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | DSCR_EXT_DCC_FAST_MODE
;
2412 target_buffer_set_u32(target
, command
+ 4, new_dscr
);
2413 retval
= mem_ap_sel_write_buf(swjdp
, armv7a
->debug_ap
, command
, 4, 2,
2414 armv7a
->debug_base
+ CPUDBG_ITR
);
2415 if (retval
!= ERROR_OK
)
2419 /* Read the value transferred to DTRTX into the buffer. Due to fast
2420 * mode rules, this blocks until the instruction finishes executing and
2421 * then reissues the read instruction to read the next word from
2422 * memory. The last read of DTRTX in this call reads the second-to-last
2423 * word from memory and issues the read instruction for the last word.
2425 retval
= mem_ap_sel_read_buf_noincr(swjdp
, armv7a
->debug_ap
, buffer
,
2426 4, count
- 1, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2427 if (retval
!= ERROR_OK
)
2431 buffer
+= (count
- 1) * 4;
2433 /* Issue the LDC instruction via a write to ITR. */
2434 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2435 if (retval
!= ERROR_OK
)
2439 /* Switch to non-blocking mode if not already in that mode. */
2440 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2441 if (retval
!= ERROR_OK
)
2444 /* Wait for last issued instruction to complete. */
2445 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2446 if (retval
!= ERROR_OK
)
2449 /* Check for faults and return early. */
2450 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2451 return ERROR_OK
; /* A data fault is not considered a system failure. */
2453 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2454 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2455 * check TXfull_l). Most of the time this will be free because TXfull_l
2456 * will be set immediately and cached in dscr. */
2457 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2458 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2459 if (retval
!= ERROR_OK
)
2462 /* Read the value transferred to DTRTX into the buffer. This is the last
2464 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2465 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2466 if (retval
!= ERROR_OK
)
2468 target_buffer_set_u32(target
, buffer
, u32
);
2473 static int cortex_a_read_apb_ab_memory(struct target
*target
,
2474 uint32_t address
, uint32_t size
,
2475 uint32_t count
, uint8_t *buffer
)
2477 /* Read memory through APB-AP. */
2478 int retval
, final_retval
;
2479 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2480 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2481 struct arm
*arm
= &armv7a
->arm
;
2482 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2484 LOG_DEBUG("Reading APB-AP memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2485 address
, size
, count
);
2486 if (target
->state
!= TARGET_HALTED
) {
2487 LOG_WARNING("target not halted");
2488 return ERROR_TARGET_NOT_HALTED
;
2494 /* Clear any abort. */
2495 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2496 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2497 if (retval
!= ERROR_OK
)
2501 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2502 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2503 if (retval
!= ERROR_OK
)
2506 /* Switch to non-blocking mode if not already in that mode. */
2507 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2508 if (retval
!= ERROR_OK
)
2511 /* Mark R0 as dirty. */
2512 arm_reg_current(arm
, 0)->dirty
= true;
2514 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2515 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2516 if (retval
!= ERROR_OK
)
2519 /* Get the memory address into R0. */
2520 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2521 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2522 if (retval
!= ERROR_OK
)
2524 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2525 if (retval
!= ERROR_OK
)
2528 if (size
== 4 && (address
% 4) == 0) {
2529 /* We are doing a word-aligned transfer, so use fast mode. */
2530 retval
= cortex_a_read_apb_ab_memory_fast(target
, count
, buffer
, &dscr
);
2532 /* Use slow path. */
2533 retval
= cortex_a_read_apb_ab_memory_slow(target
, size
, count
, buffer
, &dscr
);
2537 final_retval
= retval
;
2539 /* Switch to non-blocking mode if not already in that mode. */
2540 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2541 if (final_retval
== ERROR_OK
)
2542 final_retval
= retval
;
2544 /* Wait for last issued instruction to complete. */
2545 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2546 if (final_retval
== ERROR_OK
)
2547 final_retval
= retval
;
2549 /* If there were any sticky abort flags, clear them. */
2550 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2552 mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
2553 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2554 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2559 /* Handle synchronous data faults. */
2560 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2561 if (final_retval
== ERROR_OK
) {
2562 /* Final return value will reflect cause of fault. */
2563 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2564 if (retval
== ERROR_OK
) {
2565 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2566 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2568 final_retval
= retval
;
2570 /* Fault destroyed DFAR/DFSR; restore them. */
2571 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2572 if (retval
!= ERROR_OK
)
2573 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2576 /* Handle asynchronous data faults. */
2577 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2578 if (final_retval
== ERROR_OK
)
2579 /* No other error has been recorded so far, so keep this one. */
2580 final_retval
= ERROR_TARGET_DATA_ABORT
;
2583 /* If the DCC is nonempty, clear it. */
2584 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2586 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2587 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2588 if (final_retval
== ERROR_OK
)
2589 final_retval
= retval
;
2591 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2592 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2593 if (final_retval
== ERROR_OK
)
2594 final_retval
= retval
;
2598 return final_retval
;
2603 * Cortex-A Memory access
2605 * This is same Cortex M3 but we must also use the correct
2606 * ap number for every access.
2609 static int cortex_a_read_phys_memory(struct target
*target
,
2610 uint32_t address
, uint32_t size
,
2611 uint32_t count
, uint8_t *buffer
)
2613 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2614 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2616 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2617 address
, size
, count
);
2619 if (count
&& buffer
) {
2620 /* read memory through APB-AP */
2621 if (!armv7a
->is_armv7r
) {
2623 retval
= cortex_a_mmu_modify(target
, 0);
2624 if (retval
!= ERROR_OK
)
2627 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2632 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2633 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2635 int mmu_enabled
= 0;
2637 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2639 /* cortex_a handles unaligned memory access */
2640 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2643 /* determine if MMU was enabled on target stop */
2644 if (!armv7a
->is_armv7r
) {
2645 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2646 if (retval
!= ERROR_OK
)
2651 retval
= cortex_a_check_address(target
, address
);
2652 if (retval
!= ERROR_OK
)
2654 /* enable MMU as we could have disabled it for phys access */
2655 retval
= cortex_a_mmu_modify(target
, 1);
2656 if (retval
!= ERROR_OK
)
2659 retval
= cortex_a_read_apb_ab_memory(target
, address
, size
, count
, buffer
);
2664 static int cortex_a_read_memory_ahb(struct target
*target
, uint32_t address
,
2665 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2667 int mmu_enabled
= 0;
2668 uint32_t virt
, phys
;
2670 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2671 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2672 uint8_t apsel
= swjdp
->apsel
;
2674 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
))
2675 return target_read_memory(target
, address
, size
, count
, buffer
);
2677 /* cortex_a handles unaligned memory access */
2678 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2681 /* determine if MMU was enabled on target stop */
2682 if (!armv7a
->is_armv7r
) {
2683 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2684 if (retval
!= ERROR_OK
)
2690 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2691 if (retval
!= ERROR_OK
)
2694 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2699 if (!count
|| !buffer
)
2700 return ERROR_COMMAND_SYNTAX_ERROR
;
2702 retval
= mem_ap_sel_read_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2707 static int cortex_a_write_phys_memory(struct target
*target
,
2708 uint32_t address
, uint32_t size
,
2709 uint32_t count
, const uint8_t *buffer
)
2711 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2712 int retval
= ERROR_COMMAND_SYNTAX_ERROR
;
2714 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2717 if (count
&& buffer
) {
2718 /* write memory through APB-AP */
2719 if (!armv7a
->is_armv7r
) {
2720 retval
= cortex_a_mmu_modify(target
, 0);
2721 if (retval
!= ERROR_OK
)
2724 return cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2730 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2731 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2733 int mmu_enabled
= 0;
2735 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2737 /* cortex_a handles unaligned memory access */
2738 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2741 /* determine if MMU was enabled on target stop */
2742 if (!armv7a
->is_armv7r
) {
2743 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2744 if (retval
!= ERROR_OK
)
2749 retval
= cortex_a_check_address(target
, address
);
2750 if (retval
!= ERROR_OK
)
2752 /* enable MMU as we could have disabled it for phys access */
2753 retval
= cortex_a_mmu_modify(target
, 1);
2754 if (retval
!= ERROR_OK
)
2757 retval
= cortex_a_write_apb_ab_memory(target
, address
, size
, count
, buffer
);
2759 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2764 static int cortex_a_write_memory_ahb(struct target
*target
, uint32_t address
,
2765 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2767 int mmu_enabled
= 0;
2768 uint32_t virt
, phys
;
2770 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2771 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2772 uint8_t apsel
= swjdp
->apsel
;
2774 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
))
2775 return target_write_memory(target
, address
, size
, count
, buffer
);
2777 /* cortex_a handles unaligned memory access */
2778 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2781 /* determine if MMU was enabled on target stop */
2782 if (!armv7a
->is_armv7r
) {
2783 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2784 if (retval
!= ERROR_OK
)
2790 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2791 if (retval
!= ERROR_OK
)
2794 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2800 if (!count
|| !buffer
)
2801 return ERROR_COMMAND_SYNTAX_ERROR
;
2803 retval
= mem_ap_sel_write_buf(swjdp
, armv7a
->memory_ap
, buffer
, size
, count
, address
);
2808 static int cortex_a_read_buffer(struct target
*target
, uint32_t address
,
2809 uint32_t count
, uint8_t *buffer
)
2813 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2814 * will have something to do with the size we leave to it. */
2815 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2816 if (address
& size
) {
2817 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2818 if (retval
!= ERROR_OK
)
2826 /* Read the data with as large access size as possible. */
2827 for (; size
> 0; size
/= 2) {
2828 uint32_t aligned
= count
- count
% size
;
2830 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2831 if (retval
!= ERROR_OK
)
2842 static int cortex_a_write_buffer(struct target
*target
, uint32_t address
,
2843 uint32_t count
, const uint8_t *buffer
)
2847 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2848 * will have something to do with the size we leave to it. */
2849 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2850 if (address
& size
) {
2851 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2852 if (retval
!= ERROR_OK
)
2860 /* Write the data with as large access size as possible. */
2861 for (; size
> 0; size
/= 2) {
2862 uint32_t aligned
= count
- count
% size
;
2864 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2865 if (retval
!= ERROR_OK
)
2876 static int cortex_a_handle_target_request(void *priv
)
2878 struct target
*target
= priv
;
2879 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2880 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2883 if (!target_was_examined(target
))
2885 if (!target
->dbg_msg_enabled
)
2888 if (target
->state
== TARGET_RUNNING
) {
2891 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2892 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2894 /* check if we have data */
2895 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2896 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2897 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2898 if (retval
== ERROR_OK
) {
2899 target_request(target
, request
);
2900 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2901 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2910 * Cortex-A target information and configuration
2913 static int cortex_a_examine_first(struct target
*target
)
2915 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2916 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2917 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2919 int retval
= ERROR_OK
;
2920 uint32_t didr
, ctypr
, ttypr
, cpuid
, dbg_osreg
;
2922 /* We do one extra read to ensure DAP is configured,
2923 * we call ahbap_debugport_init(swjdp) instead
2925 retval
= ahbap_debugport_init(swjdp
);
2926 if (retval
!= ERROR_OK
)
2929 /* Search for the APB-AB - it is needed for access to debug registers */
2930 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2931 if (retval
!= ERROR_OK
) {
2932 LOG_ERROR("Could not find APB-AP for debug access");
2935 /* Search for the AHB-AB */
2936 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2937 if (retval
!= ERROR_OK
) {
2938 /* AHB-AP not found - use APB-AP */
2939 LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
2940 armv7a
->memory_ap_available
= false;
2942 armv7a
->memory_ap_available
= true;
2946 if (!target
->dbgbase_set
) {
2948 /* Get ROM Table base */
2950 int32_t coreidx
= target
->coreid
;
2951 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2953 retval
= dap_get_debugbase(swjdp
, 1, &dbgbase
, &apid
);
2954 if (retval
!= ERROR_OK
)
2956 /* Lookup 0x15 -- Processor DAP */
2957 retval
= dap_lookup_cs_component(swjdp
, 1, dbgbase
, 0x15,
2958 &armv7a
->debug_base
, &coreidx
);
2959 if (retval
!= ERROR_OK
) {
2960 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2964 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2965 coreidx
, armv7a
->debug_base
);
2967 armv7a
->debug_base
= target
->dbgbase
;
2969 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2970 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2971 if (retval
!= ERROR_OK
)
2974 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2975 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2976 if (retval
!= ERROR_OK
) {
2977 LOG_DEBUG("Examine %s failed", "CPUID");
2981 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2982 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
);
2983 if (retval
!= ERROR_OK
) {
2984 LOG_DEBUG("Examine %s failed", "CTYPR");
2988 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2989 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
);
2990 if (retval
!= ERROR_OK
) {
2991 LOG_DEBUG("Examine %s failed", "TTYPR");
2995 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
2996 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2997 if (retval
!= ERROR_OK
) {
2998 LOG_DEBUG("Examine %s failed", "DIDR");
3002 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3003 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
3004 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
3005 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
3007 cortex_a
->cpuid
= cpuid
;
3008 cortex_a
->ctypr
= ctypr
;
3009 cortex_a
->ttypr
= ttypr
;
3010 cortex_a
->didr
= didr
;
3012 /* Unlocking the debug registers */
3013 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3014 CORTEX_A15_PARTNUM
) {
3016 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
3017 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3020 if (retval
!= ERROR_OK
)
3024 /* Unlocking the debug registers */
3025 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3026 CORTEX_A7_PARTNUM
) {
3028 retval
= mem_ap_sel_write_atomic_u32(swjdp
, armv7a
->debug_ap
,
3029 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3032 if (retval
!= ERROR_OK
)
3036 retval
= mem_ap_sel_read_atomic_u32(swjdp
, armv7a
->debug_ap
,
3037 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3039 if (retval
!= ERROR_OK
)
3042 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3044 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3046 /* Avoid recreating the registers cache */
3047 if (!target_was_examined(target
)) {
3048 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3049 if (retval
!= ERROR_OK
)
3053 /* Setup Breakpoint Register Pairs */
3054 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3055 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3056 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3057 free(cortex_a
->brp_list
);
3058 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3059 /* cortex_a->brb_enabled = ????; */
3060 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3061 cortex_a
->brp_list
[i
].used
= 0;
3062 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3063 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3065 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3066 cortex_a
->brp_list
[i
].value
= 0;
3067 cortex_a
->brp_list
[i
].control
= 0;
3068 cortex_a
->brp_list
[i
].BRPn
= i
;
3071 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3073 target_set_examined(target
);
3077 static int cortex_a_examine(struct target
*target
)
3079 int retval
= ERROR_OK
;
3081 /* Reestablish communication after target reset */
3082 retval
= cortex_a_examine_first(target
);
3084 /* Configure core debug access */
3085 if (retval
== ERROR_OK
)
3086 retval
= cortex_a_init_debug_access(target
);
3092 * Cortex-A target creation and initialization
3095 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3096 struct target
*target
)
3098 /* examine_first() does a bunch of this */
3102 static int cortex_a_init_arch_info(struct target
*target
,
3103 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3105 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3106 struct adiv5_dap
*dap
= &armv7a
->dap
;
3108 armv7a
->arm
.dap
= dap
;
3110 /* Setup struct cortex_a_common */
3111 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3112 /* tap has no dap initialized */
3114 armv7a
->arm
.dap
= dap
;
3115 /* Setup struct cortex_a_common */
3117 /* prepare JTAG information for the new target */
3118 cortex_a
->jtag_info
.tap
= tap
;
3119 cortex_a
->jtag_info
.scann_size
= 4;
3121 /* Leave (only) generic DAP stuff for debugport_init() */
3122 dap
->jtag_info
= &cortex_a
->jtag_info
;
3124 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
3125 dap
->tar_autoincr_block
= (1 << 10);
3126 dap
->memaccess_tck
= 80;
3129 armv7a
->arm
.dap
= tap
->dap
;
3131 cortex_a
->fast_reg_read
= 0;
3133 /* register arch-specific functions */
3134 armv7a
->examine_debug_reason
= NULL
;
3136 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3138 armv7a
->pre_restore_context
= NULL
;
3140 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3143 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3145 /* REVISIT v7a setup should be in a v7a-specific routine */
3146 armv7a_init_arch_info(target
, armv7a
);
3147 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3152 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3154 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3156 cortex_a
->armv7a_common
.is_armv7r
= false;
3158 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3161 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3163 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3165 cortex_a
->armv7a_common
.is_armv7r
= true;
3167 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3170 static void cortex_a_deinit_target(struct target
*target
)
3172 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3173 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3175 free(cortex_a
->brp_list
);
3181 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3183 if (target
->state
!= TARGET_HALTED
) {
3184 LOG_ERROR("%s: target not halted", __func__
);
3185 return ERROR_TARGET_INVALID
;
3188 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3192 static int cortex_a_virt2phys(struct target
*target
,
3193 uint32_t virt
, uint32_t *phys
)
3195 int retval
= ERROR_FAIL
;
3196 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3197 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3198 uint8_t apsel
= swjdp
->apsel
;
3199 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
)) {
3201 retval
= armv7a_mmu_translate_va(target
,
3203 if (retval
!= ERROR_OK
)
3206 } else {/* use this method if armv7a->memory_ap not selected
3207 * mmu must be enable in order to get a correct translation */
3208 retval
= cortex_a_mmu_modify(target
, 1);
3209 if (retval
!= ERROR_OK
)
3211 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
3217 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3219 struct target
*target
= get_current_target(CMD_CTX
);
3220 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3222 return armv7a_handle_cache_info_command(CMD_CTX
,
3223 &armv7a
->armv7a_mmu
.armv7a_cache
);
3227 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3229 struct target
*target
= get_current_target(CMD_CTX
);
3230 if (!target_was_examined(target
)) {
3231 LOG_ERROR("target not examined yet");
3235 return cortex_a_init_debug_access(target
);
3237 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3239 struct target
*target
= get_current_target(CMD_CTX
);
3240 /* check target is an smp target */
3241 struct target_list
*head
;
3242 struct target
*curr
;
3243 head
= target
->head
;
3245 if (head
!= (struct target_list
*)NULL
) {
3246 while (head
!= (struct target_list
*)NULL
) {
3247 curr
= head
->target
;
3251 /* fixes the target display to the debugger */
3252 target
->gdb_service
->target
= target
;
3257 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3259 struct target
*target
= get_current_target(CMD_CTX
);
3260 struct target_list
*head
;
3261 struct target
*curr
;
3262 head
= target
->head
;
3263 if (head
!= (struct target_list
*)NULL
) {
3265 while (head
!= (struct target_list
*)NULL
) {
3266 curr
= head
->target
;
3274 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3276 struct target
*target
= get_current_target(CMD_CTX
);
3277 int retval
= ERROR_OK
;
3278 struct target_list
*head
;
3279 head
= target
->head
;
3280 if (head
!= (struct target_list
*)NULL
) {
3281 if (CMD_ARGC
== 1) {
3283 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3284 if (ERROR_OK
!= retval
)
3286 target
->gdb_service
->core
[1] = coreid
;
3289 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3290 , target
->gdb_service
->core
[1]);
3295 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3297 struct target
*target
= get_current_target(CMD_CTX
);
3298 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3300 static const Jim_Nvp nvp_maskisr_modes
[] = {
3301 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3302 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3303 { .name
= NULL
, .value
= -1 },
3307 if (target
->state
!= TARGET_HALTED
) {
3308 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
3313 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3314 if (n
->name
== NULL
)
3315 return ERROR_COMMAND_SYNTAX_ERROR
;
3316 cortex_a
->isrmasking_mode
= n
->value
;
3320 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3321 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3326 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3328 .name
= "cache_info",
3329 .handler
= cortex_a_handle_cache_info_command
,
3330 .mode
= COMMAND_EXEC
,
3331 .help
= "display information about target caches",
3336 .handler
= cortex_a_handle_dbginit_command
,
3337 .mode
= COMMAND_EXEC
,
3338 .help
= "Initialize core debug",
3341 { .name
= "smp_off",
3342 .handler
= cortex_a_handle_smp_off_command
,
3343 .mode
= COMMAND_EXEC
,
3344 .help
= "Stop smp handling",
3348 .handler
= cortex_a_handle_smp_on_command
,
3349 .mode
= COMMAND_EXEC
,
3350 .help
= "Restart smp handling",
3355 .handler
= cortex_a_handle_smp_gdb_command
,
3356 .mode
= COMMAND_EXEC
,
3357 .help
= "display/fix current core played to gdb",
3362 .handler
= handle_cortex_a_mask_interrupts_command
,
3363 .mode
= COMMAND_EXEC
,
3364 .help
= "mask cortex_a interrupts",
3365 .usage
= "['on'|'off']",
3369 COMMAND_REGISTRATION_DONE
3371 static const struct command_registration cortex_a_command_handlers
[] = {
3373 .chain
= arm_command_handlers
,
3376 .chain
= armv7a_command_handlers
,
3380 .mode
= COMMAND_ANY
,
3381 .help
= "Cortex-A command group",
3383 .chain
= cortex_a_exec_command_handlers
,
3385 COMMAND_REGISTRATION_DONE
3388 struct target_type cortexa_target
= {
3390 .deprecated_name
= "cortex_a8",
3392 .poll
= cortex_a_poll
,
3393 .arch_state
= armv7a_arch_state
,
3395 .halt
= cortex_a_halt
,
3396 .resume
= cortex_a_resume
,
3397 .step
= cortex_a_step
,
3399 .assert_reset
= cortex_a_assert_reset
,
3400 .deassert_reset
= cortex_a_deassert_reset
,
3402 /* REVISIT allow exporting VFP3 registers ... */
3403 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3405 .read_memory
= cortex_a_read_memory
,
3406 .write_memory
= cortex_a_write_memory
,
3408 .read_buffer
= cortex_a_read_buffer
,
3409 .write_buffer
= cortex_a_write_buffer
,
3411 .checksum_memory
= arm_checksum_memory
,
3412 .blank_check_memory
= arm_blank_check_memory
,
3414 .run_algorithm
= armv4_5_run_algorithm
,
3416 .add_breakpoint
= cortex_a_add_breakpoint
,
3417 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3418 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3419 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3420 .add_watchpoint
= NULL
,
3421 .remove_watchpoint
= NULL
,
3423 .commands
= cortex_a_command_handlers
,
3424 .target_create
= cortex_a_target_create
,
3425 .init_target
= cortex_a_init_target
,
3426 .examine
= cortex_a_examine
,
3427 .deinit_target
= cortex_a_deinit_target
,
3429 .read_phys_memory
= cortex_a_read_phys_memory
,
3430 .write_phys_memory
= cortex_a_write_phys_memory
,
3431 .mmu
= cortex_a_mmu
,
3432 .virt2phys
= cortex_a_virt2phys
,
3435 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3437 .name
= "cache_info",
3438 .handler
= cortex_a_handle_cache_info_command
,
3439 .mode
= COMMAND_EXEC
,
3440 .help
= "display information about target caches",
3445 .handler
= cortex_a_handle_dbginit_command
,
3446 .mode
= COMMAND_EXEC
,
3447 .help
= "Initialize core debug",
3452 .handler
= handle_cortex_a_mask_interrupts_command
,
3453 .mode
= COMMAND_EXEC
,
3454 .help
= "mask cortex_r4 interrupts",
3455 .usage
= "['on'|'off']",
3458 COMMAND_REGISTRATION_DONE
3460 static const struct command_registration cortex_r4_command_handlers
[] = {
3462 .chain
= arm_command_handlers
,
3465 .chain
= armv7a_command_handlers
,
3468 .name
= "cortex_r4",
3469 .mode
= COMMAND_ANY
,
3470 .help
= "Cortex-R4 command group",
3472 .chain
= cortex_r4_exec_command_handlers
,
3474 COMMAND_REGISTRATION_DONE
3477 struct target_type cortexr4_target
= {
3478 .name
= "cortex_r4",
3480 .poll
= cortex_a_poll
,
3481 .arch_state
= armv7a_arch_state
,
3483 .halt
= cortex_a_halt
,
3484 .resume
= cortex_a_resume
,
3485 .step
= cortex_a_step
,
3487 .assert_reset
= cortex_a_assert_reset
,
3488 .deassert_reset
= cortex_a_deassert_reset
,
3490 /* REVISIT allow exporting VFP3 registers ... */
3491 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3493 .read_memory
= cortex_a_read_memory
,
3494 .write_memory
= cortex_a_write_memory
,
3496 .checksum_memory
= arm_checksum_memory
,
3497 .blank_check_memory
= arm_blank_check_memory
,
3499 .run_algorithm
= armv4_5_run_algorithm
,
3501 .add_breakpoint
= cortex_a_add_breakpoint
,
3502 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3503 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3504 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3505 .add_watchpoint
= NULL
,
3506 .remove_watchpoint
= NULL
,
3508 .commands
= cortex_r4_command_handlers
,
3509 .target_create
= cortex_r4_target_create
,
3510 .init_target
= cortex_a_init_target
,
3511 .examine
= cortex_a_examine
,
3512 .deinit_target
= cortex_a_deinit_target
,