1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
57 #include <helper/time_support.h>
59 static int cortex_a_poll(struct target
*target
);
60 static int cortex_a_debug_entry(struct target
*target
);
61 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
62 static int cortex_a_set_breakpoint(struct target
*target
,
63 struct breakpoint
*breakpoint
, uint8_t matchmode
);
64 static int cortex_a_set_context_breakpoint(struct target
*target
,
65 struct breakpoint
*breakpoint
, uint8_t matchmode
);
66 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
67 struct breakpoint
*breakpoint
);
68 static int cortex_a_unset_breakpoint(struct target
*target
,
69 struct breakpoint
*breakpoint
);
70 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
71 uint32_t *value
, int regnum
);
72 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
73 uint32_t value
, int regnum
);
74 static int cortex_a_mmu(struct target
*target
, int *enabled
);
75 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
76 static int cortex_a_virt2phys(struct target
*target
,
77 uint32_t virt
, uint32_t *phys
);
78 static int cortex_a_read_cpu_memory(struct target
*target
,
79 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
82 /* restore cp15_control_reg at resume */
83 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
85 int retval
= ERROR_OK
;
86 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
87 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
89 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
90 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
91 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
92 retval
= armv7a
->arm
.mcr(target
, 15,
95 cortex_a
->cp15_control_reg
);
101 * Set up ARM core for memory access.
102 * If !phys_access, switch to SVC mode and make sure MMU is on
103 * If phys_access, switch off mmu
105 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
107 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
108 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
111 if (phys_access
== 0) {
112 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
113 cortex_a_mmu(target
, &mmu_enabled
);
115 cortex_a_mmu_modify(target
, 1);
116 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
117 /* overwrite DACR to all-manager */
118 armv7a
->arm
.mcr(target
, 15,
123 cortex_a_mmu(target
, &mmu_enabled
);
125 cortex_a_mmu_modify(target
, 0);
131 * Restore ARM core after memory access.
132 * If !phys_access, switch to previous mode
133 * If phys_access, restore MMU setting
135 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
137 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
138 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
140 if (phys_access
== 0) {
141 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
143 armv7a
->arm
.mcr(target
, 15,
145 cortex_a
->cp15_dacr_reg
);
147 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
150 cortex_a_mmu(target
, &mmu_enabled
);
152 cortex_a_mmu_modify(target
, 1);
158 /* modify cp15_control_reg in order to enable or disable mmu for :
159 * - virt2phys address conversion
160 * - read or write memory in phys or virt address */
161 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
163 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
164 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
165 int retval
= ERROR_OK
;
169 /* if mmu enabled at target stop and mmu not enable */
170 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
171 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
174 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
175 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
179 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
180 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
186 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
187 enable
? "enable mmu" : "disable mmu",
188 cortex_a
->cp15_control_reg_curr
);
190 retval
= armv7a
->arm
.mcr(target
, 15,
193 cortex_a
->cp15_control_reg_curr
);
199 * Cortex-A Basic debug access, very low level assumes state is saved
201 static int cortex_a8_init_debug_access(struct target
*target
)
203 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
208 /* Unlocking the debug registers for modification
209 * The debugport might be uninitialised so try twice */
210 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
211 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
212 if (retval
!= ERROR_OK
) {
214 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
215 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0xC5ACCE55);
216 if (retval
== ERROR_OK
)
218 "Locking debug access failed on first, but succeeded on second try.");
225 * Cortex-A Basic debug access, very low level assumes state is saved
227 static int cortex_a_init_debug_access(struct target
*target
)
229 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
232 uint32_t cortex_part_num
;
233 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
236 cortex_part_num
= (cortex_a
->cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >>
237 CORTEX_A_MIDR_PARTNUM_SHIFT
;
239 switch (cortex_part_num
) {
240 case CORTEX_A7_PARTNUM
:
241 case CORTEX_A15_PARTNUM
:
242 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
243 armv7a
->debug_base
+ CPUDBG_OSLSR
,
245 if (retval
!= ERROR_OK
)
248 LOG_DEBUG("DBGOSLSR 0x%" PRIx32
, dbg_osreg
);
250 if (dbg_osreg
& CPUDBG_OSLAR_LK_MASK
)
251 /* Unlocking the DEBUG OS registers for modification */
252 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
253 armv7a
->debug_base
+ CPUDBG_OSLAR
,
257 case CORTEX_A5_PARTNUM
:
258 case CORTEX_A8_PARTNUM
:
259 case CORTEX_A9_PARTNUM
:
261 retval
= cortex_a8_init_debug_access(target
);
264 if (retval
!= ERROR_OK
)
266 /* Clear Sticky Power Down status Bit in PRSR to enable access to
267 the registers in the Core Power Domain */
268 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
269 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
270 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
272 if (retval
!= ERROR_OK
)
275 /* Disable cacheline fills and force cache write-through in debug state */
276 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
277 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
278 if (retval
!= ERROR_OK
)
281 /* Disable TLB lookup and refill/eviction in debug state */
282 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
283 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
284 if (retval
!= ERROR_OK
)
287 /* Enabling of instruction execution in debug mode is done in debug_entry code */
289 /* Resync breakpoint registers */
291 /* Since this is likely called from init or reset, update target state information*/
292 return cortex_a_poll(target
);
295 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
297 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
298 * Writes final value of DSCR into *dscr. Pass force to force always
299 * reading DSCR at least once. */
300 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
301 int64_t then
= timeval_ms();
302 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
304 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
305 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
306 if (retval
!= ERROR_OK
) {
307 LOG_ERROR("Could not read DSCR register");
310 if (timeval_ms() > then
+ 1000) {
311 LOG_ERROR("Timeout waiting for InstrCompl=1");
318 /* To reduce needless round-trips, pass in a pointer to the current
319 * DSCR value. Initialize it to zero if you just need to know the
320 * value on return from this function; or DSCR_INSTR_COMP if you
321 * happen to know that no instruction is pending.
323 static int cortex_a_exec_opcode(struct target
*target
,
324 uint32_t opcode
, uint32_t *dscr_p
)
328 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
330 dscr
= dscr_p
? *dscr_p
: 0;
332 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
334 /* Wait for InstrCompl bit to be set */
335 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
336 if (retval
!= ERROR_OK
)
339 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
340 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
341 if (retval
!= ERROR_OK
)
344 int64_t then
= timeval_ms();
346 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
347 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
348 if (retval
!= ERROR_OK
) {
349 LOG_ERROR("Could not read DSCR register");
352 if (timeval_ms() > then
+ 1000) {
353 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
356 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
364 /**************************************************************************
365 Read core register with very few exec_opcode, fast but needs work_area.
366 This can cause problems with MMU active.
367 **************************************************************************/
368 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
371 int retval
= ERROR_OK
;
372 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
374 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
375 if (retval
!= ERROR_OK
)
377 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
378 if (retval
!= ERROR_OK
)
380 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
381 if (retval
!= ERROR_OK
)
384 retval
= mem_ap_read_buf(armv7a
->memory_ap
,
385 (uint8_t *)(®file
[1]), 4, 15, address
);
390 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
391 uint32_t *value
, int regnum
)
393 int retval
= ERROR_OK
;
394 uint8_t reg
= regnum
&0xFF;
396 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
402 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
403 retval
= cortex_a_exec_opcode(target
,
404 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
406 if (retval
!= ERROR_OK
)
408 } else if (reg
== 15) {
409 /* "MOV r0, r15"; then move r0 to DCCTX */
410 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
411 if (retval
!= ERROR_OK
)
413 retval
= cortex_a_exec_opcode(target
,
414 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
416 if (retval
!= ERROR_OK
)
419 /* "MRS r0, CPSR" or "MRS r0, SPSR"
420 * then move r0 to DCCTX
422 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
423 if (retval
!= ERROR_OK
)
425 retval
= cortex_a_exec_opcode(target
,
426 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
428 if (retval
!= ERROR_OK
)
432 /* Wait for DTRRXfull then read DTRRTX */
433 int64_t then
= timeval_ms();
434 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
435 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
436 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
437 if (retval
!= ERROR_OK
)
439 if (timeval_ms() > then
+ 1000) {
440 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
445 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
446 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
447 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
452 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
453 uint32_t value
, int regnum
)
455 int retval
= ERROR_OK
;
456 uint8_t Rd
= regnum
&0xFF;
458 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
460 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
462 /* Check that DCCRX is not full */
463 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
464 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
465 if (retval
!= ERROR_OK
)
467 if (dscr
& DSCR_DTR_RX_FULL
) {
468 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
469 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
470 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
472 if (retval
!= ERROR_OK
)
479 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
480 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
481 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
482 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
483 if (retval
!= ERROR_OK
)
487 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
488 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
491 if (retval
!= ERROR_OK
)
493 } else if (Rd
== 15) {
494 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
497 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
499 if (retval
!= ERROR_OK
)
501 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
502 if (retval
!= ERROR_OK
)
505 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
506 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
508 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
510 if (retval
!= ERROR_OK
)
512 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
514 if (retval
!= ERROR_OK
)
517 /* "Prefetch flush" after modifying execution status in CPSR */
519 retval
= cortex_a_exec_opcode(target
,
520 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
522 if (retval
!= ERROR_OK
)
530 /* Write to memory mapped registers directly with no cache or mmu handling */
531 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
536 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
538 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
544 * Cortex-A implementation of Debug Programmer's Model
546 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
547 * so there's no need to poll for it before executing an instruction.
549 * NOTE that in several of these cases the "stall" mode might be useful.
550 * It'd let us queue a few operations together... prepare/finish might
551 * be the places to enable/disable that mode.
554 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
556 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
559 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
561 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
562 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
563 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
566 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
569 uint32_t dscr
= DSCR_INSTR_COMP
;
575 /* Wait for DTRRXfull */
576 int64_t then
= timeval_ms();
577 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
578 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
579 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
581 if (retval
!= ERROR_OK
)
583 if (timeval_ms() > then
+ 1000) {
584 LOG_ERROR("Timeout waiting for read dcc");
589 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
590 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
591 if (retval
!= ERROR_OK
)
593 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
601 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
603 struct cortex_a_common
*a
= dpm_to_a(dpm
);
607 /* set up invariant: INSTR_COMP is set after ever DPM operation */
608 int64_t then
= timeval_ms();
610 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
611 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
613 if (retval
!= ERROR_OK
)
615 if ((dscr
& DSCR_INSTR_COMP
) != 0)
617 if (timeval_ms() > then
+ 1000) {
618 LOG_ERROR("Timeout waiting for dpm prepare");
623 /* this "should never happen" ... */
624 if (dscr
& DSCR_DTR_RX_FULL
) {
625 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
627 retval
= cortex_a_exec_opcode(
628 a
->armv7a_common
.arm
.target
,
629 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
631 if (retval
!= ERROR_OK
)
638 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
640 /* REVISIT what could be done here? */
644 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
645 uint32_t opcode
, uint32_t data
)
647 struct cortex_a_common
*a
= dpm_to_a(dpm
);
649 uint32_t dscr
= DSCR_INSTR_COMP
;
651 retval
= cortex_a_write_dcc(a
, data
);
652 if (retval
!= ERROR_OK
)
655 return cortex_a_exec_opcode(
656 a
->armv7a_common
.arm
.target
,
661 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
662 uint32_t opcode
, uint32_t data
)
664 struct cortex_a_common
*a
= dpm_to_a(dpm
);
665 uint32_t dscr
= DSCR_INSTR_COMP
;
668 retval
= cortex_a_write_dcc(a
, data
);
669 if (retval
!= ERROR_OK
)
672 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
673 retval
= cortex_a_exec_opcode(
674 a
->armv7a_common
.arm
.target
,
675 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
677 if (retval
!= ERROR_OK
)
680 /* then the opcode, taking data from R0 */
681 retval
= cortex_a_exec_opcode(
682 a
->armv7a_common
.arm
.target
,
689 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
691 struct target
*target
= dpm
->arm
->target
;
692 uint32_t dscr
= DSCR_INSTR_COMP
;
694 /* "Prefetch flush" after modifying execution status in CPSR */
695 return cortex_a_exec_opcode(target
,
696 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
700 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
701 uint32_t opcode
, uint32_t *data
)
703 struct cortex_a_common
*a
= dpm_to_a(dpm
);
705 uint32_t dscr
= DSCR_INSTR_COMP
;
707 /* the opcode, writing data to DCC */
708 retval
= cortex_a_exec_opcode(
709 a
->armv7a_common
.arm
.target
,
712 if (retval
!= ERROR_OK
)
715 return cortex_a_read_dcc(a
, data
, &dscr
);
719 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
720 uint32_t opcode
, uint32_t *data
)
722 struct cortex_a_common
*a
= dpm_to_a(dpm
);
723 uint32_t dscr
= DSCR_INSTR_COMP
;
726 /* the opcode, writing data to R0 */
727 retval
= cortex_a_exec_opcode(
728 a
->armv7a_common
.arm
.target
,
731 if (retval
!= ERROR_OK
)
734 /* write R0 to DCC */
735 retval
= cortex_a_exec_opcode(
736 a
->armv7a_common
.arm
.target
,
737 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
739 if (retval
!= ERROR_OK
)
742 return cortex_a_read_dcc(a
, data
, &dscr
);
745 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
746 uint32_t addr
, uint32_t control
)
748 struct cortex_a_common
*a
= dpm_to_a(dpm
);
749 uint32_t vr
= a
->armv7a_common
.debug_base
;
750 uint32_t cr
= a
->armv7a_common
.debug_base
;
754 case 0 ... 15: /* breakpoints */
755 vr
+= CPUDBG_BVR_BASE
;
756 cr
+= CPUDBG_BCR_BASE
;
758 case 16 ... 31: /* watchpoints */
759 vr
+= CPUDBG_WVR_BASE
;
760 cr
+= CPUDBG_WCR_BASE
;
769 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
770 (unsigned) vr
, (unsigned) cr
);
772 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
774 if (retval
!= ERROR_OK
)
776 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
781 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
783 struct cortex_a_common
*a
= dpm_to_a(dpm
);
788 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
791 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
799 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
801 /* clear control register */
802 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
805 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
807 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
810 dpm
->arm
= &a
->armv7a_common
.arm
;
813 dpm
->prepare
= cortex_a_dpm_prepare
;
814 dpm
->finish
= cortex_a_dpm_finish
;
816 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
817 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
818 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
820 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
821 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
823 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
824 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
826 retval
= arm_dpm_setup(dpm
);
827 if (retval
== ERROR_OK
)
828 retval
= arm_dpm_initialize(dpm
);
832 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
834 struct target_list
*head
;
838 while (head
!= (struct target_list
*)NULL
) {
840 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
846 static int cortex_a_halt(struct target
*target
);
848 static int cortex_a_halt_smp(struct target
*target
)
851 struct target_list
*head
;
854 while (head
!= (struct target_list
*)NULL
) {
856 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
857 && target_was_examined(curr
))
858 retval
+= cortex_a_halt(curr
);
864 static int update_halt_gdb(struct target
*target
)
867 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
868 target
->gdb_service
->target
= target
;
869 target
->gdb_service
->core
[0] = target
->coreid
;
870 retval
+= cortex_a_halt_smp(target
);
876 * Cortex-A Run control
879 static int cortex_a_poll(struct target
*target
)
881 int retval
= ERROR_OK
;
883 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
884 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
885 enum target_state prev_target_state
= target
->state
;
886 /* toggle to another core is done by gdb as follow */
887 /* maint packet J core_id */
889 /* the next polling trigger an halt event sent to gdb */
890 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
891 (target
->gdb_service
) &&
892 (target
->gdb_service
->target
== NULL
)) {
893 target
->gdb_service
->target
=
894 get_cortex_a(target
, target
->gdb_service
->core
[1]);
895 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
898 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
899 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
900 if (retval
!= ERROR_OK
)
902 cortex_a
->cpudbg_dscr
= dscr
;
904 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
905 if (prev_target_state
!= TARGET_HALTED
) {
906 /* We have a halting debug event */
907 LOG_DEBUG("Target halted");
908 target
->state
= TARGET_HALTED
;
909 if ((prev_target_state
== TARGET_RUNNING
)
910 || (prev_target_state
== TARGET_UNKNOWN
)
911 || (prev_target_state
== TARGET_RESET
)) {
912 retval
= cortex_a_debug_entry(target
);
913 if (retval
!= ERROR_OK
)
916 retval
= update_halt_gdb(target
);
917 if (retval
!= ERROR_OK
)
921 if (arm_semihosting(target
, &retval
) != 0)
924 target_call_event_callbacks(target
,
925 TARGET_EVENT_HALTED
);
927 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
930 retval
= cortex_a_debug_entry(target
);
931 if (retval
!= ERROR_OK
)
934 retval
= update_halt_gdb(target
);
935 if (retval
!= ERROR_OK
)
939 target_call_event_callbacks(target
,
940 TARGET_EVENT_DEBUG_HALTED
);
943 } else if (DSCR_RUN_MODE(dscr
) == DSCR_CORE_RESTARTED
)
944 target
->state
= TARGET_RUNNING
;
946 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32
, dscr
);
947 target
->state
= TARGET_UNKNOWN
;
953 static int cortex_a_halt(struct target
*target
)
955 int retval
= ERROR_OK
;
957 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
960 * Tell the core to be halted by writing DRCR with 0x1
961 * and then wait for the core to be halted.
963 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
964 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
965 if (retval
!= ERROR_OK
)
969 * enter halting debug mode
971 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
972 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
973 if (retval
!= ERROR_OK
)
976 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
977 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
978 if (retval
!= ERROR_OK
)
981 int64_t then
= timeval_ms();
983 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
984 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
985 if (retval
!= ERROR_OK
)
987 if ((dscr
& DSCR_CORE_HALTED
) != 0)
989 if (timeval_ms() > then
+ 1000) {
990 LOG_ERROR("Timeout waiting for halt");
995 target
->debug_reason
= DBG_REASON_DBGRQ
;
1000 static int cortex_a_internal_restore(struct target
*target
, int current
,
1001 uint32_t *address
, int handle_breakpoints
, int debug_execution
)
1003 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1004 struct arm
*arm
= &armv7a
->arm
;
1008 if (!debug_execution
)
1009 target_free_all_working_areas(target
);
1012 if (debug_execution
) {
1013 /* Disable interrupts */
1014 /* We disable interrupts in the PRIMASK register instead of
1015 * masking with C_MASKINTS,
1016 * This is probably the same issue as Cortex-M3 Errata 377493:
1017 * C_MASKINTS in parallel with disabled interrupts can cause
1018 * local faults to not be taken. */
1019 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
1020 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
1021 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
1023 /* Make sure we are in Thumb mode */
1024 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
1025 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
1027 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
1028 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
1032 /* current = 1: continue on current pc, otherwise continue at <address> */
1033 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
1035 resume_pc
= *address
;
1037 *address
= resume_pc
;
1039 /* Make sure that the Armv7 gdb thumb fixups does not
1040 * kill the return address
1042 switch (arm
->core_state
) {
1044 resume_pc
&= 0xFFFFFFFC;
1046 case ARM_STATE_THUMB
:
1047 case ARM_STATE_THUMB_EE
:
1048 /* When the return address is loaded into PC
1049 * bit 0 must be 1 to stay in Thumb state
1053 case ARM_STATE_JAZELLE
:
1054 LOG_ERROR("How do I resume into Jazelle state??");
1057 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
1058 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1062 /* restore dpm_mode at system halt */
1063 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1064 /* called it now before restoring context because it uses cpu
1065 * register r0 for restoring cp15 control register */
1066 retval
= cortex_a_restore_cp15_control_reg(target
);
1067 if (retval
!= ERROR_OK
)
1069 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1070 if (retval
!= ERROR_OK
)
1072 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1073 target
->state
= TARGET_RUNNING
;
1075 /* registers are now invalid */
1076 register_cache_invalidate(arm
->core_cache
);
1079 /* the front-end may request us not to handle breakpoints */
1080 if (handle_breakpoints
) {
1081 /* Single step past breakpoint at current address */
1082 breakpoint
= breakpoint_find(target
, resume_pc
);
1084 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1085 cortex_m3_unset_breakpoint(target
, breakpoint
);
1086 cortex_m3_single_step_core(target
);
1087 cortex_m3_set_breakpoint(target
, breakpoint
);
1095 static int cortex_a_internal_restart(struct target
*target
)
1097 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1098 struct arm
*arm
= &armv7a
->arm
;
1102 * * Restart core and wait for it to be started. Clear ITRen and sticky
1103 * * exception flags: see ARMv7 ARM, C5.9.
1105 * REVISIT: for single stepping, we probably want to
1106 * disable IRQs by default, with optional override...
1109 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1110 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1111 if (retval
!= ERROR_OK
)
1114 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1115 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1117 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1118 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1119 if (retval
!= ERROR_OK
)
1122 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1123 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1124 DRCR_CLEAR_EXCEPTIONS
);
1125 if (retval
!= ERROR_OK
)
1128 int64_t then
= timeval_ms();
1130 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1131 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1132 if (retval
!= ERROR_OK
)
1134 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1136 if (timeval_ms() > then
+ 1000) {
1137 LOG_ERROR("Timeout waiting for resume");
1142 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1143 target
->state
= TARGET_RUNNING
;
1145 /* registers are now invalid */
1146 register_cache_invalidate(arm
->core_cache
);
1151 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1154 struct target_list
*head
;
1155 struct target
*curr
;
1157 head
= target
->head
;
1158 while (head
!= (struct target_list
*)NULL
) {
1159 curr
= head
->target
;
1160 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
1161 && target_was_examined(curr
)) {
1162 /* resume current address , not in step mode */
1163 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1164 handle_breakpoints
, 0);
1165 retval
+= cortex_a_internal_restart(curr
);
1173 static int cortex_a_resume(struct target
*target
, int current
,
1174 uint32_t address
, int handle_breakpoints
, int debug_execution
)
1177 /* dummy resume for smp toggle in order to reduce gdb impact */
1178 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1179 /* simulate a start and halt of target */
1180 target
->gdb_service
->target
= NULL
;
1181 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1182 /* fake resume at next poll we play the target core[1], see poll*/
1183 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1186 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1188 target
->gdb_service
->core
[0] = -1;
1189 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1190 if (retval
!= ERROR_OK
)
1193 cortex_a_internal_restart(target
);
1195 if (!debug_execution
) {
1196 target
->state
= TARGET_RUNNING
;
1197 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1198 LOG_DEBUG("target resumed at 0x%" PRIx32
, address
);
1200 target
->state
= TARGET_DEBUG_RUNNING
;
1201 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1202 LOG_DEBUG("target debug resumed at 0x%" PRIx32
, address
);
1208 static int cortex_a_debug_entry(struct target
*target
)
1211 uint32_t regfile
[16], cpsr
, spsr
, dscr
;
1212 int retval
= ERROR_OK
;
1213 struct working_area
*regfile_working_area
= NULL
;
1214 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1215 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1216 struct arm
*arm
= &armv7a
->arm
;
1219 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1221 /* REVISIT surely we should not re-read DSCR !! */
1222 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1223 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1224 if (retval
!= ERROR_OK
)
1227 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1228 * imprecise data aborts get discarded by issuing a Data
1229 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1232 /* Enable the ITR execution once we are in debug mode */
1233 dscr
|= DSCR_ITR_EN
;
1234 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1235 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1236 if (retval
!= ERROR_OK
)
1239 /* Examine debug reason */
1240 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1242 /* save address of instruction that triggered the watchpoint? */
1243 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1246 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1247 armv7a
->debug_base
+ CPUDBG_WFAR
,
1249 if (retval
!= ERROR_OK
)
1251 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1254 /* REVISIT fast_reg_read is never set ... */
1256 /* Examine target state and mode */
1257 if (cortex_a
->fast_reg_read
)
1258 target_alloc_working_area(target
, 64, ®file_working_area
);
1261 /* First load register acessible through core debug port*/
1262 if (!regfile_working_area
)
1263 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1265 retval
= cortex_a_read_regs_through_mem(target
,
1266 regfile_working_area
->address
, regfile
);
1268 target_free_working_area(target
, regfile_working_area
);
1269 if (retval
!= ERROR_OK
)
1272 /* read Current PSR */
1273 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1274 /* store current cpsr */
1275 if (retval
!= ERROR_OK
)
1278 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1280 arm_set_cpsr(arm
, cpsr
);
1283 for (i
= 0; i
<= ARM_PC
; i
++) {
1284 reg
= arm_reg_current(arm
, i
);
1286 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1291 /* Fixup PC Resume Address */
1292 if (cpsr
& (1 << 5)) {
1293 /* T bit set for Thumb or ThumbEE state */
1294 regfile
[ARM_PC
] -= 4;
1297 regfile
[ARM_PC
] -= 8;
1301 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1302 reg
->dirty
= reg
->valid
;
1305 /* read Saved PSR */
1306 retval
= cortex_a_dap_read_coreregister_u32(target
, &spsr
, 17);
1307 /* store current spsr */
1308 if (retval
!= ERROR_OK
)
1312 buf_set_u32(reg
->value
, 0, 32, spsr
);
1317 /* TODO, Move this */
1318 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1319 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1320 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1322 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1323 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1325 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1326 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1329 /* Are we in an exception handler */
1330 /* armv4_5->exception_number = 0; */
1331 if (armv7a
->post_debug_entry
) {
1332 retval
= armv7a
->post_debug_entry(target
);
1333 if (retval
!= ERROR_OK
)
1340 static int cortex_a_post_debug_entry(struct target
*target
)
1342 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1343 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1346 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1347 retval
= armv7a
->arm
.mrc(target
, 15,
1348 0, 0, /* op1, op2 */
1349 1, 0, /* CRn, CRm */
1350 &cortex_a
->cp15_control_reg
);
1351 if (retval
!= ERROR_OK
)
1353 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1354 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1356 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1357 armv7a_identify_cache(target
);
1359 if (armv7a
->is_armv7r
) {
1360 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1362 armv7a
->armv7a_mmu
.mmu_enabled
=
1363 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1365 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1366 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1367 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1368 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1369 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1371 /* switch to SVC mode to read DACR */
1372 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1373 armv7a
->arm
.mrc(target
, 15,
1375 &cortex_a
->cp15_dacr_reg
);
1377 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1378 cortex_a
->cp15_dacr_reg
);
1380 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1384 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1386 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1390 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1391 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1392 if (ERROR_OK
!= retval
)
1395 /* clear bitfield */
1398 dscr
|= value
& bit_mask
;
1400 /* write new DSCR */
1401 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1402 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1406 static int cortex_a_step(struct target
*target
, int current
, uint32_t address
,
1407 int handle_breakpoints
)
1409 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1410 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1411 struct arm
*arm
= &armv7a
->arm
;
1412 struct breakpoint
*breakpoint
= NULL
;
1413 struct breakpoint stepbreakpoint
;
1417 if (target
->state
!= TARGET_HALTED
) {
1418 LOG_WARNING("target not halted");
1419 return ERROR_TARGET_NOT_HALTED
;
1422 /* current = 1: continue on current pc, otherwise continue at <address> */
1425 buf_set_u32(r
->value
, 0, 32, address
);
1427 address
= buf_get_u32(r
->value
, 0, 32);
1429 /* The front-end may request us not to handle breakpoints.
1430 * But since Cortex-A uses breakpoint for single step,
1431 * we MUST handle breakpoints.
1433 handle_breakpoints
= 1;
1434 if (handle_breakpoints
) {
1435 breakpoint
= breakpoint_find(target
, address
);
1437 cortex_a_unset_breakpoint(target
, breakpoint
);
1440 /* Setup single step breakpoint */
1441 stepbreakpoint
.address
= address
;
1442 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1444 stepbreakpoint
.type
= BKPT_HARD
;
1445 stepbreakpoint
.set
= 0;
1447 /* Disable interrupts during single step if requested */
1448 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1449 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1450 if (ERROR_OK
!= retval
)
1454 /* Break on IVA mismatch */
1455 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1457 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1459 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1460 if (retval
!= ERROR_OK
)
1463 int64_t then
= timeval_ms();
1464 while (target
->state
!= TARGET_HALTED
) {
1465 retval
= cortex_a_poll(target
);
1466 if (retval
!= ERROR_OK
)
1468 if (timeval_ms() > then
+ 1000) {
1469 LOG_ERROR("timeout waiting for target halt");
1474 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1476 /* Re-enable interrupts if they were disabled */
1477 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1478 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1479 if (ERROR_OK
!= retval
)
1484 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1487 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1489 if (target
->state
!= TARGET_HALTED
)
1490 LOG_DEBUG("target stepped");
1495 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1497 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1501 if (armv7a
->pre_restore_context
)
1502 armv7a
->pre_restore_context(target
);
1504 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1508 * Cortex-A Breakpoint and watchpoint functions
1511 /* Setup hardware Breakpoint Register Pair */
1512 static int cortex_a_set_breakpoint(struct target
*target
,
1513 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1518 uint8_t byte_addr_select
= 0x0F;
1519 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1520 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1521 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1523 if (breakpoint
->set
) {
1524 LOG_WARNING("breakpoint already set");
1528 if (breakpoint
->type
== BKPT_HARD
) {
1529 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1531 if (brp_i
>= cortex_a
->brp_num
) {
1532 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1533 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1535 breakpoint
->set
= brp_i
+ 1;
1536 if (breakpoint
->length
== 2)
1537 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1538 control
= ((matchmode
& 0x7) << 20)
1539 | (byte_addr_select
<< 5)
1541 brp_list
[brp_i
].used
= 1;
1542 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1543 brp_list
[brp_i
].control
= control
;
1544 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1545 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1546 brp_list
[brp_i
].value
);
1547 if (retval
!= ERROR_OK
)
1549 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1550 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1551 brp_list
[brp_i
].control
);
1552 if (retval
!= ERROR_OK
)
1554 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1555 brp_list
[brp_i
].control
,
1556 brp_list
[brp_i
].value
);
1557 } else if (breakpoint
->type
== BKPT_SOFT
) {
1559 if (breakpoint
->length
== 2)
1560 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1562 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1563 retval
= target_read_memory(target
,
1564 breakpoint
->address
& 0xFFFFFFFE,
1565 breakpoint
->length
, 1,
1566 breakpoint
->orig_instr
);
1567 if (retval
!= ERROR_OK
)
1570 /* make sure data cache is cleaned & invalidated down to PoC */
1571 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1572 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1573 breakpoint
->length
);
1576 retval
= target_write_memory(target
,
1577 breakpoint
->address
& 0xFFFFFFFE,
1578 breakpoint
->length
, 1, code
);
1579 if (retval
!= ERROR_OK
)
1582 /* update i-cache at breakpoint location */
1583 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1584 breakpoint
->length
);
1585 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1586 breakpoint
->length
);
1588 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1594 static int cortex_a_set_context_breakpoint(struct target
*target
,
1595 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1597 int retval
= ERROR_FAIL
;
1600 uint8_t byte_addr_select
= 0x0F;
1601 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1602 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1603 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1605 if (breakpoint
->set
) {
1606 LOG_WARNING("breakpoint already set");
1609 /*check available context BRPs*/
1610 while ((brp_list
[brp_i
].used
||
1611 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1614 if (brp_i
>= cortex_a
->brp_num
) {
1615 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1619 breakpoint
->set
= brp_i
+ 1;
1620 control
= ((matchmode
& 0x7) << 20)
1621 | (byte_addr_select
<< 5)
1623 brp_list
[brp_i
].used
= 1;
1624 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1625 brp_list
[brp_i
].control
= control
;
1626 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1627 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1628 brp_list
[brp_i
].value
);
1629 if (retval
!= ERROR_OK
)
1631 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1632 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1633 brp_list
[brp_i
].control
);
1634 if (retval
!= ERROR_OK
)
1636 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1637 brp_list
[brp_i
].control
,
1638 brp_list
[brp_i
].value
);
1643 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1645 int retval
= ERROR_FAIL
;
1646 int brp_1
= 0; /* holds the contextID pair */
1647 int brp_2
= 0; /* holds the IVA pair */
1648 uint32_t control_CTX
, control_IVA
;
1649 uint8_t CTX_byte_addr_select
= 0x0F;
1650 uint8_t IVA_byte_addr_select
= 0x0F;
1651 uint8_t CTX_machmode
= 0x03;
1652 uint8_t IVA_machmode
= 0x01;
1653 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1654 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1655 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1657 if (breakpoint
->set
) {
1658 LOG_WARNING("breakpoint already set");
1661 /*check available context BRPs*/
1662 while ((brp_list
[brp_1
].used
||
1663 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1666 printf("brp(CTX) found num: %d\n", brp_1
);
1667 if (brp_1
>= cortex_a
->brp_num
) {
1668 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1672 while ((brp_list
[brp_2
].used
||
1673 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1676 printf("brp(IVA) found num: %d\n", brp_2
);
1677 if (brp_2
>= cortex_a
->brp_num
) {
1678 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1682 breakpoint
->set
= brp_1
+ 1;
1683 breakpoint
->linked_BRP
= brp_2
;
1684 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1687 | (CTX_byte_addr_select
<< 5)
1689 brp_list
[brp_1
].used
= 1;
1690 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1691 brp_list
[brp_1
].control
= control_CTX
;
1692 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1693 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1694 brp_list
[brp_1
].value
);
1695 if (retval
!= ERROR_OK
)
1697 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1698 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1699 brp_list
[brp_1
].control
);
1700 if (retval
!= ERROR_OK
)
1703 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1705 | (IVA_byte_addr_select
<< 5)
1707 brp_list
[brp_2
].used
= 1;
1708 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1709 brp_list
[brp_2
].control
= control_IVA
;
1710 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1711 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1712 brp_list
[brp_2
].value
);
1713 if (retval
!= ERROR_OK
)
1715 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1716 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1717 brp_list
[brp_2
].control
);
1718 if (retval
!= ERROR_OK
)
1724 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1727 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1728 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1729 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1731 if (!breakpoint
->set
) {
1732 LOG_WARNING("breakpoint not set");
1736 if (breakpoint
->type
== BKPT_HARD
) {
1737 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1738 int brp_i
= breakpoint
->set
- 1;
1739 int brp_j
= breakpoint
->linked_BRP
;
1740 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1741 LOG_DEBUG("Invalid BRP number in breakpoint");
1744 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1745 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1746 brp_list
[brp_i
].used
= 0;
1747 brp_list
[brp_i
].value
= 0;
1748 brp_list
[brp_i
].control
= 0;
1749 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1750 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1751 brp_list
[brp_i
].control
);
1752 if (retval
!= ERROR_OK
)
1754 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1755 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1756 brp_list
[brp_i
].value
);
1757 if (retval
!= ERROR_OK
)
1759 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1760 LOG_DEBUG("Invalid BRP number in breakpoint");
1763 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1764 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1765 brp_list
[brp_j
].used
= 0;
1766 brp_list
[brp_j
].value
= 0;
1767 brp_list
[brp_j
].control
= 0;
1768 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1769 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1770 brp_list
[brp_j
].control
);
1771 if (retval
!= ERROR_OK
)
1773 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1774 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1775 brp_list
[brp_j
].value
);
1776 if (retval
!= ERROR_OK
)
1778 breakpoint
->linked_BRP
= 0;
1779 breakpoint
->set
= 0;
1783 int brp_i
= breakpoint
->set
- 1;
1784 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1785 LOG_DEBUG("Invalid BRP number in breakpoint");
1788 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1789 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1790 brp_list
[brp_i
].used
= 0;
1791 brp_list
[brp_i
].value
= 0;
1792 brp_list
[brp_i
].control
= 0;
1793 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1794 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1795 brp_list
[brp_i
].control
);
1796 if (retval
!= ERROR_OK
)
1798 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1799 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1800 brp_list
[brp_i
].value
);
1801 if (retval
!= ERROR_OK
)
1803 breakpoint
->set
= 0;
1808 /* make sure data cache is cleaned & invalidated down to PoC */
1809 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1810 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1811 breakpoint
->length
);
1814 /* restore original instruction (kept in target endianness) */
1815 if (breakpoint
->length
== 4) {
1816 retval
= target_write_memory(target
,
1817 breakpoint
->address
& 0xFFFFFFFE,
1818 4, 1, breakpoint
->orig_instr
);
1819 if (retval
!= ERROR_OK
)
1822 retval
= target_write_memory(target
,
1823 breakpoint
->address
& 0xFFFFFFFE,
1824 2, 1, breakpoint
->orig_instr
);
1825 if (retval
!= ERROR_OK
)
1829 /* update i-cache at breakpoint location */
1830 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1831 breakpoint
->length
);
1832 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1833 breakpoint
->length
);
1835 breakpoint
->set
= 0;
1840 static int cortex_a_add_breakpoint(struct target
*target
,
1841 struct breakpoint
*breakpoint
)
1843 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1845 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1846 LOG_INFO("no hardware breakpoint available");
1847 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1850 if (breakpoint
->type
== BKPT_HARD
)
1851 cortex_a
->brp_num_available
--;
1853 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1856 static int cortex_a_add_context_breakpoint(struct target
*target
,
1857 struct breakpoint
*breakpoint
)
1859 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1861 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1862 LOG_INFO("no hardware breakpoint available");
1863 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1866 if (breakpoint
->type
== BKPT_HARD
)
1867 cortex_a
->brp_num_available
--;
1869 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1872 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1873 struct breakpoint
*breakpoint
)
1875 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1877 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1878 LOG_INFO("no hardware breakpoint available");
1879 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1882 if (breakpoint
->type
== BKPT_HARD
)
1883 cortex_a
->brp_num_available
--;
1885 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1889 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1891 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1894 /* It is perfectly possible to remove breakpoints while the target is running */
1895 if (target
->state
!= TARGET_HALTED
) {
1896 LOG_WARNING("target not halted");
1897 return ERROR_TARGET_NOT_HALTED
;
1901 if (breakpoint
->set
) {
1902 cortex_a_unset_breakpoint(target
, breakpoint
);
1903 if (breakpoint
->type
== BKPT_HARD
)
1904 cortex_a
->brp_num_available
++;
1912 * Cortex-A Reset functions
1915 static int cortex_a_assert_reset(struct target
*target
)
1917 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1921 /* FIXME when halt is requested, make it work somehow... */
1923 /* This function can be called in "target not examined" state */
1925 /* Issue some kind of warm reset. */
1926 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1927 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1928 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1929 /* REVISIT handle "pulls" cases, if there's
1930 * hardware that needs them to work.
1932 if (target
->reset_halt
)
1933 if (jtag_get_reset_config() & RESET_SRST_NO_GATING
)
1934 jtag_add_reset(0, 1);
1936 LOG_ERROR("%s: how to reset?", target_name(target
));
1940 /* registers are now invalid */
1941 if (target_was_examined(target
))
1942 register_cache_invalidate(armv7a
->arm
.core_cache
);
1944 target
->state
= TARGET_RESET
;
1949 static int cortex_a_deassert_reset(struct target
*target
)
1955 /* be certain SRST is off */
1956 jtag_add_reset(0, 0);
1958 if (target_was_examined(target
)) {
1959 retval
= cortex_a_poll(target
);
1960 if (retval
!= ERROR_OK
)
1964 if (target
->reset_halt
) {
1965 if (target
->state
!= TARGET_HALTED
) {
1966 LOG_WARNING("%s: ran after reset and before halt ...",
1967 target_name(target
));
1968 if (target_was_examined(target
)) {
1969 retval
= target_halt(target
);
1970 if (retval
!= ERROR_OK
)
1973 target
->state
= TARGET_UNKNOWN
;
1980 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1982 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1983 * New desired mode must be in mode. Current value of DSCR must be in
1984 * *dscr, which is updated with new value.
1986 * This function elides actually sending the mode-change over the debug
1987 * interface if the mode is already set as desired.
1989 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1990 if (new_dscr
!= *dscr
) {
1991 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1992 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1993 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1994 if (retval
== ERROR_OK
)
2002 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
2003 uint32_t value
, uint32_t *dscr
)
2005 /* Waits until the specified bit(s) of DSCR take on a specified value. */
2006 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2007 int64_t then
= timeval_ms();
2010 while ((*dscr
& mask
) != value
) {
2011 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2012 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
2013 if (retval
!= ERROR_OK
)
2015 if (timeval_ms() > then
+ 1000) {
2016 LOG_ERROR("timeout waiting for DSCR bit change");
2023 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
2024 uint32_t *data
, uint32_t *dscr
)
2027 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2029 /* Move from coprocessor to R0. */
2030 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2031 if (retval
!= ERROR_OK
)
2034 /* Move from R0 to DTRTX. */
2035 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
2036 if (retval
!= ERROR_OK
)
2039 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2040 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2041 * must also check TXfull_l). Most of the time this will be free
2042 * because TXfull_l will be set immediately and cached in dscr. */
2043 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2044 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2045 if (retval
!= ERROR_OK
)
2048 /* Read the value transferred to DTRTX. */
2049 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2050 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
2051 if (retval
!= ERROR_OK
)
2057 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
2058 uint32_t *dfsr
, uint32_t *dscr
)
2063 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2064 if (retval
!= ERROR_OK
)
2069 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2070 if (retval
!= ERROR_OK
)
2077 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2078 uint32_t data
, uint32_t *dscr
)
2081 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2083 /* Write the value into DTRRX. */
2084 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2085 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2086 if (retval
!= ERROR_OK
)
2089 /* Move from DTRRX to R0. */
2090 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2091 if (retval
!= ERROR_OK
)
2094 /* Move from R0 to coprocessor. */
2095 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2096 if (retval
!= ERROR_OK
)
2099 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2100 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2101 * check RXfull_l). Most of the time this will be free because RXfull_l
2102 * will be cleared immediately and cached in dscr. */
2103 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2104 if (retval
!= ERROR_OK
)
2110 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2111 uint32_t dfsr
, uint32_t *dscr
)
2115 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2116 if (retval
!= ERROR_OK
)
2119 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2120 if (retval
!= ERROR_OK
)
2126 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2128 uint32_t status
, upper4
;
2130 if (dfsr
& (1 << 9)) {
2132 status
= dfsr
& 0x3f;
2133 upper4
= status
>> 2;
2134 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2135 return ERROR_TARGET_TRANSLATION_FAULT
;
2136 else if (status
== 33)
2137 return ERROR_TARGET_UNALIGNED_ACCESS
;
2139 return ERROR_TARGET_DATA_ABORT
;
2141 /* Normal format. */
2142 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2144 return ERROR_TARGET_UNALIGNED_ACCESS
;
2145 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2146 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2147 return ERROR_TARGET_TRANSLATION_FAULT
;
2149 return ERROR_TARGET_DATA_ABORT
;
2153 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
2154 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2156 /* Writes count objects of size size from *buffer. Old value of DSCR must
2157 * be in *dscr; updated to new value. This is slow because it works for
2158 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2159 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2162 * - Address is in R0.
2163 * - R0 is marked dirty.
2165 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2166 struct arm
*arm
= &armv7a
->arm
;
2169 /* Mark register R1 as dirty, to use for transferring data. */
2170 arm_reg_current(arm
, 1)->dirty
= true;
2172 /* Switch to non-blocking mode if not already in that mode. */
2173 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2174 if (retval
!= ERROR_OK
)
2177 /* Go through the objects. */
2179 /* Write the value to store into DTRRX. */
2180 uint32_t data
, opcode
;
2184 data
= target_buffer_get_u16(target
, buffer
);
2186 data
= target_buffer_get_u32(target
, buffer
);
2187 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2188 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2189 if (retval
!= ERROR_OK
)
2192 /* Transfer the value from DTRRX to R1. */
2193 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2194 if (retval
!= ERROR_OK
)
2197 /* Write the value transferred to R1 into memory. */
2199 opcode
= ARMV4_5_STRB_IP(1, 0);
2201 opcode
= ARMV4_5_STRH_IP(1, 0);
2203 opcode
= ARMV4_5_STRW_IP(1, 0);
2204 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2205 if (retval
!= ERROR_OK
)
2208 /* Check for faults and return early. */
2209 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2210 return ERROR_OK
; /* A data fault is not considered a system failure. */
2212 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2213 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2214 * must also check RXfull_l). Most of the time this will be free
2215 * because RXfull_l will be cleared immediately and cached in dscr. */
2216 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2217 if (retval
!= ERROR_OK
)
2228 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
2229 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2231 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2232 * in *dscr; updated to new value. This is fast but only works for
2233 * word-sized objects at aligned addresses.
2235 * - Address is in R0 and must be a multiple of 4.
2236 * - R0 is marked dirty.
2238 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2241 /* Switch to fast mode if not already in that mode. */
2242 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2243 if (retval
!= ERROR_OK
)
2246 /* Latch STC instruction. */
2247 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2248 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2249 if (retval
!= ERROR_OK
)
2252 /* Transfer all the data and issue all the instructions. */
2253 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
2254 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2257 static int cortex_a_write_cpu_memory(struct target
*target
,
2258 uint32_t address
, uint32_t size
,
2259 uint32_t count
, const uint8_t *buffer
)
2261 /* Write memory through the CPU. */
2262 int retval
, final_retval
;
2263 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2264 struct arm
*arm
= &armv7a
->arm
;
2265 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2267 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2268 address
, size
, count
);
2269 if (target
->state
!= TARGET_HALTED
) {
2270 LOG_WARNING("target not halted");
2271 return ERROR_TARGET_NOT_HALTED
;
2277 /* Clear any abort. */
2278 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2279 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2280 if (retval
!= ERROR_OK
)
2284 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2285 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2286 if (retval
!= ERROR_OK
)
2289 /* Switch to non-blocking mode if not already in that mode. */
2290 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2291 if (retval
!= ERROR_OK
)
2294 /* Mark R0 as dirty. */
2295 arm_reg_current(arm
, 0)->dirty
= true;
2297 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2298 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2299 if (retval
!= ERROR_OK
)
2302 /* Get the memory address into R0. */
2303 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2304 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2305 if (retval
!= ERROR_OK
)
2307 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2308 if (retval
!= ERROR_OK
)
2311 if (size
== 4 && (address
% 4) == 0) {
2312 /* We are doing a word-aligned transfer, so use fast mode. */
2313 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2315 /* Use slow path. */
2316 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2320 final_retval
= retval
;
2322 /* Switch to non-blocking mode if not already in that mode. */
2323 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2324 if (final_retval
== ERROR_OK
)
2325 final_retval
= retval
;
2327 /* Wait for last issued instruction to complete. */
2328 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2329 if (final_retval
== ERROR_OK
)
2330 final_retval
= retval
;
2332 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2333 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2334 * check RXfull_l). Most of the time this will be free because RXfull_l
2335 * will be cleared immediately and cached in dscr. However, don't do this
2336 * if there is fault, because then the instruction might not have completed
2338 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2339 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2340 if (retval
!= ERROR_OK
)
2344 /* If there were any sticky abort flags, clear them. */
2345 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2347 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2348 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2349 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2354 /* Handle synchronous data faults. */
2355 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2356 if (final_retval
== ERROR_OK
) {
2357 /* Final return value will reflect cause of fault. */
2358 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2359 if (retval
== ERROR_OK
) {
2360 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2361 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2363 final_retval
= retval
;
2365 /* Fault destroyed DFAR/DFSR; restore them. */
2366 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2367 if (retval
!= ERROR_OK
)
2368 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2371 /* Handle asynchronous data faults. */
2372 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2373 if (final_retval
== ERROR_OK
)
2374 /* No other error has been recorded so far, so keep this one. */
2375 final_retval
= ERROR_TARGET_DATA_ABORT
;
2378 /* If the DCC is nonempty, clear it. */
2379 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2381 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2382 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2383 if (final_retval
== ERROR_OK
)
2384 final_retval
= retval
;
2386 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2387 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2388 if (final_retval
== ERROR_OK
)
2389 final_retval
= retval
;
2393 return final_retval
;
2396 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2397 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2399 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2400 * in *dscr; updated to new value. This is slow because it works for
2401 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2402 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2405 * - Address is in R0.
2406 * - R0 is marked dirty.
2408 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2409 struct arm
*arm
= &armv7a
->arm
;
2412 /* Mark register R1 as dirty, to use for transferring data. */
2413 arm_reg_current(arm
, 1)->dirty
= true;
2415 /* Switch to non-blocking mode if not already in that mode. */
2416 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2417 if (retval
!= ERROR_OK
)
2420 /* Go through the objects. */
2422 /* Issue a load of the appropriate size to R1. */
2423 uint32_t opcode
, data
;
2425 opcode
= ARMV4_5_LDRB_IP(1, 0);
2427 opcode
= ARMV4_5_LDRH_IP(1, 0);
2429 opcode
= ARMV4_5_LDRW_IP(1, 0);
2430 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2431 if (retval
!= ERROR_OK
)
2434 /* Issue a write of R1 to DTRTX. */
2435 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2436 if (retval
!= ERROR_OK
)
2439 /* Check for faults and return early. */
2440 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2441 return ERROR_OK
; /* A data fault is not considered a system failure. */
2443 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2444 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2445 * must also check TXfull_l). Most of the time this will be free
2446 * because TXfull_l will be set immediately and cached in dscr. */
2447 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2448 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2449 if (retval
!= ERROR_OK
)
2452 /* Read the value transferred to DTRTX into the buffer. */
2453 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2454 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2455 if (retval
!= ERROR_OK
)
2458 *buffer
= (uint8_t) data
;
2460 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2462 target_buffer_set_u32(target
, buffer
, data
);
2472 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2473 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2475 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2476 * *dscr; updated to new value. This is fast but only works for word-sized
2477 * objects at aligned addresses.
2479 * - Address is in R0 and must be a multiple of 4.
2480 * - R0 is marked dirty.
2482 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2486 /* Switch to non-blocking mode if not already in that mode. */
2487 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2488 if (retval
!= ERROR_OK
)
2491 /* Issue the LDC instruction via a write to ITR. */
2492 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2493 if (retval
!= ERROR_OK
)
2499 /* Switch to fast mode if not already in that mode. */
2500 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2501 if (retval
!= ERROR_OK
)
2504 /* Latch LDC instruction. */
2505 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2506 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2507 if (retval
!= ERROR_OK
)
2510 /* Read the value transferred to DTRTX into the buffer. Due to fast
2511 * mode rules, this blocks until the instruction finishes executing and
2512 * then reissues the read instruction to read the next word from
2513 * memory. The last read of DTRTX in this call reads the second-to-last
2514 * word from memory and issues the read instruction for the last word.
2516 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2517 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2518 if (retval
!= ERROR_OK
)
2522 buffer
+= count
* 4;
2525 /* Wait for last issued instruction to complete. */
2526 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2527 if (retval
!= ERROR_OK
)
2530 /* Switch to non-blocking mode if not already in that mode. */
2531 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2532 if (retval
!= ERROR_OK
)
2535 /* Check for faults and return early. */
2536 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2537 return ERROR_OK
; /* A data fault is not considered a system failure. */
2539 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2540 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2541 * check TXfull_l). Most of the time this will be free because TXfull_l
2542 * will be set immediately and cached in dscr. */
2543 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2544 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2545 if (retval
!= ERROR_OK
)
2548 /* Read the value transferred to DTRTX into the buffer. This is the last
2550 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2551 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2552 if (retval
!= ERROR_OK
)
2554 target_buffer_set_u32(target
, buffer
, u32
);
2559 static int cortex_a_read_cpu_memory(struct target
*target
,
2560 uint32_t address
, uint32_t size
,
2561 uint32_t count
, uint8_t *buffer
)
2563 /* Read memory through the CPU. */
2564 int retval
, final_retval
;
2565 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2566 struct arm
*arm
= &armv7a
->arm
;
2567 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2569 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2570 address
, size
, count
);
2571 if (target
->state
!= TARGET_HALTED
) {
2572 LOG_WARNING("target not halted");
2573 return ERROR_TARGET_NOT_HALTED
;
2579 /* Clear any abort. */
2580 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2581 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2582 if (retval
!= ERROR_OK
)
2586 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2587 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2588 if (retval
!= ERROR_OK
)
2591 /* Switch to non-blocking mode if not already in that mode. */
2592 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2593 if (retval
!= ERROR_OK
)
2596 /* Mark R0 as dirty. */
2597 arm_reg_current(arm
, 0)->dirty
= true;
2599 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2600 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2601 if (retval
!= ERROR_OK
)
2604 /* Get the memory address into R0. */
2605 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2606 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2607 if (retval
!= ERROR_OK
)
2609 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2610 if (retval
!= ERROR_OK
)
2613 if (size
== 4 && (address
% 4) == 0) {
2614 /* We are doing a word-aligned transfer, so use fast mode. */
2615 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2617 /* Use slow path. */
2618 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2622 final_retval
= retval
;
2624 /* Switch to non-blocking mode if not already in that mode. */
2625 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2626 if (final_retval
== ERROR_OK
)
2627 final_retval
= retval
;
2629 /* Wait for last issued instruction to complete. */
2630 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2631 if (final_retval
== ERROR_OK
)
2632 final_retval
= retval
;
2634 /* If there were any sticky abort flags, clear them. */
2635 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2637 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2638 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2639 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2644 /* Handle synchronous data faults. */
2645 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2646 if (final_retval
== ERROR_OK
) {
2647 /* Final return value will reflect cause of fault. */
2648 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2649 if (retval
== ERROR_OK
) {
2650 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2651 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2653 final_retval
= retval
;
2655 /* Fault destroyed DFAR/DFSR; restore them. */
2656 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2657 if (retval
!= ERROR_OK
)
2658 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2661 /* Handle asynchronous data faults. */
2662 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2663 if (final_retval
== ERROR_OK
)
2664 /* No other error has been recorded so far, so keep this one. */
2665 final_retval
= ERROR_TARGET_DATA_ABORT
;
2668 /* If the DCC is nonempty, clear it. */
2669 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2671 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2672 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2673 if (final_retval
== ERROR_OK
)
2674 final_retval
= retval
;
2676 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2677 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2678 if (final_retval
== ERROR_OK
)
2679 final_retval
= retval
;
2683 return final_retval
;
2688 * Cortex-A Memory access
2690 * This is same Cortex-M3 but we must also use the correct
2691 * ap number for every access.
2694 static int cortex_a_read_phys_memory(struct target
*target
,
2695 uint32_t address
, uint32_t size
,
2696 uint32_t count
, uint8_t *buffer
)
2698 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2699 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2700 uint8_t apsel
= swjdp
->apsel
;
2703 if (!count
|| !buffer
)
2704 return ERROR_COMMAND_SYNTAX_ERROR
;
2706 LOG_DEBUG("Reading memory at real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
,
2707 address
, size
, count
);
2709 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2710 return mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2712 /* read memory through the CPU */
2713 cortex_a_prep_memaccess(target
, 1);
2714 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2715 cortex_a_post_memaccess(target
, 1);
2720 static int cortex_a_read_memory(struct target
*target
, uint32_t address
,
2721 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2725 /* cortex_a handles unaligned memory access */
2726 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2729 cortex_a_prep_memaccess(target
, 0);
2730 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2731 cortex_a_post_memaccess(target
, 0);
2736 static int cortex_a_read_memory_ahb(struct target
*target
, uint32_t address
,
2737 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2739 int mmu_enabled
= 0;
2740 uint32_t virt
, phys
;
2742 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2743 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2744 uint8_t apsel
= swjdp
->apsel
;
2746 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2747 return target_read_memory(target
, address
, size
, count
, buffer
);
2749 /* cortex_a handles unaligned memory access */
2750 LOG_DEBUG("Reading memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2753 /* determine if MMU was enabled on target stop */
2754 if (!armv7a
->is_armv7r
) {
2755 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2756 if (retval
!= ERROR_OK
)
2762 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2763 if (retval
!= ERROR_OK
)
2766 LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2771 if (!count
|| !buffer
)
2772 return ERROR_COMMAND_SYNTAX_ERROR
;
2774 retval
= mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2779 static int cortex_a_write_phys_memory(struct target
*target
,
2780 uint32_t address
, uint32_t size
,
2781 uint32_t count
, const uint8_t *buffer
)
2783 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2784 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2785 uint8_t apsel
= swjdp
->apsel
;
2788 if (!count
|| !buffer
)
2789 return ERROR_COMMAND_SYNTAX_ERROR
;
2791 LOG_DEBUG("Writing memory to real address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2794 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2795 return mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2797 /* write memory through the CPU */
2798 cortex_a_prep_memaccess(target
, 1);
2799 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2800 cortex_a_post_memaccess(target
, 1);
2805 static int cortex_a_write_memory(struct target
*target
, uint32_t address
,
2806 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2810 /* cortex_a handles unaligned memory access */
2811 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2814 /* memory writes bypass the caches, must flush before writing */
2815 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2817 cortex_a_prep_memaccess(target
, 0);
2818 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2819 cortex_a_post_memaccess(target
, 0);
2823 static int cortex_a_write_memory_ahb(struct target
*target
, uint32_t address
,
2824 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2826 int mmu_enabled
= 0;
2827 uint32_t virt
, phys
;
2829 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2830 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2831 uint8_t apsel
= swjdp
->apsel
;
2833 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2834 return target_write_memory(target
, address
, size
, count
, buffer
);
2836 /* cortex_a handles unaligned memory access */
2837 LOG_DEBUG("Writing memory at address 0x%" PRIx32
"; size %" PRId32
"; count %" PRId32
, address
,
2840 /* determine if MMU was enabled on target stop */
2841 if (!armv7a
->is_armv7r
) {
2842 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2843 if (retval
!= ERROR_OK
)
2849 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2850 if (retval
!= ERROR_OK
)
2853 LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32
" to r:0x%" PRIx32
,
2859 if (!count
|| !buffer
)
2860 return ERROR_COMMAND_SYNTAX_ERROR
;
2862 retval
= mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2867 static int cortex_a_read_buffer(struct target
*target
, uint32_t address
,
2868 uint32_t count
, uint8_t *buffer
)
2872 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2873 * will have something to do with the size we leave to it. */
2874 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2875 if (address
& size
) {
2876 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2877 if (retval
!= ERROR_OK
)
2885 /* Read the data with as large access size as possible. */
2886 for (; size
> 0; size
/= 2) {
2887 uint32_t aligned
= count
- count
% size
;
2889 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2890 if (retval
!= ERROR_OK
)
2901 static int cortex_a_write_buffer(struct target
*target
, uint32_t address
,
2902 uint32_t count
, const uint8_t *buffer
)
2906 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2907 * will have something to do with the size we leave to it. */
2908 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2909 if (address
& size
) {
2910 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2911 if (retval
!= ERROR_OK
)
2919 /* Write the data with as large access size as possible. */
2920 for (; size
> 0; size
/= 2) {
2921 uint32_t aligned
= count
- count
% size
;
2923 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2924 if (retval
!= ERROR_OK
)
2935 static int cortex_a_handle_target_request(void *priv
)
2937 struct target
*target
= priv
;
2938 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2941 if (!target_was_examined(target
))
2943 if (!target
->dbg_msg_enabled
)
2946 if (target
->state
== TARGET_RUNNING
) {
2949 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2950 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2952 /* check if we have data */
2953 int64_t then
= timeval_ms();
2954 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2955 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2956 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2957 if (retval
== ERROR_OK
) {
2958 target_request(target
, request
);
2959 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2960 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2962 if (timeval_ms() > then
+ 1000) {
2963 LOG_ERROR("Timeout waiting for dtr tx full");
2973 * Cortex-A target information and configuration
2976 static int cortex_a_examine_first(struct target
*target
)
2978 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2979 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2980 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2983 int retval
= ERROR_OK
;
2984 uint32_t didr
, ctypr
, ttypr
, cpuid
, dbg_osreg
;
2986 retval
= dap_dp_init(swjdp
);
2987 if (retval
!= ERROR_OK
) {
2988 LOG_ERROR("Could not initialize the debug port");
2992 /* Search for the APB-AP - it is needed for access to debug registers */
2993 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2994 if (retval
!= ERROR_OK
) {
2995 LOG_ERROR("Could not find APB-AP for debug access");
2999 retval
= mem_ap_init(armv7a
->debug_ap
);
3000 if (retval
!= ERROR_OK
) {
3001 LOG_ERROR("Could not initialize the APB-AP");
3005 armv7a
->debug_ap
->memaccess_tck
= 80;
3007 /* Search for the AHB-AB.
3008 * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
3009 * can access system memory. */
3010 armv7a
->memory_ap_available
= false;
3011 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
3012 if (retval
== ERROR_OK
) {
3013 retval
= mem_ap_init(armv7a
->memory_ap
);
3014 if (retval
== ERROR_OK
)
3015 armv7a
->memory_ap_available
= true;
3017 if (retval
!= ERROR_OK
) {
3018 /* AHB-AP not found or unavailable - use the CPU */
3019 LOG_DEBUG("No AHB-AP available for memory access");
3022 if (!target
->dbgbase_set
) {
3024 /* Get ROM Table base */
3026 int32_t coreidx
= target
->coreid
;
3027 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
3029 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
3030 if (retval
!= ERROR_OK
)
3032 /* Lookup 0x15 -- Processor DAP */
3033 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
3034 &armv7a
->debug_base
, &coreidx
);
3035 if (retval
!= ERROR_OK
) {
3036 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
3040 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
3041 target
->coreid
, armv7a
->debug_base
);
3043 armv7a
->debug_base
= target
->dbgbase
;
3045 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3046 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
3047 if (retval
!= ERROR_OK
)
3050 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3051 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
3052 if (retval
!= ERROR_OK
) {
3053 LOG_DEBUG("Examine %s failed", "CPUID");
3057 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3058 armv7a
->debug_base
+ CPUDBG_CTYPR
, &ctypr
);
3059 if (retval
!= ERROR_OK
) {
3060 LOG_DEBUG("Examine %s failed", "CTYPR");
3064 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3065 armv7a
->debug_base
+ CPUDBG_TTYPR
, &ttypr
);
3066 if (retval
!= ERROR_OK
) {
3067 LOG_DEBUG("Examine %s failed", "TTYPR");
3071 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3072 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
3073 if (retval
!= ERROR_OK
) {
3074 LOG_DEBUG("Examine %s failed", "DIDR");
3078 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3079 LOG_DEBUG("ctypr = 0x%08" PRIx32
, ctypr
);
3080 LOG_DEBUG("ttypr = 0x%08" PRIx32
, ttypr
);
3081 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
3083 cortex_a
->cpuid
= cpuid
;
3084 cortex_a
->ctypr
= ctypr
;
3085 cortex_a
->ttypr
= ttypr
;
3086 cortex_a
->didr
= didr
;
3088 /* Unlocking the debug registers */
3089 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3090 CORTEX_A15_PARTNUM
) {
3092 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
3093 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3096 if (retval
!= ERROR_OK
)
3100 /* Unlocking the debug registers */
3101 if ((cpuid
& CORTEX_A_MIDR_PARTNUM_MASK
) >> CORTEX_A_MIDR_PARTNUM_SHIFT
==
3102 CORTEX_A7_PARTNUM
) {
3104 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
3105 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3108 if (retval
!= ERROR_OK
)
3112 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3113 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3115 if (retval
!= ERROR_OK
)
3118 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3120 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3122 /* Avoid recreating the registers cache */
3123 if (!target_was_examined(target
)) {
3124 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3125 if (retval
!= ERROR_OK
)
3129 /* Setup Breakpoint Register Pairs */
3130 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3131 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3132 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3133 free(cortex_a
->brp_list
);
3134 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3135 /* cortex_a->brb_enabled = ????; */
3136 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3137 cortex_a
->brp_list
[i
].used
= 0;
3138 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3139 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3141 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3142 cortex_a
->brp_list
[i
].value
= 0;
3143 cortex_a
->brp_list
[i
].control
= 0;
3144 cortex_a
->brp_list
[i
].BRPn
= i
;
3147 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3149 /* select debug_ap as default */
3150 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
3152 target_set_examined(target
);
3156 static int cortex_a_examine(struct target
*target
)
3158 int retval
= ERROR_OK
;
3160 /* Reestablish communication after target reset */
3161 retval
= cortex_a_examine_first(target
);
3163 /* Configure core debug access */
3164 if (retval
== ERROR_OK
)
3165 retval
= cortex_a_init_debug_access(target
);
3171 * Cortex-A target creation and initialization
3174 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3175 struct target
*target
)
3177 /* examine_first() does a bunch of this */
3181 static int cortex_a_init_arch_info(struct target
*target
,
3182 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3184 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3186 /* Setup struct cortex_a_common */
3187 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3189 /* tap has no dap initialized */
3191 tap
->dap
= dap_init();
3193 /* Leave (only) generic DAP stuff for debugport_init() */
3194 tap
->dap
->tap
= tap
;
3197 armv7a
->arm
.dap
= tap
->dap
;
3199 cortex_a
->fast_reg_read
= 0;
3201 /* register arch-specific functions */
3202 armv7a
->examine_debug_reason
= NULL
;
3204 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3206 armv7a
->pre_restore_context
= NULL
;
3208 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3211 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3213 /* REVISIT v7a setup should be in a v7a-specific routine */
3214 armv7a_init_arch_info(target
, armv7a
);
3215 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3220 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3222 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3224 cortex_a
->armv7a_common
.is_armv7r
= false;
3226 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3229 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3231 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3233 cortex_a
->armv7a_common
.is_armv7r
= true;
3235 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3238 static void cortex_a_deinit_target(struct target
*target
)
3240 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3241 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3243 free(cortex_a
->brp_list
);
3249 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3251 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3253 if (target
->state
!= TARGET_HALTED
) {
3254 LOG_ERROR("%s: target not halted", __func__
);
3255 return ERROR_TARGET_INVALID
;
3258 if (armv7a
->is_armv7r
)
3261 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3266 static int cortex_a_virt2phys(struct target
*target
,
3267 uint32_t virt
, uint32_t *phys
)
3269 int retval
= ERROR_FAIL
;
3270 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3271 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3272 uint8_t apsel
= swjdp
->apsel
;
3273 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
)) {
3275 retval
= armv7a_mmu_translate_va(target
,
3277 if (retval
!= ERROR_OK
)
3280 } else {/* use this method if armv7a->memory_ap not selected
3281 * mmu must be enable in order to get a correct translation */
3282 retval
= cortex_a_mmu_modify(target
, 1);
3283 if (retval
!= ERROR_OK
)
3285 retval
= armv7a_mmu_translate_va_pa(target
, virt
, phys
, 1);
3291 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3293 struct target
*target
= get_current_target(CMD_CTX
);
3294 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3296 return armv7a_handle_cache_info_command(CMD_CTX
,
3297 &armv7a
->armv7a_mmu
.armv7a_cache
);
3301 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3303 struct target
*target
= get_current_target(CMD_CTX
);
3304 if (!target_was_examined(target
)) {
3305 LOG_ERROR("target not examined yet");
3309 return cortex_a_init_debug_access(target
);
3311 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3313 struct target
*target
= get_current_target(CMD_CTX
);
3314 /* check target is an smp target */
3315 struct target_list
*head
;
3316 struct target
*curr
;
3317 head
= target
->head
;
3319 if (head
!= (struct target_list
*)NULL
) {
3320 while (head
!= (struct target_list
*)NULL
) {
3321 curr
= head
->target
;
3325 /* fixes the target display to the debugger */
3326 target
->gdb_service
->target
= target
;
3331 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3333 struct target
*target
= get_current_target(CMD_CTX
);
3334 struct target_list
*head
;
3335 struct target
*curr
;
3336 head
= target
->head
;
3337 if (head
!= (struct target_list
*)NULL
) {
3339 while (head
!= (struct target_list
*)NULL
) {
3340 curr
= head
->target
;
3348 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3350 struct target
*target
= get_current_target(CMD_CTX
);
3351 int retval
= ERROR_OK
;
3352 struct target_list
*head
;
3353 head
= target
->head
;
3354 if (head
!= (struct target_list
*)NULL
) {
3355 if (CMD_ARGC
== 1) {
3357 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3358 if (ERROR_OK
!= retval
)
3360 target
->gdb_service
->core
[1] = coreid
;
3363 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3364 , target
->gdb_service
->core
[1]);
3369 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3371 struct target
*target
= get_current_target(CMD_CTX
);
3372 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3374 static const Jim_Nvp nvp_maskisr_modes
[] = {
3375 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3376 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3377 { .name
= NULL
, .value
= -1 },
3382 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3383 if (n
->name
== NULL
) {
3384 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
3385 return ERROR_COMMAND_SYNTAX_ERROR
;
3388 cortex_a
->isrmasking_mode
= n
->value
;
3391 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3392 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3397 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
3399 struct target
*target
= get_current_target(CMD_CTX
);
3400 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3402 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
3403 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
3404 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
3405 { .name
= NULL
, .value
= -1 },
3410 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
3411 if (n
->name
== NULL
)
3412 return ERROR_COMMAND_SYNTAX_ERROR
;
3413 cortex_a
->dacrfixup_mode
= n
->value
;
3417 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
3418 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3423 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3425 .name
= "cache_info",
3426 .handler
= cortex_a_handle_cache_info_command
,
3427 .mode
= COMMAND_EXEC
,
3428 .help
= "display information about target caches",
3433 .handler
= cortex_a_handle_dbginit_command
,
3434 .mode
= COMMAND_EXEC
,
3435 .help
= "Initialize core debug",
3438 { .name
= "smp_off",
3439 .handler
= cortex_a_handle_smp_off_command
,
3440 .mode
= COMMAND_EXEC
,
3441 .help
= "Stop smp handling",
3445 .handler
= cortex_a_handle_smp_on_command
,
3446 .mode
= COMMAND_EXEC
,
3447 .help
= "Restart smp handling",
3452 .handler
= cortex_a_handle_smp_gdb_command
,
3453 .mode
= COMMAND_EXEC
,
3454 .help
= "display/fix current core played to gdb",
3459 .handler
= handle_cortex_a_mask_interrupts_command
,
3460 .mode
= COMMAND_ANY
,
3461 .help
= "mask cortex_a interrupts",
3462 .usage
= "['on'|'off']",
3465 .name
= "dacrfixup",
3466 .handler
= handle_cortex_a_dacrfixup_command
,
3467 .mode
= COMMAND_EXEC
,
3468 .help
= "set domain access control (DACR) to all-manager "
3470 .usage
= "['on'|'off']",
3473 COMMAND_REGISTRATION_DONE
3475 static const struct command_registration cortex_a_command_handlers
[] = {
3477 .chain
= arm_command_handlers
,
3480 .chain
= armv7a_command_handlers
,
3484 .mode
= COMMAND_ANY
,
3485 .help
= "Cortex-A command group",
3487 .chain
= cortex_a_exec_command_handlers
,
3489 COMMAND_REGISTRATION_DONE
3492 struct target_type cortexa_target
= {
3494 .deprecated_name
= "cortex_a8",
3496 .poll
= cortex_a_poll
,
3497 .arch_state
= armv7a_arch_state
,
3499 .halt
= cortex_a_halt
,
3500 .resume
= cortex_a_resume
,
3501 .step
= cortex_a_step
,
3503 .assert_reset
= cortex_a_assert_reset
,
3504 .deassert_reset
= cortex_a_deassert_reset
,
3506 /* REVISIT allow exporting VFP3 registers ... */
3507 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3509 .read_memory
= cortex_a_read_memory
,
3510 .write_memory
= cortex_a_write_memory
,
3512 .read_buffer
= cortex_a_read_buffer
,
3513 .write_buffer
= cortex_a_write_buffer
,
3515 .checksum_memory
= arm_checksum_memory
,
3516 .blank_check_memory
= arm_blank_check_memory
,
3518 .run_algorithm
= armv4_5_run_algorithm
,
3520 .add_breakpoint
= cortex_a_add_breakpoint
,
3521 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3522 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3523 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3524 .add_watchpoint
= NULL
,
3525 .remove_watchpoint
= NULL
,
3527 .commands
= cortex_a_command_handlers
,
3528 .target_create
= cortex_a_target_create
,
3529 .init_target
= cortex_a_init_target
,
3530 .examine
= cortex_a_examine
,
3531 .deinit_target
= cortex_a_deinit_target
,
3533 .read_phys_memory
= cortex_a_read_phys_memory
,
3534 .write_phys_memory
= cortex_a_write_phys_memory
,
3535 .mmu
= cortex_a_mmu
,
3536 .virt2phys
= cortex_a_virt2phys
,
3539 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3541 .name
= "cache_info",
3542 .handler
= cortex_a_handle_cache_info_command
,
3543 .mode
= COMMAND_EXEC
,
3544 .help
= "display information about target caches",
3549 .handler
= cortex_a_handle_dbginit_command
,
3550 .mode
= COMMAND_EXEC
,
3551 .help
= "Initialize core debug",
3556 .handler
= handle_cortex_a_mask_interrupts_command
,
3557 .mode
= COMMAND_EXEC
,
3558 .help
= "mask cortex_r4 interrupts",
3559 .usage
= "['on'|'off']",
3562 COMMAND_REGISTRATION_DONE
3564 static const struct command_registration cortex_r4_command_handlers
[] = {
3566 .chain
= arm_command_handlers
,
3569 .chain
= armv7a_command_handlers
,
3572 .name
= "cortex_r4",
3573 .mode
= COMMAND_ANY
,
3574 .help
= "Cortex-R4 command group",
3576 .chain
= cortex_r4_exec_command_handlers
,
3578 COMMAND_REGISTRATION_DONE
3581 struct target_type cortexr4_target
= {
3582 .name
= "cortex_r4",
3584 .poll
= cortex_a_poll
,
3585 .arch_state
= armv7a_arch_state
,
3587 .halt
= cortex_a_halt
,
3588 .resume
= cortex_a_resume
,
3589 .step
= cortex_a_step
,
3591 .assert_reset
= cortex_a_assert_reset
,
3592 .deassert_reset
= cortex_a_deassert_reset
,
3594 /* REVISIT allow exporting VFP3 registers ... */
3595 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3597 .read_memory
= cortex_a_read_memory
,
3598 .write_memory
= cortex_a_write_memory
,
3600 .checksum_memory
= arm_checksum_memory
,
3601 .blank_check_memory
= arm_blank_check_memory
,
3603 .run_algorithm
= armv4_5_run_algorithm
,
3605 .add_breakpoint
= cortex_a_add_breakpoint
,
3606 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3607 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3608 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3609 .add_watchpoint
= NULL
,
3610 .remove_watchpoint
= NULL
,
3612 .commands
= cortex_r4_command_handlers
,
3613 .target_create
= cortex_r4_target_create
,
3614 .init_target
= cortex_a_init_target
,
3615 .examine
= cortex_a_examine
,
3616 .deinit_target
= cortex_a_deinit_target
,