1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "armv7a_mmu.h"
54 #include "target_request.h"
55 #include "target_type.h"
56 #include "arm_opcodes.h"
57 #include "arm_semihosting.h"
58 #include "transport/transport.h"
60 #include <helper/time_support.h>
62 static int cortex_a_poll(struct target
*target
);
63 static int cortex_a_debug_entry(struct target
*target
);
64 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
65 static int cortex_a_set_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_context_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
, uint8_t matchmode
);
69 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_unset_breakpoint(struct target
*target
,
72 struct breakpoint
*breakpoint
);
73 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
74 uint32_t value
, uint32_t *dscr
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
77 static int cortex_a_virt2phys(struct target
*target
,
78 target_addr_t virt
, target_addr_t
*phys
);
79 static int cortex_a_read_cpu_memory(struct target
*target
,
80 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
83 /* restore cp15_control_reg at resume */
84 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
86 int retval
= ERROR_OK
;
87 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
88 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
90 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
91 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
92 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
93 retval
= armv7a
->arm
.mcr(target
, 15,
96 cortex_a
->cp15_control_reg
);
102 * Set up ARM core for memory access.
103 * If !phys_access, switch to SVC mode and make sure MMU is on
104 * If phys_access, switch off mmu
106 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
108 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
109 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
112 if (phys_access
== 0) {
113 arm_dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
114 cortex_a_mmu(target
, &mmu_enabled
);
116 cortex_a_mmu_modify(target
, 1);
117 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
118 /* overwrite DACR to all-manager */
119 armv7a
->arm
.mcr(target
, 15,
124 cortex_a_mmu(target
, &mmu_enabled
);
126 cortex_a_mmu_modify(target
, 0);
132 * Restore ARM core after memory access.
133 * If !phys_access, switch to previous mode
134 * If phys_access, restore MMU setting
136 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
138 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
139 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
141 if (phys_access
== 0) {
142 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
144 armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_dacr_reg
);
148 arm_dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
151 cortex_a_mmu(target
, &mmu_enabled
);
153 cortex_a_mmu_modify(target
, 1);
159 /* modify cp15_control_reg in order to enable or disable mmu for :
160 * - virt2phys address conversion
161 * - read or write memory in phys or virt address */
162 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
164 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
165 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
166 int retval
= ERROR_OK
;
170 /* if mmu enabled at target stop and mmu not enable */
171 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
172 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
175 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
176 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
180 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
181 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
187 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
188 enable
? "enable mmu" : "disable mmu",
189 cortex_a
->cp15_control_reg_curr
);
191 retval
= armv7a
->arm
.mcr(target
, 15,
194 cortex_a
->cp15_control_reg_curr
);
200 * Cortex-A Basic debug access, very low level assumes state is saved
202 static int cortex_a_init_debug_access(struct target
*target
)
204 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
208 /* lock memory-mapped access to debug registers to prevent
209 * software interference */
210 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
211 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0);
212 if (retval
!= ERROR_OK
)
215 /* Disable cacheline fills and force cache write-through in debug state */
216 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
217 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
218 if (retval
!= ERROR_OK
)
221 /* Disable TLB lookup and refill/eviction in debug state */
222 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
223 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
224 if (retval
!= ERROR_OK
)
227 retval
= dap_run(armv7a
->debug_ap
->dap
);
228 if (retval
!= ERROR_OK
)
231 /* Enabling of instruction execution in debug mode is done in debug_entry code */
233 /* Resync breakpoint registers */
235 /* Enable halt for breakpoint, watchpoint and vector catch */
236 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
237 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
238 if (retval
!= ERROR_OK
)
240 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
241 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
242 if (retval
!= ERROR_OK
)
245 /* Since this is likely called from init or reset, update target state information*/
246 return cortex_a_poll(target
);
249 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
251 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
252 * Writes final value of DSCR into *dscr. Pass force to force always
253 * reading DSCR at least once. */
254 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
258 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
259 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
260 if (retval
!= ERROR_OK
) {
261 LOG_ERROR("Could not read DSCR register");
266 retval
= cortex_a_wait_dscr_bits(target
, DSCR_INSTR_COMP
, DSCR_INSTR_COMP
, dscr
);
267 if (retval
!= ERROR_OK
)
268 LOG_ERROR("Error waiting for InstrCompl=1");
272 /* To reduce needless round-trips, pass in a pointer to the current
273 * DSCR value. Initialize it to zero if you just need to know the
274 * value on return from this function; or DSCR_INSTR_COMP if you
275 * happen to know that no instruction is pending.
277 static int cortex_a_exec_opcode(struct target
*target
,
278 uint32_t opcode
, uint32_t *dscr_p
)
282 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
284 dscr
= dscr_p
? *dscr_p
: 0;
286 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
288 /* Wait for InstrCompl bit to be set */
289 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
290 if (retval
!= ERROR_OK
)
293 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
294 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
295 if (retval
!= ERROR_OK
)
298 /* Wait for InstrCompl bit to be set */
299 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
300 if (retval
!= ERROR_OK
) {
301 LOG_ERROR("Error waiting for cortex_a_exec_opcode");
311 /* Write to memory mapped registers directly with no cache or mmu handling */
312 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
317 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
319 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
325 * Cortex-A implementation of Debug Programmer's Model
327 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
328 * so there's no need to poll for it before executing an instruction.
330 * NOTE that in several of these cases the "stall" mode might be useful.
331 * It'd let us queue a few operations together... prepare/finish might
332 * be the places to enable/disable that mode.
335 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
337 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
340 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
342 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
343 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
344 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
347 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
350 uint32_t dscr
= DSCR_INSTR_COMP
;
356 /* Wait for DTRRXfull */
357 retval
= cortex_a_wait_dscr_bits(a
->armv7a_common
.arm
.target
,
358 DSCR_DTR_TX_FULL
, DSCR_DTR_TX_FULL
, &dscr
);
359 if (retval
!= ERROR_OK
) {
360 LOG_ERROR("Error waiting for read dcc");
364 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
365 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
366 if (retval
!= ERROR_OK
)
368 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
376 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
378 struct cortex_a_common
*a
= dpm_to_a(dpm
);
382 /* set up invariant: INSTR_COMP is set after ever DPM operation */
383 retval
= cortex_a_wait_instrcmpl(dpm
->arm
->target
, &dscr
, true);
384 if (retval
!= ERROR_OK
) {
385 LOG_ERROR("Error waiting for dpm prepare");
389 /* this "should never happen" ... */
390 if (dscr
& DSCR_DTR_RX_FULL
) {
391 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
393 retval
= cortex_a_exec_opcode(
394 a
->armv7a_common
.arm
.target
,
395 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
397 if (retval
!= ERROR_OK
)
404 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
406 /* REVISIT what could be done here? */
410 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
411 uint32_t opcode
, uint32_t data
)
413 struct cortex_a_common
*a
= dpm_to_a(dpm
);
415 uint32_t dscr
= DSCR_INSTR_COMP
;
417 retval
= cortex_a_write_dcc(a
, data
);
418 if (retval
!= ERROR_OK
)
421 return cortex_a_exec_opcode(
422 a
->armv7a_common
.arm
.target
,
427 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
428 uint32_t opcode
, uint32_t data
)
430 struct cortex_a_common
*a
= dpm_to_a(dpm
);
431 uint32_t dscr
= DSCR_INSTR_COMP
;
434 retval
= cortex_a_write_dcc(a
, data
);
435 if (retval
!= ERROR_OK
)
438 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
439 retval
= cortex_a_exec_opcode(
440 a
->armv7a_common
.arm
.target
,
441 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
443 if (retval
!= ERROR_OK
)
446 /* then the opcode, taking data from R0 */
447 retval
= cortex_a_exec_opcode(
448 a
->armv7a_common
.arm
.target
,
455 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
457 struct target
*target
= dpm
->arm
->target
;
458 uint32_t dscr
= DSCR_INSTR_COMP
;
460 /* "Prefetch flush" after modifying execution status in CPSR */
461 return cortex_a_exec_opcode(target
,
462 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
466 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
467 uint32_t opcode
, uint32_t *data
)
469 struct cortex_a_common
*a
= dpm_to_a(dpm
);
471 uint32_t dscr
= DSCR_INSTR_COMP
;
473 /* the opcode, writing data to DCC */
474 retval
= cortex_a_exec_opcode(
475 a
->armv7a_common
.arm
.target
,
478 if (retval
!= ERROR_OK
)
481 return cortex_a_read_dcc(a
, data
, &dscr
);
485 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
486 uint32_t opcode
, uint32_t *data
)
488 struct cortex_a_common
*a
= dpm_to_a(dpm
);
489 uint32_t dscr
= DSCR_INSTR_COMP
;
492 /* the opcode, writing data to R0 */
493 retval
= cortex_a_exec_opcode(
494 a
->armv7a_common
.arm
.target
,
497 if (retval
!= ERROR_OK
)
500 /* write R0 to DCC */
501 retval
= cortex_a_exec_opcode(
502 a
->armv7a_common
.arm
.target
,
503 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
505 if (retval
!= ERROR_OK
)
508 return cortex_a_read_dcc(a
, data
, &dscr
);
511 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
512 uint32_t addr
, uint32_t control
)
514 struct cortex_a_common
*a
= dpm_to_a(dpm
);
515 uint32_t vr
= a
->armv7a_common
.debug_base
;
516 uint32_t cr
= a
->armv7a_common
.debug_base
;
520 case 0 ... 15: /* breakpoints */
521 vr
+= CPUDBG_BVR_BASE
;
522 cr
+= CPUDBG_BCR_BASE
;
524 case 16 ... 31: /* watchpoints */
525 vr
+= CPUDBG_WVR_BASE
;
526 cr
+= CPUDBG_WCR_BASE
;
535 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
536 (unsigned) vr
, (unsigned) cr
);
538 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
540 if (retval
!= ERROR_OK
)
542 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
547 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
549 struct cortex_a_common
*a
= dpm_to_a(dpm
);
554 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
557 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
565 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
567 /* clear control register */
568 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
571 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
573 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
576 dpm
->arm
= &a
->armv7a_common
.arm
;
579 dpm
->prepare
= cortex_a_dpm_prepare
;
580 dpm
->finish
= cortex_a_dpm_finish
;
582 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
583 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
584 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
586 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
587 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
589 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
590 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
592 retval
= arm_dpm_setup(dpm
);
593 if (retval
== ERROR_OK
)
594 retval
= arm_dpm_initialize(dpm
);
598 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
600 struct target_list
*head
;
604 while (head
!= (struct target_list
*)NULL
) {
606 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
612 static int cortex_a_halt(struct target
*target
);
614 static int cortex_a_halt_smp(struct target
*target
)
617 struct target_list
*head
;
620 while (head
!= (struct target_list
*)NULL
) {
622 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
623 && target_was_examined(curr
))
624 retval
+= cortex_a_halt(curr
);
630 static int update_halt_gdb(struct target
*target
)
632 struct target
*gdb_target
= NULL
;
633 struct target_list
*head
;
637 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
638 target
->gdb_service
->target
= target
;
639 target
->gdb_service
->core
[0] = target
->coreid
;
640 retval
+= cortex_a_halt_smp(target
);
643 if (target
->gdb_service
)
644 gdb_target
= target
->gdb_service
->target
;
646 foreach_smp_target(head
, target
->head
) {
648 /* skip calling context */
651 if (!target_was_examined(curr
))
653 /* skip targets that were already halted */
654 if (curr
->state
== TARGET_HALTED
)
656 /* Skip gdb_target; it alerts GDB so has to be polled as last one */
657 if (curr
== gdb_target
)
660 /* avoid recursion in cortex_a_poll() */
666 /* after all targets were updated, poll the gdb serving target */
667 if (gdb_target
!= NULL
&& gdb_target
!= target
)
668 cortex_a_poll(gdb_target
);
673 * Cortex-A Run control
676 static int cortex_a_poll(struct target
*target
)
678 int retval
= ERROR_OK
;
680 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
681 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
682 enum target_state prev_target_state
= target
->state
;
683 /* toggle to another core is done by gdb as follow */
684 /* maint packet J core_id */
686 /* the next polling trigger an halt event sent to gdb */
687 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
688 (target
->gdb_service
) &&
689 (target
->gdb_service
->target
== NULL
)) {
690 target
->gdb_service
->target
=
691 get_cortex_a(target
, target
->gdb_service
->core
[1]);
692 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
695 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
696 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
697 if (retval
!= ERROR_OK
)
699 cortex_a
->cpudbg_dscr
= dscr
;
701 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
702 if (prev_target_state
!= TARGET_HALTED
) {
703 /* We have a halting debug event */
704 LOG_DEBUG("Target halted");
705 target
->state
= TARGET_HALTED
;
707 retval
= cortex_a_debug_entry(target
);
708 if (retval
!= ERROR_OK
)
712 retval
= update_halt_gdb(target
);
713 if (retval
!= ERROR_OK
)
717 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
718 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
719 } else { /* prev_target_state is RUNNING, UNKNOWN or RESET */
720 if (arm_semihosting(target
, &retval
) != 0)
723 target_call_event_callbacks(target
,
724 TARGET_EVENT_HALTED
);
728 target
->state
= TARGET_RUNNING
;
733 static int cortex_a_halt(struct target
*target
)
737 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
740 * Tell the core to be halted by writing DRCR with 0x1
741 * and then wait for the core to be halted.
743 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
744 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
745 if (retval
!= ERROR_OK
)
748 dscr
= 0; /* force read of dscr */
749 retval
= cortex_a_wait_dscr_bits(target
, DSCR_CORE_HALTED
,
750 DSCR_CORE_HALTED
, &dscr
);
751 if (retval
!= ERROR_OK
) {
752 LOG_ERROR("Error waiting for halt");
756 target
->debug_reason
= DBG_REASON_DBGRQ
;
761 static int cortex_a_internal_restore(struct target
*target
, int current
,
762 target_addr_t
*address
, int handle_breakpoints
, int debug_execution
)
764 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
765 struct arm
*arm
= &armv7a
->arm
;
769 if (!debug_execution
)
770 target_free_all_working_areas(target
);
773 if (debug_execution
) {
774 /* Disable interrupts */
775 /* We disable interrupts in the PRIMASK register instead of
776 * masking with C_MASKINTS,
777 * This is probably the same issue as Cortex-M3 Errata 377493:
778 * C_MASKINTS in parallel with disabled interrupts can cause
779 * local faults to not be taken. */
780 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
781 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= true;
782 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= true;
784 /* Make sure we are in Thumb mode */
785 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
786 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
788 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= true;
789 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= true;
793 /* current = 1: continue on current pc, otherwise continue at <address> */
794 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
796 resume_pc
= *address
;
798 *address
= resume_pc
;
800 /* Make sure that the Armv7 gdb thumb fixups does not
801 * kill the return address
803 switch (arm
->core_state
) {
805 resume_pc
&= 0xFFFFFFFC;
807 case ARM_STATE_THUMB
:
808 case ARM_STATE_THUMB_EE
:
809 /* When the return address is loaded into PC
810 * bit 0 must be 1 to stay in Thumb state
814 case ARM_STATE_JAZELLE
:
815 LOG_ERROR("How do I resume into Jazelle state??");
817 case ARM_STATE_AARCH64
:
818 LOG_ERROR("Shoudn't be in AARCH64 state");
821 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
822 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
823 arm
->pc
->dirty
= true;
824 arm
->pc
->valid
= true;
826 /* restore dpm_mode at system halt */
827 arm_dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
828 /* called it now before restoring context because it uses cpu
829 * register r0 for restoring cp15 control register */
830 retval
= cortex_a_restore_cp15_control_reg(target
);
831 if (retval
!= ERROR_OK
)
833 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
834 if (retval
!= ERROR_OK
)
836 target
->debug_reason
= DBG_REASON_NOTHALTED
;
837 target
->state
= TARGET_RUNNING
;
839 /* registers are now invalid */
840 register_cache_invalidate(arm
->core_cache
);
843 /* the front-end may request us not to handle breakpoints */
844 if (handle_breakpoints
) {
845 /* Single step past breakpoint at current address */
846 breakpoint
= breakpoint_find(target
, resume_pc
);
848 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
849 cortex_m3_unset_breakpoint(target
, breakpoint
);
850 cortex_m3_single_step_core(target
);
851 cortex_m3_set_breakpoint(target
, breakpoint
);
859 static int cortex_a_internal_restart(struct target
*target
)
861 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
862 struct arm
*arm
= &armv7a
->arm
;
866 * * Restart core and wait for it to be started. Clear ITRen and sticky
867 * * exception flags: see ARMv7 ARM, C5.9.
869 * REVISIT: for single stepping, we probably want to
870 * disable IRQs by default, with optional override...
873 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
874 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
875 if (retval
!= ERROR_OK
)
878 if ((dscr
& DSCR_INSTR_COMP
) == 0)
879 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
881 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
882 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
883 if (retval
!= ERROR_OK
)
886 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
887 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
888 DRCR_CLEAR_EXCEPTIONS
);
889 if (retval
!= ERROR_OK
)
892 dscr
= 0; /* force read of dscr */
893 retval
= cortex_a_wait_dscr_bits(target
, DSCR_CORE_RESTARTED
,
894 DSCR_CORE_RESTARTED
, &dscr
);
895 if (retval
!= ERROR_OK
) {
896 LOG_ERROR("Error waiting for resume");
900 target
->debug_reason
= DBG_REASON_NOTHALTED
;
901 target
->state
= TARGET_RUNNING
;
903 /* registers are now invalid */
904 register_cache_invalidate(arm
->core_cache
);
909 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
912 struct target_list
*head
;
914 target_addr_t address
;
916 while (head
!= (struct target_list
*)NULL
) {
918 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
919 && target_was_examined(curr
)) {
920 /* resume current address , not in step mode */
921 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
922 handle_breakpoints
, 0);
923 retval
+= cortex_a_internal_restart(curr
);
931 static int cortex_a_resume(struct target
*target
, int current
,
932 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
935 /* dummy resume for smp toggle in order to reduce gdb impact */
936 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
937 /* simulate a start and halt of target */
938 target
->gdb_service
->target
= NULL
;
939 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
940 /* fake resume at next poll we play the target core[1], see poll*/
941 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
944 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
946 target
->gdb_service
->core
[0] = -1;
947 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
948 if (retval
!= ERROR_OK
)
951 cortex_a_internal_restart(target
);
953 if (!debug_execution
) {
954 target
->state
= TARGET_RUNNING
;
955 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
956 LOG_DEBUG("target resumed at " TARGET_ADDR_FMT
, address
);
958 target
->state
= TARGET_DEBUG_RUNNING
;
959 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
960 LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT
, address
);
966 static int cortex_a_debug_entry(struct target
*target
)
969 int retval
= ERROR_OK
;
970 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
971 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
972 struct arm
*arm
= &armv7a
->arm
;
974 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
976 /* REVISIT surely we should not re-read DSCR !! */
977 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
978 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
979 if (retval
!= ERROR_OK
)
982 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
983 * imprecise data aborts get discarded by issuing a Data
984 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
987 /* Enable the ITR execution once we are in debug mode */
989 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
990 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
991 if (retval
!= ERROR_OK
)
994 /* Examine debug reason */
995 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
997 /* save address of instruction that triggered the watchpoint? */
998 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1001 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1002 armv7a
->debug_base
+ CPUDBG_WFAR
,
1004 if (retval
!= ERROR_OK
)
1006 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1009 /* First load register accessible through core debug port */
1010 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1011 if (retval
!= ERROR_OK
)
1016 retval
= arm_dpm_read_reg(&armv7a
->dpm
, arm
->spsr
, 17);
1017 if (retval
!= ERROR_OK
)
1022 /* TODO, Move this */
1023 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1024 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1025 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1027 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1028 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1030 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1031 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1034 /* Are we in an exception handler */
1035 /* armv4_5->exception_number = 0; */
1036 if (armv7a
->post_debug_entry
) {
1037 retval
= armv7a
->post_debug_entry(target
);
1038 if (retval
!= ERROR_OK
)
1045 static int cortex_a_post_debug_entry(struct target
*target
)
1047 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1048 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1051 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1052 retval
= armv7a
->arm
.mrc(target
, 15,
1053 0, 0, /* op1, op2 */
1054 1, 0, /* CRn, CRm */
1055 &cortex_a
->cp15_control_reg
);
1056 if (retval
!= ERROR_OK
)
1058 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1059 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1061 if (!armv7a
->is_armv7r
)
1062 armv7a_read_ttbcr(target
);
1064 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1065 armv7a_identify_cache(target
);
1067 if (armv7a
->is_armv7r
) {
1068 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1070 armv7a
->armv7a_mmu
.mmu_enabled
=
1071 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1073 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1074 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1075 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1076 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1077 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1079 /* switch to SVC mode to read DACR */
1080 arm_dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1081 armv7a
->arm
.mrc(target
, 15,
1083 &cortex_a
->cp15_dacr_reg
);
1085 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1086 cortex_a
->cp15_dacr_reg
);
1088 arm_dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1092 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1094 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1098 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1099 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1100 if (ERROR_OK
!= retval
)
1103 /* clear bitfield */
1106 dscr
|= value
& bit_mask
;
1108 /* write new DSCR */
1109 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1110 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1114 static int cortex_a_step(struct target
*target
, int current
, target_addr_t address
,
1115 int handle_breakpoints
)
1117 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1118 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1119 struct arm
*arm
= &armv7a
->arm
;
1120 struct breakpoint
*breakpoint
= NULL
;
1121 struct breakpoint stepbreakpoint
;
1125 if (target
->state
!= TARGET_HALTED
) {
1126 LOG_WARNING("target not halted");
1127 return ERROR_TARGET_NOT_HALTED
;
1130 /* current = 1: continue on current pc, otherwise continue at <address> */
1133 buf_set_u32(r
->value
, 0, 32, address
);
1135 address
= buf_get_u32(r
->value
, 0, 32);
1137 /* The front-end may request us not to handle breakpoints.
1138 * But since Cortex-A uses breakpoint for single step,
1139 * we MUST handle breakpoints.
1141 handle_breakpoints
= 1;
1142 if (handle_breakpoints
) {
1143 breakpoint
= breakpoint_find(target
, address
);
1145 cortex_a_unset_breakpoint(target
, breakpoint
);
1148 /* Setup single step breakpoint */
1149 stepbreakpoint
.address
= address
;
1150 stepbreakpoint
.asid
= 0;
1151 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1153 stepbreakpoint
.type
= BKPT_HARD
;
1154 stepbreakpoint
.set
= 0;
1156 /* Disable interrupts during single step if requested */
1157 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1158 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1159 if (ERROR_OK
!= retval
)
1163 /* Break on IVA mismatch */
1164 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1166 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1168 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1169 if (retval
!= ERROR_OK
)
1172 int64_t then
= timeval_ms();
1173 while (target
->state
!= TARGET_HALTED
) {
1174 retval
= cortex_a_poll(target
);
1175 if (retval
!= ERROR_OK
)
1177 if (target
->state
== TARGET_HALTED
)
1179 if (timeval_ms() > then
+ 1000) {
1180 LOG_ERROR("timeout waiting for target halt");
1185 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1187 /* Re-enable interrupts if they were disabled */
1188 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1189 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1190 if (ERROR_OK
!= retval
)
1195 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1198 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1200 if (target
->state
!= TARGET_HALTED
)
1201 LOG_DEBUG("target stepped");
1206 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1208 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1212 if (armv7a
->pre_restore_context
)
1213 armv7a
->pre_restore_context(target
);
1215 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1219 * Cortex-A Breakpoint and watchpoint functions
1222 /* Setup hardware Breakpoint Register Pair */
1223 static int cortex_a_set_breakpoint(struct target
*target
,
1224 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1229 uint8_t byte_addr_select
= 0x0F;
1230 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1231 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1232 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1234 if (breakpoint
->set
) {
1235 LOG_WARNING("breakpoint already set");
1239 if (breakpoint
->type
== BKPT_HARD
) {
1240 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1242 if (brp_i
>= cortex_a
->brp_num
) {
1243 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1244 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1246 breakpoint
->set
= brp_i
+ 1;
1247 if (breakpoint
->length
== 2)
1248 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1249 control
= ((matchmode
& 0x7) << 20)
1250 | (byte_addr_select
<< 5)
1252 brp_list
[brp_i
].used
= 1;
1253 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1254 brp_list
[brp_i
].control
= control
;
1255 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1256 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1257 brp_list
[brp_i
].value
);
1258 if (retval
!= ERROR_OK
)
1260 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1261 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1262 brp_list
[brp_i
].control
);
1263 if (retval
!= ERROR_OK
)
1265 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1266 brp_list
[brp_i
].control
,
1267 brp_list
[brp_i
].value
);
1268 } else if (breakpoint
->type
== BKPT_SOFT
) {
1270 /* length == 2: Thumb breakpoint */
1271 if (breakpoint
->length
== 2)
1272 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1274 /* length == 3: Thumb-2 breakpoint, actual encoding is
1275 * a regular Thumb BKPT instruction but we replace a
1276 * 32bit Thumb-2 instruction, so fix-up the breakpoint
1279 if (breakpoint
->length
== 3) {
1280 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1281 breakpoint
->length
= 4;
1283 /* length == 4, normal ARM breakpoint */
1284 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1286 retval
= target_read_memory(target
,
1287 breakpoint
->address
& 0xFFFFFFFE,
1288 breakpoint
->length
, 1,
1289 breakpoint
->orig_instr
);
1290 if (retval
!= ERROR_OK
)
1293 /* make sure data cache is cleaned & invalidated down to PoC */
1294 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1295 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1296 breakpoint
->length
);
1299 retval
= target_write_memory(target
,
1300 breakpoint
->address
& 0xFFFFFFFE,
1301 breakpoint
->length
, 1, code
);
1302 if (retval
!= ERROR_OK
)
1305 /* update i-cache at breakpoint location */
1306 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1307 breakpoint
->length
);
1308 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1309 breakpoint
->length
);
1311 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1317 static int cortex_a_set_context_breakpoint(struct target
*target
,
1318 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1320 int retval
= ERROR_FAIL
;
1323 uint8_t byte_addr_select
= 0x0F;
1324 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1325 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1326 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1328 if (breakpoint
->set
) {
1329 LOG_WARNING("breakpoint already set");
1332 /*check available context BRPs*/
1333 while ((brp_list
[brp_i
].used
||
1334 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1337 if (brp_i
>= cortex_a
->brp_num
) {
1338 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1342 breakpoint
->set
= brp_i
+ 1;
1343 control
= ((matchmode
& 0x7) << 20)
1344 | (byte_addr_select
<< 5)
1346 brp_list
[brp_i
].used
= 1;
1347 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1348 brp_list
[brp_i
].control
= control
;
1349 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1350 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1351 brp_list
[brp_i
].value
);
1352 if (retval
!= ERROR_OK
)
1354 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1355 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1356 brp_list
[brp_i
].control
);
1357 if (retval
!= ERROR_OK
)
1359 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1360 brp_list
[brp_i
].control
,
1361 brp_list
[brp_i
].value
);
1366 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1368 int retval
= ERROR_FAIL
;
1369 int brp_1
= 0; /* holds the contextID pair */
1370 int brp_2
= 0; /* holds the IVA pair */
1371 uint32_t control_CTX
, control_IVA
;
1372 uint8_t CTX_byte_addr_select
= 0x0F;
1373 uint8_t IVA_byte_addr_select
= 0x0F;
1374 uint8_t CTX_machmode
= 0x03;
1375 uint8_t IVA_machmode
= 0x01;
1376 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1377 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1378 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1380 if (breakpoint
->set
) {
1381 LOG_WARNING("breakpoint already set");
1384 /*check available context BRPs*/
1385 while ((brp_list
[brp_1
].used
||
1386 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1389 printf("brp(CTX) found num: %d\n", brp_1
);
1390 if (brp_1
>= cortex_a
->brp_num
) {
1391 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1395 while ((brp_list
[brp_2
].used
||
1396 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1399 printf("brp(IVA) found num: %d\n", brp_2
);
1400 if (brp_2
>= cortex_a
->brp_num
) {
1401 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1405 breakpoint
->set
= brp_1
+ 1;
1406 breakpoint
->linked_BRP
= brp_2
;
1407 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1410 | (CTX_byte_addr_select
<< 5)
1412 brp_list
[brp_1
].used
= 1;
1413 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1414 brp_list
[brp_1
].control
= control_CTX
;
1415 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1416 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1417 brp_list
[brp_1
].value
);
1418 if (retval
!= ERROR_OK
)
1420 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1421 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1422 brp_list
[brp_1
].control
);
1423 if (retval
!= ERROR_OK
)
1426 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1428 | (IVA_byte_addr_select
<< 5)
1430 brp_list
[brp_2
].used
= 1;
1431 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1432 brp_list
[brp_2
].control
= control_IVA
;
1433 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1434 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1435 brp_list
[brp_2
].value
);
1436 if (retval
!= ERROR_OK
)
1438 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1439 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1440 brp_list
[brp_2
].control
);
1441 if (retval
!= ERROR_OK
)
1447 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1450 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1451 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1452 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1454 if (!breakpoint
->set
) {
1455 LOG_WARNING("breakpoint not set");
1459 if (breakpoint
->type
== BKPT_HARD
) {
1460 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1461 int brp_i
= breakpoint
->set
- 1;
1462 int brp_j
= breakpoint
->linked_BRP
;
1463 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1464 LOG_DEBUG("Invalid BRP number in breakpoint");
1467 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1468 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1469 brp_list
[brp_i
].used
= 0;
1470 brp_list
[brp_i
].value
= 0;
1471 brp_list
[brp_i
].control
= 0;
1472 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1473 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1474 brp_list
[brp_i
].control
);
1475 if (retval
!= ERROR_OK
)
1477 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1478 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1479 brp_list
[brp_i
].value
);
1480 if (retval
!= ERROR_OK
)
1482 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1483 LOG_DEBUG("Invalid BRP number in breakpoint");
1486 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1487 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1488 brp_list
[brp_j
].used
= 0;
1489 brp_list
[brp_j
].value
= 0;
1490 brp_list
[brp_j
].control
= 0;
1491 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1492 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1493 brp_list
[brp_j
].control
);
1494 if (retval
!= ERROR_OK
)
1496 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1497 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1498 brp_list
[brp_j
].value
);
1499 if (retval
!= ERROR_OK
)
1501 breakpoint
->linked_BRP
= 0;
1502 breakpoint
->set
= 0;
1506 int brp_i
= breakpoint
->set
- 1;
1507 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1508 LOG_DEBUG("Invalid BRP number in breakpoint");
1511 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1512 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1513 brp_list
[brp_i
].used
= 0;
1514 brp_list
[brp_i
].value
= 0;
1515 brp_list
[brp_i
].control
= 0;
1516 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1517 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1518 brp_list
[brp_i
].control
);
1519 if (retval
!= ERROR_OK
)
1521 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1522 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1523 brp_list
[brp_i
].value
);
1524 if (retval
!= ERROR_OK
)
1526 breakpoint
->set
= 0;
1531 /* make sure data cache is cleaned & invalidated down to PoC */
1532 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1533 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1534 breakpoint
->length
);
1537 /* restore original instruction (kept in target endianness) */
1538 if (breakpoint
->length
== 4) {
1539 retval
= target_write_memory(target
,
1540 breakpoint
->address
& 0xFFFFFFFE,
1541 4, 1, breakpoint
->orig_instr
);
1542 if (retval
!= ERROR_OK
)
1545 retval
= target_write_memory(target
,
1546 breakpoint
->address
& 0xFFFFFFFE,
1547 2, 1, breakpoint
->orig_instr
);
1548 if (retval
!= ERROR_OK
)
1552 /* update i-cache at breakpoint location */
1553 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1554 breakpoint
->length
);
1555 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1556 breakpoint
->length
);
1558 breakpoint
->set
= 0;
1563 static int cortex_a_add_breakpoint(struct target
*target
,
1564 struct breakpoint
*breakpoint
)
1566 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1568 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1569 LOG_INFO("no hardware breakpoint available");
1570 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1573 if (breakpoint
->type
== BKPT_HARD
)
1574 cortex_a
->brp_num_available
--;
1576 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1579 static int cortex_a_add_context_breakpoint(struct target
*target
,
1580 struct breakpoint
*breakpoint
)
1582 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1584 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1585 LOG_INFO("no hardware breakpoint available");
1586 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1589 if (breakpoint
->type
== BKPT_HARD
)
1590 cortex_a
->brp_num_available
--;
1592 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1595 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1596 struct breakpoint
*breakpoint
)
1598 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1600 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1601 LOG_INFO("no hardware breakpoint available");
1602 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1605 if (breakpoint
->type
== BKPT_HARD
)
1606 cortex_a
->brp_num_available
--;
1608 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1612 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1614 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1617 /* It is perfectly possible to remove breakpoints while the target is running */
1618 if (target
->state
!= TARGET_HALTED
) {
1619 LOG_WARNING("target not halted");
1620 return ERROR_TARGET_NOT_HALTED
;
1624 if (breakpoint
->set
) {
1625 cortex_a_unset_breakpoint(target
, breakpoint
);
1626 if (breakpoint
->type
== BKPT_HARD
)
1627 cortex_a
->brp_num_available
++;
1635 * Cortex-A Reset functions
1638 static int cortex_a_assert_reset(struct target
*target
)
1640 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1644 /* FIXME when halt is requested, make it work somehow... */
1646 /* This function can be called in "target not examined" state */
1648 /* Issue some kind of warm reset. */
1649 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1650 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1651 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1652 /* REVISIT handle "pulls" cases, if there's
1653 * hardware that needs them to work.
1657 * FIXME: fix reset when transport is SWD. This is a temporary
1658 * work-around for release v0.10 that is not intended to stay!
1660 if (transport_is_swd() ||
1661 (target
->reset_halt
&& (jtag_get_reset_config() & RESET_SRST_NO_GATING
)))
1662 jtag_add_reset(0, 1);
1665 LOG_ERROR("%s: how to reset?", target_name(target
));
1669 /* registers are now invalid */
1670 if (target_was_examined(target
))
1671 register_cache_invalidate(armv7a
->arm
.core_cache
);
1673 target
->state
= TARGET_RESET
;
1678 static int cortex_a_deassert_reset(struct target
*target
)
1684 /* be certain SRST is off */
1685 jtag_add_reset(0, 0);
1687 if (target_was_examined(target
)) {
1688 retval
= cortex_a_poll(target
);
1689 if (retval
!= ERROR_OK
)
1693 if (target
->reset_halt
) {
1694 if (target
->state
!= TARGET_HALTED
) {
1695 LOG_WARNING("%s: ran after reset and before halt ...",
1696 target_name(target
));
1697 if (target_was_examined(target
)) {
1698 retval
= target_halt(target
);
1699 if (retval
!= ERROR_OK
)
1702 target
->state
= TARGET_UNKNOWN
;
1709 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1711 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1712 * New desired mode must be in mode. Current value of DSCR must be in
1713 * *dscr, which is updated with new value.
1715 * This function elides actually sending the mode-change over the debug
1716 * interface if the mode is already set as desired.
1718 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1719 if (new_dscr
!= *dscr
) {
1720 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1721 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1722 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1723 if (retval
== ERROR_OK
)
1731 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1732 uint32_t value
, uint32_t *dscr
)
1734 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1735 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1739 if ((*dscr
& mask
) == value
)
1742 then
= timeval_ms();
1744 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1745 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1746 if (retval
!= ERROR_OK
) {
1747 LOG_ERROR("Could not read DSCR register");
1750 if ((*dscr
& mask
) == value
)
1752 if (timeval_ms() > then
+ 1000) {
1753 LOG_ERROR("timeout waiting for DSCR bit change");
1760 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1761 uint32_t *data
, uint32_t *dscr
)
1764 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1766 /* Move from coprocessor to R0. */
1767 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1768 if (retval
!= ERROR_OK
)
1771 /* Move from R0 to DTRTX. */
1772 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1773 if (retval
!= ERROR_OK
)
1776 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1777 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1778 * must also check TXfull_l). Most of the time this will be free
1779 * because TXfull_l will be set immediately and cached in dscr. */
1780 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1781 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1782 if (retval
!= ERROR_OK
)
1785 /* Read the value transferred to DTRTX. */
1786 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1787 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1788 if (retval
!= ERROR_OK
)
1794 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
1795 uint32_t *dfsr
, uint32_t *dscr
)
1800 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
1801 if (retval
!= ERROR_OK
)
1806 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
1807 if (retval
!= ERROR_OK
)
1814 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
1815 uint32_t data
, uint32_t *dscr
)
1818 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1820 /* Write the value into DTRRX. */
1821 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1822 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
1823 if (retval
!= ERROR_OK
)
1826 /* Move from DTRRX to R0. */
1827 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
1828 if (retval
!= ERROR_OK
)
1831 /* Move from R0 to coprocessor. */
1832 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1833 if (retval
!= ERROR_OK
)
1836 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
1837 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
1838 * check RXfull_l). Most of the time this will be free because RXfull_l
1839 * will be cleared immediately and cached in dscr. */
1840 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
1841 if (retval
!= ERROR_OK
)
1847 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
1848 uint32_t dfsr
, uint32_t *dscr
)
1852 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
1853 if (retval
!= ERROR_OK
)
1856 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
1857 if (retval
!= ERROR_OK
)
1863 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
1865 uint32_t status
, upper4
;
1867 if (dfsr
& (1 << 9)) {
1869 status
= dfsr
& 0x3f;
1870 upper4
= status
>> 2;
1871 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
1872 return ERROR_TARGET_TRANSLATION_FAULT
;
1873 else if (status
== 33)
1874 return ERROR_TARGET_UNALIGNED_ACCESS
;
1876 return ERROR_TARGET_DATA_ABORT
;
1878 /* Normal format. */
1879 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
1881 return ERROR_TARGET_UNALIGNED_ACCESS
;
1882 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
1883 status
== 9 || status
== 11 || status
== 13 || status
== 15)
1884 return ERROR_TARGET_TRANSLATION_FAULT
;
1886 return ERROR_TARGET_DATA_ABORT
;
1890 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
1891 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
1893 /* Writes count objects of size size from *buffer. Old value of DSCR must
1894 * be in *dscr; updated to new value. This is slow because it works for
1895 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
1896 * the address is aligned, cortex_a_write_cpu_memory_fast should be
1899 * - Address is in R0.
1900 * - R0 is marked dirty.
1902 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1903 struct arm
*arm
= &armv7a
->arm
;
1906 /* Mark register R1 as dirty, to use for transferring data. */
1907 arm_reg_current(arm
, 1)->dirty
= true;
1909 /* Switch to non-blocking mode if not already in that mode. */
1910 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
1911 if (retval
!= ERROR_OK
)
1914 /* Go through the objects. */
1916 /* Write the value to store into DTRRX. */
1917 uint32_t data
, opcode
;
1921 data
= target_buffer_get_u16(target
, buffer
);
1923 data
= target_buffer_get_u32(target
, buffer
);
1924 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1925 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
1926 if (retval
!= ERROR_OK
)
1929 /* Transfer the value from DTRRX to R1. */
1930 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
1931 if (retval
!= ERROR_OK
)
1934 /* Write the value transferred to R1 into memory. */
1936 opcode
= ARMV4_5_STRB_IP(1, 0);
1938 opcode
= ARMV4_5_STRH_IP(1, 0);
1940 opcode
= ARMV4_5_STRW_IP(1, 0);
1941 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1942 if (retval
!= ERROR_OK
)
1945 /* Check for faults and return early. */
1946 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
1947 return ERROR_OK
; /* A data fault is not considered a system failure. */
1949 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
1950 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1951 * must also check RXfull_l). Most of the time this will be free
1952 * because RXfull_l will be cleared immediately and cached in dscr. */
1953 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
1954 if (retval
!= ERROR_OK
)
1965 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
1966 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
1968 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
1969 * in *dscr; updated to new value. This is fast but only works for
1970 * word-sized objects at aligned addresses.
1972 * - Address is in R0 and must be a multiple of 4.
1973 * - R0 is marked dirty.
1975 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1978 /* Switch to fast mode if not already in that mode. */
1979 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
1980 if (retval
!= ERROR_OK
)
1983 /* Latch STC instruction. */
1984 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1985 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
1986 if (retval
!= ERROR_OK
)
1989 /* Transfer all the data and issue all the instructions. */
1990 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
1991 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
1994 static int cortex_a_write_cpu_memory(struct target
*target
,
1995 uint32_t address
, uint32_t size
,
1996 uint32_t count
, const uint8_t *buffer
)
1998 /* Write memory through the CPU. */
1999 int retval
, final_retval
;
2000 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2001 struct arm
*arm
= &armv7a
->arm
;
2002 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2004 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2005 address
, size
, count
);
2006 if (target
->state
!= TARGET_HALTED
) {
2007 LOG_WARNING("target not halted");
2008 return ERROR_TARGET_NOT_HALTED
;
2014 /* Clear any abort. */
2015 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2016 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2017 if (retval
!= ERROR_OK
)
2021 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2022 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2023 if (retval
!= ERROR_OK
)
2026 /* Switch to non-blocking mode if not already in that mode. */
2027 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2028 if (retval
!= ERROR_OK
)
2031 /* Mark R0 as dirty. */
2032 arm_reg_current(arm
, 0)->dirty
= true;
2034 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2035 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2036 if (retval
!= ERROR_OK
)
2039 /* Get the memory address into R0. */
2040 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2041 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2042 if (retval
!= ERROR_OK
)
2044 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2045 if (retval
!= ERROR_OK
)
2048 if (size
== 4 && (address
% 4) == 0) {
2049 /* We are doing a word-aligned transfer, so use fast mode. */
2050 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2052 /* Use slow path. */
2053 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2057 final_retval
= retval
;
2059 /* Switch to non-blocking mode if not already in that mode. */
2060 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2061 if (final_retval
== ERROR_OK
)
2062 final_retval
= retval
;
2064 /* Wait for last issued instruction to complete. */
2065 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2066 if (final_retval
== ERROR_OK
)
2067 final_retval
= retval
;
2069 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2070 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2071 * check RXfull_l). Most of the time this will be free because RXfull_l
2072 * will be cleared immediately and cached in dscr. However, don't do this
2073 * if there is fault, because then the instruction might not have completed
2075 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2076 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2077 if (retval
!= ERROR_OK
)
2081 /* If there were any sticky abort flags, clear them. */
2082 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2084 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2085 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2086 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2091 /* Handle synchronous data faults. */
2092 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2093 if (final_retval
== ERROR_OK
) {
2094 /* Final return value will reflect cause of fault. */
2095 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2096 if (retval
== ERROR_OK
) {
2097 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2098 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2100 final_retval
= retval
;
2102 /* Fault destroyed DFAR/DFSR; restore them. */
2103 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2104 if (retval
!= ERROR_OK
)
2105 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2108 /* Handle asynchronous data faults. */
2109 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2110 if (final_retval
== ERROR_OK
)
2111 /* No other error has been recorded so far, so keep this one. */
2112 final_retval
= ERROR_TARGET_DATA_ABORT
;
2115 /* If the DCC is nonempty, clear it. */
2116 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2118 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2119 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2120 if (final_retval
== ERROR_OK
)
2121 final_retval
= retval
;
2123 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2124 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2125 if (final_retval
== ERROR_OK
)
2126 final_retval
= retval
;
2130 return final_retval
;
2133 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2134 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2136 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2137 * in *dscr; updated to new value. This is slow because it works for
2138 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2139 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2142 * - Address is in R0.
2143 * - R0 is marked dirty.
2145 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2146 struct arm
*arm
= &armv7a
->arm
;
2149 /* Mark register R1 as dirty, to use for transferring data. */
2150 arm_reg_current(arm
, 1)->dirty
= true;
2152 /* Switch to non-blocking mode if not already in that mode. */
2153 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2154 if (retval
!= ERROR_OK
)
2157 /* Go through the objects. */
2159 /* Issue a load of the appropriate size to R1. */
2160 uint32_t opcode
, data
;
2162 opcode
= ARMV4_5_LDRB_IP(1, 0);
2164 opcode
= ARMV4_5_LDRH_IP(1, 0);
2166 opcode
= ARMV4_5_LDRW_IP(1, 0);
2167 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2168 if (retval
!= ERROR_OK
)
2171 /* Issue a write of R1 to DTRTX. */
2172 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2173 if (retval
!= ERROR_OK
)
2176 /* Check for faults and return early. */
2177 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2178 return ERROR_OK
; /* A data fault is not considered a system failure. */
2180 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2181 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2182 * must also check TXfull_l). Most of the time this will be free
2183 * because TXfull_l will be set immediately and cached in dscr. */
2184 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2185 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2186 if (retval
!= ERROR_OK
)
2189 /* Read the value transferred to DTRTX into the buffer. */
2190 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2191 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2192 if (retval
!= ERROR_OK
)
2195 *buffer
= (uint8_t) data
;
2197 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2199 target_buffer_set_u32(target
, buffer
, data
);
2209 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2210 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2212 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2213 * *dscr; updated to new value. This is fast but only works for word-sized
2214 * objects at aligned addresses.
2216 * - Address is in R0 and must be a multiple of 4.
2217 * - R0 is marked dirty.
2219 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2223 /* Switch to non-blocking mode if not already in that mode. */
2224 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2225 if (retval
!= ERROR_OK
)
2228 /* Issue the LDC instruction via a write to ITR. */
2229 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2230 if (retval
!= ERROR_OK
)
2236 /* Switch to fast mode if not already in that mode. */
2237 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2238 if (retval
!= ERROR_OK
)
2241 /* Latch LDC instruction. */
2242 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2243 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2244 if (retval
!= ERROR_OK
)
2247 /* Read the value transferred to DTRTX into the buffer. Due to fast
2248 * mode rules, this blocks until the instruction finishes executing and
2249 * then reissues the read instruction to read the next word from
2250 * memory. The last read of DTRTX in this call reads the second-to-last
2251 * word from memory and issues the read instruction for the last word.
2253 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2254 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2255 if (retval
!= ERROR_OK
)
2259 buffer
+= count
* 4;
2262 /* Wait for last issued instruction to complete. */
2263 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2264 if (retval
!= ERROR_OK
)
2267 /* Switch to non-blocking mode if not already in that mode. */
2268 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2269 if (retval
!= ERROR_OK
)
2272 /* Check for faults and return early. */
2273 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2274 return ERROR_OK
; /* A data fault is not considered a system failure. */
2276 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2277 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2278 * check TXfull_l). Most of the time this will be free because TXfull_l
2279 * will be set immediately and cached in dscr. */
2280 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2281 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2282 if (retval
!= ERROR_OK
)
2285 /* Read the value transferred to DTRTX into the buffer. This is the last
2287 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2288 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2289 if (retval
!= ERROR_OK
)
2291 target_buffer_set_u32(target
, buffer
, u32
);
2296 static int cortex_a_read_cpu_memory(struct target
*target
,
2297 uint32_t address
, uint32_t size
,
2298 uint32_t count
, uint8_t *buffer
)
2300 /* Read memory through the CPU. */
2301 int retval
, final_retval
;
2302 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2303 struct arm
*arm
= &armv7a
->arm
;
2304 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2306 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2307 address
, size
, count
);
2308 if (target
->state
!= TARGET_HALTED
) {
2309 LOG_WARNING("target not halted");
2310 return ERROR_TARGET_NOT_HALTED
;
2316 /* Clear any abort. */
2317 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2318 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2319 if (retval
!= ERROR_OK
)
2323 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2324 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2325 if (retval
!= ERROR_OK
)
2328 /* Switch to non-blocking mode if not already in that mode. */
2329 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2330 if (retval
!= ERROR_OK
)
2333 /* Mark R0 as dirty. */
2334 arm_reg_current(arm
, 0)->dirty
= true;
2336 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2337 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2338 if (retval
!= ERROR_OK
)
2341 /* Get the memory address into R0. */
2342 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2343 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2344 if (retval
!= ERROR_OK
)
2346 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2347 if (retval
!= ERROR_OK
)
2350 if (size
== 4 && (address
% 4) == 0) {
2351 /* We are doing a word-aligned transfer, so use fast mode. */
2352 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2354 /* Use slow path. */
2355 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2359 final_retval
= retval
;
2361 /* Switch to non-blocking mode if not already in that mode. */
2362 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2363 if (final_retval
== ERROR_OK
)
2364 final_retval
= retval
;
2366 /* Wait for last issued instruction to complete. */
2367 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2368 if (final_retval
== ERROR_OK
)
2369 final_retval
= retval
;
2371 /* If there were any sticky abort flags, clear them. */
2372 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2374 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2375 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2376 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2381 /* Handle synchronous data faults. */
2382 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2383 if (final_retval
== ERROR_OK
) {
2384 /* Final return value will reflect cause of fault. */
2385 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2386 if (retval
== ERROR_OK
) {
2387 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2388 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2390 final_retval
= retval
;
2392 /* Fault destroyed DFAR/DFSR; restore them. */
2393 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2394 if (retval
!= ERROR_OK
)
2395 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2398 /* Handle asynchronous data faults. */
2399 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2400 if (final_retval
== ERROR_OK
)
2401 /* No other error has been recorded so far, so keep this one. */
2402 final_retval
= ERROR_TARGET_DATA_ABORT
;
2405 /* If the DCC is nonempty, clear it. */
2406 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2408 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2409 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2410 if (final_retval
== ERROR_OK
)
2411 final_retval
= retval
;
2413 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2414 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2415 if (final_retval
== ERROR_OK
)
2416 final_retval
= retval
;
2420 return final_retval
;
2425 * Cortex-A Memory access
2427 * This is same Cortex-M3 but we must also use the correct
2428 * ap number for every access.
2431 static int cortex_a_read_phys_memory(struct target
*target
,
2432 target_addr_t address
, uint32_t size
,
2433 uint32_t count
, uint8_t *buffer
)
2437 if (!count
|| !buffer
)
2438 return ERROR_COMMAND_SYNTAX_ERROR
;
2440 LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2441 address
, size
, count
);
2443 /* read memory through the CPU */
2444 cortex_a_prep_memaccess(target
, 1);
2445 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2446 cortex_a_post_memaccess(target
, 1);
2451 static int cortex_a_read_memory(struct target
*target
, target_addr_t address
,
2452 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2456 /* cortex_a handles unaligned memory access */
2457 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2458 address
, size
, count
);
2460 cortex_a_prep_memaccess(target
, 0);
2461 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2462 cortex_a_post_memaccess(target
, 0);
2467 static int cortex_a_write_phys_memory(struct target
*target
,
2468 target_addr_t address
, uint32_t size
,
2469 uint32_t count
, const uint8_t *buffer
)
2473 if (!count
|| !buffer
)
2474 return ERROR_COMMAND_SYNTAX_ERROR
;
2476 LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2477 address
, size
, count
);
2479 /* write memory through the CPU */
2480 cortex_a_prep_memaccess(target
, 1);
2481 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2482 cortex_a_post_memaccess(target
, 1);
2487 static int cortex_a_write_memory(struct target
*target
, target_addr_t address
,
2488 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2492 /* cortex_a handles unaligned memory access */
2493 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2494 address
, size
, count
);
2496 /* memory writes bypass the caches, must flush before writing */
2497 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2499 cortex_a_prep_memaccess(target
, 0);
2500 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2501 cortex_a_post_memaccess(target
, 0);
2505 static int cortex_a_read_buffer(struct target
*target
, target_addr_t address
,
2506 uint32_t count
, uint8_t *buffer
)
2510 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2511 * will have something to do with the size we leave to it. */
2512 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2513 if (address
& size
) {
2514 int retval
= target_read_memory(target
, address
, size
, 1, buffer
);
2515 if (retval
!= ERROR_OK
)
2523 /* Read the data with as large access size as possible. */
2524 for (; size
> 0; size
/= 2) {
2525 uint32_t aligned
= count
- count
% size
;
2527 int retval
= target_read_memory(target
, address
, size
, aligned
/ size
, buffer
);
2528 if (retval
!= ERROR_OK
)
2539 static int cortex_a_write_buffer(struct target
*target
, target_addr_t address
,
2540 uint32_t count
, const uint8_t *buffer
)
2544 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2545 * will have something to do with the size we leave to it. */
2546 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2547 if (address
& size
) {
2548 int retval
= target_write_memory(target
, address
, size
, 1, buffer
);
2549 if (retval
!= ERROR_OK
)
2557 /* Write the data with as large access size as possible. */
2558 for (; size
> 0; size
/= 2) {
2559 uint32_t aligned
= count
- count
% size
;
2561 int retval
= target_write_memory(target
, address
, size
, aligned
/ size
, buffer
);
2562 if (retval
!= ERROR_OK
)
2573 static int cortex_a_handle_target_request(void *priv
)
2575 struct target
*target
= priv
;
2576 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2579 if (!target_was_examined(target
))
2581 if (!target
->dbg_msg_enabled
)
2584 if (target
->state
== TARGET_RUNNING
) {
2587 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2588 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2590 /* check if we have data */
2591 int64_t then
= timeval_ms();
2592 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2593 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2594 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2595 if (retval
== ERROR_OK
) {
2596 target_request(target
, request
);
2597 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2598 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2600 if (timeval_ms() > then
+ 1000) {
2601 LOG_ERROR("Timeout waiting for dtr tx full");
2611 * Cortex-A target information and configuration
2614 static int cortex_a_examine_first(struct target
*target
)
2616 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2617 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2618 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2621 int retval
= ERROR_OK
;
2622 uint32_t didr
, cpuid
, dbg_osreg
;
2624 /* Search for the APB-AP - it is needed for access to debug registers */
2625 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2626 if (retval
!= ERROR_OK
) {
2627 LOG_ERROR("Could not find APB-AP for debug access");
2631 retval
= mem_ap_init(armv7a
->debug_ap
);
2632 if (retval
!= ERROR_OK
) {
2633 LOG_ERROR("Could not initialize the APB-AP");
2637 armv7a
->debug_ap
->memaccess_tck
= 80;
2639 if (!target
->dbgbase_set
) {
2641 /* Get ROM Table base */
2643 int32_t coreidx
= target
->coreid
;
2644 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2646 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
2647 if (retval
!= ERROR_OK
)
2649 /* Lookup 0x15 -- Processor DAP */
2650 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
2651 &armv7a
->debug_base
, &coreidx
);
2652 if (retval
!= ERROR_OK
) {
2653 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2657 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2658 target
->coreid
, armv7a
->debug_base
);
2660 armv7a
->debug_base
= target
->dbgbase
;
2662 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2663 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2664 if (retval
!= ERROR_OK
) {
2665 LOG_DEBUG("Examine %s failed", "DIDR");
2669 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2670 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
2671 if (retval
!= ERROR_OK
) {
2672 LOG_DEBUG("Examine %s failed", "CPUID");
2676 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
2677 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
2679 cortex_a
->didr
= didr
;
2680 cortex_a
->cpuid
= cpuid
;
2682 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2683 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
2684 if (retval
!= ERROR_OK
)
2686 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2688 if ((dbg_osreg
& PRSR_POWERUP_STATUS
) == 0) {
2689 LOG_ERROR("target->coreid %" PRId32
" powered down!", target
->coreid
);
2690 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
2691 return ERROR_TARGET_INIT_FAILED
;
2694 if (dbg_osreg
& PRSR_STICKY_RESET_STATUS
)
2695 LOG_DEBUG("target->coreid %" PRId32
" was reset!", target
->coreid
);
2697 /* Read DBGOSLSR and check if OSLK is implemented */
2698 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2699 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
2700 if (retval
!= ERROR_OK
)
2702 LOG_DEBUG("target->coreid %" PRId32
" DBGOSLSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
2704 /* check if OS Lock is implemented */
2705 if ((dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM0
|| (dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM1
) {
2706 /* check if OS Lock is set */
2707 if (dbg_osreg
& OSLSR_OSLK
) {
2708 LOG_DEBUG("target->coreid %" PRId32
" OSLock set! Trying to unlock", target
->coreid
);
2710 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2711 armv7a
->debug_base
+ CPUDBG_OSLAR
,
2713 if (retval
== ERROR_OK
)
2714 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2715 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
2717 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
2718 if (retval
!= ERROR_OK
|| (dbg_osreg
& OSLSR_OSLK
) != 0) {
2719 LOG_ERROR("target->coreid %" PRId32
" OSLock sticky, core not powered?",
2721 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
2722 return ERROR_TARGET_INIT_FAILED
;
2727 armv7a
->arm
.core_type
= ARM_MODE_MON
;
2729 /* Avoid recreating the registers cache */
2730 if (!target_was_examined(target
)) {
2731 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
2732 if (retval
!= ERROR_OK
)
2736 /* Setup Breakpoint Register Pairs */
2737 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
2738 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
2739 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
2740 free(cortex_a
->brp_list
);
2741 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
2742 /* cortex_a->brb_enabled = ????; */
2743 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
2744 cortex_a
->brp_list
[i
].used
= 0;
2745 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
2746 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
2748 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
2749 cortex_a
->brp_list
[i
].value
= 0;
2750 cortex_a
->brp_list
[i
].control
= 0;
2751 cortex_a
->brp_list
[i
].BRPn
= i
;
2754 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
2756 /* select debug_ap as default */
2757 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
2759 target_set_examined(target
);
2763 static int cortex_a_examine(struct target
*target
)
2765 int retval
= ERROR_OK
;
2767 /* Reestablish communication after target reset */
2768 retval
= cortex_a_examine_first(target
);
2770 /* Configure core debug access */
2771 if (retval
== ERROR_OK
)
2772 retval
= cortex_a_init_debug_access(target
);
2778 * Cortex-A target creation and initialization
2781 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
2782 struct target
*target
)
2784 /* examine_first() does a bunch of this */
2785 arm_semihosting_init(target
);
2789 static int cortex_a_init_arch_info(struct target
*target
,
2790 struct cortex_a_common
*cortex_a
, struct adiv5_dap
*dap
)
2792 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2794 /* Setup struct cortex_a_common */
2795 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2796 armv7a
->arm
.dap
= dap
;
2798 /* register arch-specific functions */
2799 armv7a
->examine_debug_reason
= NULL
;
2801 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
2803 armv7a
->pre_restore_context
= NULL
;
2805 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
2808 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
2810 /* REVISIT v7a setup should be in a v7a-specific routine */
2811 armv7a_init_arch_info(target
, armv7a
);
2812 target_register_timer_callback(cortex_a_handle_target_request
, 1,
2813 TARGET_TIMER_TYPE_PERIODIC
, target
);
2818 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
2820 struct cortex_a_common
*cortex_a
;
2821 struct adiv5_private_config
*pc
;
2823 if (target
->private_config
== NULL
)
2826 pc
= (struct adiv5_private_config
*)target
->private_config
;
2828 cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2829 if (cortex_a
== NULL
) {
2830 LOG_ERROR("Out of memory");
2833 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2834 cortex_a
->armv7a_common
.is_armv7r
= false;
2835 cortex_a
->armv7a_common
.arm
.arm_vfp_version
= ARM_VFP_V3
;
2837 return cortex_a_init_arch_info(target
, cortex_a
, pc
->dap
);
2840 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
2842 struct cortex_a_common
*cortex_a
;
2843 struct adiv5_private_config
*pc
;
2845 pc
= (struct adiv5_private_config
*)target
->private_config
;
2846 if (adiv5_verify_config(pc
) != ERROR_OK
)
2849 cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
2850 if (cortex_a
== NULL
) {
2851 LOG_ERROR("Out of memory");
2854 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
2855 cortex_a
->armv7a_common
.is_armv7r
= true;
2857 return cortex_a_init_arch_info(target
, cortex_a
, pc
->dap
);
2860 static void cortex_a_deinit_target(struct target
*target
)
2862 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2863 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2864 struct arm_dpm
*dpm
= &armv7a
->dpm
;
2868 if (target_was_examined(target
)) {
2869 /* Disable halt for breakpoint, watchpoint and vector catch */
2870 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2871 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2872 if (retval
== ERROR_OK
)
2873 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2874 armv7a
->debug_base
+ CPUDBG_DSCR
,
2875 dscr
& ~DSCR_HALT_DBG_MODE
);
2878 free(cortex_a
->brp_list
);
2881 free(target
->private_config
);
2885 static int cortex_a_mmu(struct target
*target
, int *enabled
)
2887 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2889 if (target
->state
!= TARGET_HALTED
) {
2890 LOG_ERROR("%s: target not halted", __func__
);
2891 return ERROR_TARGET_INVALID
;
2894 if (armv7a
->is_armv7r
)
2897 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
2902 static int cortex_a_virt2phys(struct target
*target
,
2903 target_addr_t virt
, target_addr_t
*phys
)
2906 int mmu_enabled
= 0;
2909 * If the MMU was not enabled at debug entry, there is no
2910 * way of knowing if there was ever a valid configuration
2911 * for it and thus it's not safe to enable it. In this case,
2912 * just return the virtual address as physical.
2914 cortex_a_mmu(target
, &mmu_enabled
);
2920 /* mmu must be enable in order to get a correct translation */
2921 retval
= cortex_a_mmu_modify(target
, 1);
2922 if (retval
!= ERROR_OK
)
2924 return armv7a_mmu_translate_va_pa(target
, (uint32_t)virt
,
2925 (uint32_t *)phys
, 1);
2928 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
2930 struct target
*target
= get_current_target(CMD_CTX
);
2931 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2933 return armv7a_handle_cache_info_command(CMD_CTX
,
2934 &armv7a
->armv7a_mmu
.armv7a_cache
);
2938 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
2940 struct target
*target
= get_current_target(CMD_CTX
);
2941 if (!target_was_examined(target
)) {
2942 LOG_ERROR("target not examined yet");
2946 return cortex_a_init_debug_access(target
);
2949 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
2951 struct target
*target
= get_current_target(CMD_CTX
);
2952 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2954 static const Jim_Nvp nvp_maskisr_modes
[] = {
2955 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
2956 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
2957 { .name
= NULL
, .value
= -1 },
2962 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2963 if (n
->name
== NULL
) {
2964 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
2965 return ERROR_COMMAND_SYNTAX_ERROR
;
2968 cortex_a
->isrmasking_mode
= n
->value
;
2971 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
2972 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
2977 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
2979 struct target
*target
= get_current_target(CMD_CTX
);
2980 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2982 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
2983 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
2984 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
2985 { .name
= NULL
, .value
= -1 },
2990 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
2991 if (n
->name
== NULL
)
2992 return ERROR_COMMAND_SYNTAX_ERROR
;
2993 cortex_a
->dacrfixup_mode
= n
->value
;
2997 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
2998 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3003 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3005 .name
= "cache_info",
3006 .handler
= cortex_a_handle_cache_info_command
,
3007 .mode
= COMMAND_EXEC
,
3008 .help
= "display information about target caches",
3013 .handler
= cortex_a_handle_dbginit_command
,
3014 .mode
= COMMAND_EXEC
,
3015 .help
= "Initialize core debug",
3020 .handler
= handle_cortex_a_mask_interrupts_command
,
3021 .mode
= COMMAND_ANY
,
3022 .help
= "mask cortex_a interrupts",
3023 .usage
= "['on'|'off']",
3026 .name
= "dacrfixup",
3027 .handler
= handle_cortex_a_dacrfixup_command
,
3028 .mode
= COMMAND_ANY
,
3029 .help
= "set domain access control (DACR) to all-manager "
3031 .usage
= "['on'|'off']",
3034 .chain
= armv7a_mmu_command_handlers
,
3037 .chain
= smp_command_handlers
,
3040 COMMAND_REGISTRATION_DONE
3042 static const struct command_registration cortex_a_command_handlers
[] = {
3044 .chain
= arm_command_handlers
,
3047 .chain
= armv7a_command_handlers
,
3051 .mode
= COMMAND_ANY
,
3052 .help
= "Cortex-A command group",
3054 .chain
= cortex_a_exec_command_handlers
,
3056 COMMAND_REGISTRATION_DONE
3059 struct target_type cortexa_target
= {
3061 .deprecated_name
= "cortex_a8",
3063 .poll
= cortex_a_poll
,
3064 .arch_state
= armv7a_arch_state
,
3066 .halt
= cortex_a_halt
,
3067 .resume
= cortex_a_resume
,
3068 .step
= cortex_a_step
,
3070 .assert_reset
= cortex_a_assert_reset
,
3071 .deassert_reset
= cortex_a_deassert_reset
,
3073 /* REVISIT allow exporting VFP3 registers ... */
3074 .get_gdb_arch
= arm_get_gdb_arch
,
3075 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3077 .read_memory
= cortex_a_read_memory
,
3078 .write_memory
= cortex_a_write_memory
,
3080 .read_buffer
= cortex_a_read_buffer
,
3081 .write_buffer
= cortex_a_write_buffer
,
3083 .checksum_memory
= arm_checksum_memory
,
3084 .blank_check_memory
= arm_blank_check_memory
,
3086 .run_algorithm
= armv4_5_run_algorithm
,
3088 .add_breakpoint
= cortex_a_add_breakpoint
,
3089 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3090 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3091 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3092 .add_watchpoint
= NULL
,
3093 .remove_watchpoint
= NULL
,
3095 .commands
= cortex_a_command_handlers
,
3096 .target_create
= cortex_a_target_create
,
3097 .target_jim_configure
= adiv5_jim_configure
,
3098 .init_target
= cortex_a_init_target
,
3099 .examine
= cortex_a_examine
,
3100 .deinit_target
= cortex_a_deinit_target
,
3102 .read_phys_memory
= cortex_a_read_phys_memory
,
3103 .write_phys_memory
= cortex_a_write_phys_memory
,
3104 .mmu
= cortex_a_mmu
,
3105 .virt2phys
= cortex_a_virt2phys
,
3108 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3111 .handler
= cortex_a_handle_dbginit_command
,
3112 .mode
= COMMAND_EXEC
,
3113 .help
= "Initialize core debug",
3118 .handler
= handle_cortex_a_mask_interrupts_command
,
3119 .mode
= COMMAND_EXEC
,
3120 .help
= "mask cortex_r4 interrupts",
3121 .usage
= "['on'|'off']",
3124 COMMAND_REGISTRATION_DONE
3126 static const struct command_registration cortex_r4_command_handlers
[] = {
3128 .chain
= arm_command_handlers
,
3131 .name
= "cortex_r4",
3132 .mode
= COMMAND_ANY
,
3133 .help
= "Cortex-R4 command group",
3135 .chain
= cortex_r4_exec_command_handlers
,
3137 COMMAND_REGISTRATION_DONE
3140 struct target_type cortexr4_target
= {
3141 .name
= "cortex_r4",
3143 .poll
= cortex_a_poll
,
3144 .arch_state
= armv7a_arch_state
,
3146 .halt
= cortex_a_halt
,
3147 .resume
= cortex_a_resume
,
3148 .step
= cortex_a_step
,
3150 .assert_reset
= cortex_a_assert_reset
,
3151 .deassert_reset
= cortex_a_deassert_reset
,
3153 /* REVISIT allow exporting VFP3 registers ... */
3154 .get_gdb_arch
= arm_get_gdb_arch
,
3155 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3157 .read_memory
= cortex_a_read_phys_memory
,
3158 .write_memory
= cortex_a_write_phys_memory
,
3160 .checksum_memory
= arm_checksum_memory
,
3161 .blank_check_memory
= arm_blank_check_memory
,
3163 .run_algorithm
= armv4_5_run_algorithm
,
3165 .add_breakpoint
= cortex_a_add_breakpoint
,
3166 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3167 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3168 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3169 .add_watchpoint
= NULL
,
3170 .remove_watchpoint
= NULL
,
3172 .commands
= cortex_r4_command_handlers
,
3173 .target_create
= cortex_r4_target_create
,
3174 .target_jim_configure
= adiv5_jim_configure
,
3175 .init_target
= cortex_a_init_target
,
3176 .examine
= cortex_a_examine
,
3177 .deinit_target
= cortex_a_deinit_target
,