src/target/board/dm355evm.cfg

   1 #
   2 # DM355 EVM board
   3 #   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
   4 #   http://c6000.spectrumdigital.com/evmdm355/
   5
   6 source [find target/ti_dm355.cfg]
   7
   8 reset_config trst_and_srst separate
   9
  10 # NOTE:  disable or replace this call to dm355evm_init if you're
  11 # debugging new UBL code from SRAM.
  12 $_TARGETNAME configure -event reset-init { dm355evm_init }
  13
  14 #
  15 # This post-reset init is called when the MMU isn't active, all IRQs
  16 # are disabled, etc.  It should do most of what a UBL does, except for
  17 # loading code (like U-Boot) into DRAM and running it.
  18 #
  19 proc dm355evm_init {} {
  20         global dm355
  21
  22         puts "Initialize DM355 EVM board"
  23
  24         # CLKIN = 24 MHz ... can't talk quickly to ARM yet
  25         jtag_khz 1500
  26
  27         ########################
  28         # PLL1          = 432 MHz (/8, x144)
  29         # ...SYSCLK1    = 216 MHz (/2)  ... ARM, MJCP
  30         # ...SYSCLK2    = 108 MHz (/4)  ... Peripherals
  31         # ...SYSCLK3    = 27  MHz (/16) ... VPBE, DAC
  32         # ...SYSCLK4    = 108 MHz (/4)  ... VPSS
  33         #       pll1.{prediv,div1,div2} are fixed
  34         #       pll1.postdiv set in MISC (for *this* speed grade)
  35
  36         set addr [dict get $dm355 pllc1]
  37         set pll_divs [dict create]
  38         dict set pll_divs div3 16
  39         dict set pll_divs div4 8
  40         pll_setup $addr 144 $pll_divs
  41
  42         # ARM is now running at 216 MHz, so JTAG can go faster
  43         jtag_khz 20000
  44
  45         ########################
  46         # PLL2          = 342 MHz (/8, x114)
  47         # ....SYSCLK1   = 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock
  48         #       pll2.{postdiv,div1} are fixed
  49
  50         set addr [dict get $dm355 pllc2]
  51         set pll_divs [dict create]
  52         dict set pll_divs prediv 8
  53         pll_setup $addr 114 $pll_divs
  54
  55         ########################
  56         # PINMUX
  57
  58         # All Video Inputs
  59         davinci_pinmux $dm355 0 0x00007f55
  60         # All Video Outputs
  61         davinci_pinmux $dm355 1 0x00145555
  62         # EMIFA (NOTE: more could be set up for use as GPIOs)
  63         davinci_pinmux $dm355 2 0x00000c08
  64         # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
  65         davinci_pinmux $dm355 3 0x1bff55ff
  66         # MMC/SD0 instead of MS; SPI0
  67         davinci_pinmux $dm355 4 0x00000000
  68
  69         ########################
  70         # PSC setup (minimal)
  71
  72         # DDR EMIF/13, AEMIF/14, UART0/19
  73         psc_enable 13
  74         psc_enable 14
  75         psc_enable 19
  76         psc_go
  77
  78         ########################
  79         # DDR2 EMIF
  80
  81         # FIXME setup
  82
  83         ########################
  84         # ASYNC EMIF
  85
  86         set addr [dict get $dm355 a_emif]
  87
  88         # slow/pessimistic timings
  89         set nand_timings 0x40400204
  90         # fast (25% faster page reads)
  91         #set nand_timings 0x0400008c
  92
  93         # AWCCR
  94         mww [expr $addr + 0x04] 0xff
  95         # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
  96         mww [expr $addr + 0x10] $nand_timings
  97         # CS1 == dm9000 Ethernet
  98         mww [expr $addr + 0x14] 0x00a00505
  99         # NANDFCR -- only CS0 has NAND
 100         mww [expr $addr + 0x60] 0x01
 101
 102         ########################
 103         # UART0
 104
 105         # FIXME setup
 106 }
 107
 108 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
 109 #
 110 # NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
 111 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 112 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 113 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
 114 nand device davinci 0 0x02000000 hwecc4 0x01e10000
 115 nand device davinci 0 0x02004000 hwecc4 0x01e10000
 116
 117 # FIXME
 118 #  - support writing UBL with its header (new layout only with new ROMs)
 119 #  - support writing ABL/U-Boot with its header (new layout)