aarch64: add basic Aarch32 support
[openocd.git] / src / target / armv8_opcodes.h
1 /*
2 * Copyright (C) 2015 by pierrr kuo
3 * vichy.kuo@gmail.com
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15 #ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
16 #define OPENOCD_TARGET_ARMV8_OPCODES_H
17
18 #include "arm_opcodes.h"
19
20 /* ARM V8 Move from system register to general purpose register
21 * R = 1: SPSR R = 0: CPSR
22 * Rn: target register
23 */
24 #define SYSTEM_CUREL 0b1100001000010010
25 #define SYSTEM_CUREL_MASK 0xC0
26 #define SYSTEM_CUREL_SHIFT 6
27 #define SYSTEM_CUREL_EL0 0x0
28 #define SYSTEM_CUREL_EL1 0x1
29 #define SYSTEM_CUREL_EL2 0x2
30 #define SYSTEM_CUREL_EL3 0x3
31 #define SYSTEM_CUREL_NONCH 0xF
32 #define SYSTEM_AARCH64 0x1
33
34 #define SYSTEM_AAR64_MODE_EL0t 0x0
35 #define SYSTEM_AAR64_MODE_EL1t 0x4
36 #define SYSTEM_AAR64_MODE_EL1h 0x5
37 #define SYSTEM_AAR64_MODE_EL2t 0x8
38 #define SYSTEM_AAR64_MODE_EL2h 0x9
39 #define SYSTEM_AAR64_MODE_EL3t 0xC
40 #define SYSTEM_AAR64_MODE_EL3h 0xd
41
42 #define SYSTEM_DAIF 0b1101101000010001
43 #define SYSTEM_DAIF_MASK 0x3C0
44 #define SYSTEM_DAIF_SHIFT 6
45
46 #define SYSTEM_ELR_EL1 0b1100001000000001
47 #define SYSTEM_ELR_EL2 0b1110001000000001
48 #define SYSTEM_ELR_EL3 0b1111001000000001
49
50 #define SYSTEM_FPCR 0b1101101000100000
51 #define SYSTEM_FPSR 0b1101101000100001
52 #define SYSTEM_DAIF 0b1101101000010001
53 #define SYSTEM_NZCV 0b1101101000010000
54 #define SYSTEM_SP_EL0 0b1100001000001000
55 #define SYSTEM_SP_EL1 0b1110001000001000
56 #define SYSTEM_SP_EL2 0b1111001000001000
57 #define SYSTEM_SP_SEL 0b1100001000010000
58 #define SYSTEM_SPSR_ABT 0b1110001000011001
59 #define SYSTEM_SPSR_FIQ 0b1110001000011011
60 #define SYSTEM_SPSR_IRQ 0b1110001000011000
61 #define SYSTEM_SPSR_UND 0b1110001000011010
62
63 #define SYSTEM_SPSR_EL1 0b1100001000000000
64 #define SYSTEM_SPSR_EL2 0b1110001000000000
65 #define SYSTEM_SPSR_EL3 0b1111001000000000
66
67 #define SYSTEM_ISR_EL1 0b1100011000001000
68
69
70 #define SYSTEM_DBG_DSPSR_EL0 0b1101101000101000
71 #define SYSTEM_DBG_DLR_EL0 0b1101101000101001
72 #define SYSTEM_DBG_DTRRX_EL0 0b1001100000101000
73 #define SYSTEM_DBG_DTRTX_EL0 0b1001100000101000
74 #define SYSTEM_DBG_DBGDTR_EL0 0b1001100000100000
75
76 #define SYSTEM_CCSIDR 0b1100100000000000
77 #define SYSTEM_CLIDR 0b1100100000000001
78 #define SYSTEM_CSSELR 0b1101000000000000
79 #define SYSTEM_CTYPE 0b1101100000000001
80
81 #define SYSTEM_DCCISW 0b0100001111110010
82 #define SYSTEM_DCCSW 0b0100001111010010
83 #define SYSTEM_ICIVAU 0b0101101110101001
84 #define SYSTEM_DCCVAU 0b0101101111011001
85 #define SYSTEM_DCCIVAC 0b0101101111110001
86
87 #define SYSTEM_MPIDR 0b1100000000000101
88
89 #define SYSTEM_TCR_EL1 0b1100000100000010
90 #define SYSTEM_TCR_EL2 0b1110000100000010
91 #define SYSTEM_TCR_EL3 0b1111000100000010
92
93 #define SYSTEM_TTBR0_EL1 0b1100000100000000
94 #define SYSTEM_TTBR0_EL2 0b1110000100000000
95 #define SYSTEM_TTBR0_EL3 0b1111000100000000
96 #define SYSTEM_TTBR1_EL1 0b1100000100000001
97
98 #define ARMV8_MRS_DSPSR(Rt) (0xd53b4500 | (Rt))
99 #define ARMV8_MSR_DSPSR(Rt) (0xd51b4500 | (Rt))
100 #define ARMV8_MRS_DLR(Rt) (0xd53b4520 | (Rt))
101 #define ARMV8_MSR_DLR(Rt) (0xd51b4520 | (Rt))
102
103 /* T32 ITR format */
104 #define T32_FMTITR(instr) (((instr & 0x0000FFFF) << 16) | ((instr & 0xFFFF0000) >> 16))
105
106 /* T32 instruction to access coprocessor registers */
107 #define ARMV8_MCR_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MCR(cp, opc1, Rt, CRn, CRm, opc2)
108 #define ARMV8_MRC_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MRC(cp, opc1, Rt, CRn, CRm, opc2)
109
110 /* T32 instructions to access DSPSR and DLR */
111 #define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt)
112 #define ARMV8_MCR_DSPSR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, Rt)
113 #define ARMV8_MRC_DLR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt)
114 #define ARMV8_MCR_DLR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt)
115
116 #define ARMV8_DCPS1(IM) (0xd4a00001 | (((IM) & 0xFFFF) << 5))
117 #define ARMV8_DCPS2(IM) (0xd4a00002 | (((IM) & 0xFFFF) << 5))
118 #define ARMV8_DCPS3(IM) (0xd4a00003 | (((IM) & 0xFFFF) << 5))
119
120 #define ARMV8_DSB_SY 0xd5033F9F
121 #define ARMV8_DSB_SY_T1 0xf3bf8f4f
122
123 #define ARMV8_MRS(System, Rt) (0xd5300000 | ((System) << 5) | (Rt))
124 /* ARM V8 Move to system register. */
125 #define ARMV8_MSR_GP(System, Rt) \
126 (0xd5100000 | ((System) << 5) | (Rt))
127 /* ARM V8 Move immediate to process state field. */
128 #define ARMV8_MSR_IM(Op1, CRm, Op2) \
129 (0xd500401f | ((Op1) << 16) | ((CRm) << 8) | ((Op2) << 5))
130
131 #define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
132 #define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
133
134 #define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
135 #define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
136 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
137 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
138
139 #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
140
141 enum armv8_opcode {
142 READ_REG_CLIDR,
143 READ_REG_CSSELR,
144 READ_REG_CCSIDR,
145 WRITE_REG_CSSELR,
146 READ_REG_MPIDR,
147 READ_REG_DTRRX,
148 WRITE_REG_DTRTX,
149 WRITE_REG_DSPSR,
150 READ_REG_DSPSR,
151 ARMV8_OPC_DSB_SY,
152 ARMV8_OPC_NUM,
153 };
154
155 extern uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode);
156 extern void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64);
157
158 #endif /* OPENOCD_TARGET_ARMV8_OPCODES_H */