aarch64: fix debug entry from EL0
[openocd.git] / src / target / armv8_dpm.h
1 /*
2 * Copyright (C) 2009 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #ifndef OPENOCD_TARGET_ARMV8_DPM_H
16 #define OPENOCD_TARGET_ARMV8_DPM_H
17
18 #include "arm_dpm.h"
19
20 /* forward-declare struct armv8_common */
21 struct armv8_common;
22
23 /**
24 * This wraps an implementation of DPM primitives. Each interface
25 * provider supplies a structure like this, which is the glue between
26 * upper level code and the lower level hardware access.
27 *
28 * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
29 * support for CPU register access.
30 */
31 int armv8_dpm_setup(struct arm_dpm *dpm);
32 int armv8_dpm_initialize(struct arm_dpm *dpm);
33
34 int armv8_dpm_read_current_registers(struct arm_dpm *);
35 int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
36
37
38 int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
39
40 void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
41
42 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
43 * Not all v7 bits are valid in v6.
44 */
45 #define DSCR_DEBUG_STATUS_MASK (0x1F << 0)
46 #define DSCR_ERR (0x1 << 6)
47 #define DSCR_SYS_ERROR_PEND (0x1 << 7)
48 #define DSCR_CUR_EL (0x3 << 8)
49 #define DSCR_EL_STATUS_MASK (0xF << 10)
50 #define DSCR_HDE (0x1 << 14)
51 #define DSCR_SDD (0x1 << 16)
52 #define DSCR_NON_SECURE (0x1 << 18)
53 #define DSCR_MA (0x1 << 20)
54 #define DSCR_TDA (0x1 << 21)
55 #define DSCR_INTDIS_MASK (0x3 << 22)
56 #define DSCR_ITE (0x1 << 24)
57 #define DSCR_PIPE_ADVANCE (0x1 << 25)
58 #define DSCR_TXU (0x1 << 26)
59 #define DSCR_RTO (0x1 << 27) /* bit 28 is reserved */
60 #define DSCR_ITO (0x1 << 28)
61 #define DSCR_DTR_TX_FULL (0x1 << 29)
62 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
63
64
65
66 /* Methods of entry into debug mode */
67 #define DSCRV8_ENTRY_NON_DEBUG (0x2)
68 #define DSCRV8_ENTRY_RESTARTING (0x1)
69 #define DSCRV8_ENTRY_BKPT (0x7)
70 #define DSCRV8_ENTRY_EXT_DEBUG (0x13)
71 #define DSCRV8_ENTRY_HALT_STEP_NORMAL (0x1B)
72 #define DSCRV8_ENTRY_HALT_STEP_EXECLU (0x1F)
73 #define DSCRV8_ENTRY_OS_UNLOCK (0x23)
74 #define DSCRV8_ENTRY_RESET_CATCH (0x27)
75 #define DSCRV8_ENTRY_WATCHPOINT (0x2B)
76 #define DSCRV8_ENTRY_HLT (0x2F)
77 #define DSCRV8_ENTRY_SW_ACCESS_DBG (0x33)
78 #define DSCRV8_ENTRY_EXCEPTION_CATCH (0x37)
79 #define DSCRV8_ENTRY_HALT_STEP (0x3B)
80 #define DSCRV8_HALT_MASK (0x3C)
81
82 /*DRCR registers*/
83 #define DRCR_CSE (1 << 2)
84 #define DRCR_CSPA (1 << 3)
85 #define DRCR_CBRRQ (1 << 4)
86
87
88 /* DTR modes */
89 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
90 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
91 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
92
93
94 /* DRCR (debug run control register) bits */
95 #define DRCR_HALT (1 << 0)
96 #define DRCR_RESTART (1 << 1)
97 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
98
99 /* PRSR (processor debug status register) bits */
100 #define PRSR_PU (1 << 0)
101 #define PRSR_SPD (1 << 1)
102 #define PRSR_RESET (1 << 2)
103 #define PRSR_SR (1 << 3)
104 #define PRSR_HALT (1 << 4)
105 #define PRSR_OSLK (1 << 5)
106 #define PRSR_DLK (1 << 6)
107 #define PRSR_EDAD (1 << 7)
108 #define PRSR_SDAD (1 << 8)
109 #define PRSR_EPMAD (1 << 9)
110 #define PRSR_SPMAD (1 << 10)
111 #define PRSR_SDR (1 << 11)
112
113 /* PRCR (processor debug control register) bits */
114 #define PRCR_CORENPDRQ (1 << 0)
115 #define PRCR_CWRR (1 << 2)
116 #define PRCR_COREPURQ (1 << 3)
117
118 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
119 void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore);
120 enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);
121
122 #endif /* OPENOCD_TARGET_ARM_DPM_H */