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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / target / armv8_dpm.c
1 /*
2 * Copyright (C) 2009 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
19
20 #include "arm.h"
21 #include "armv8.h"
22 #include "armv8_dpm.h"
23 #include <jtag/jtag.h>
24 #include "register.h"
25 #include "breakpoints.h"
26 #include "target_type.h"
27 #include "armv8_opcodes.h"
28
29 #include "helper/time_support.h"
30
31 /* T32 ITR format */
32 #define T32_FMTITR(instr) (((instr & 0x0000FFFF) << 16) | ((instr & 0xFFFF0000) >> 16))
33
34 /**
35 * @file
36 * Implements various ARM DPM operations using architectural debug registers.
37 * These routines layer over core-specific communication methods to cope with
38 * implementation differences between cores like ARM1136 and Cortex-A8.
39 *
40 * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
41 * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
42 * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations
43 * are abstracted through internal programming interfaces to share code and
44 * to minimize needless differences in debug behavior between cores.
45 */
46
47 /**
48 * Get core state from EDSCR, without necessity to retrieve CPSR
49 */
50 enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
51 {
52 int el = (dpm->dscr >> 8) & 0x3;
53 int rw = (dpm->dscr >> 10) & 0xF;
54
55 dpm->last_el = el;
56
57 /* In Debug state, each bit gives the current Execution state of each EL */
58 if ((rw >> el) & 0b1)
59 return ARM_STATE_AARCH64;
60
61 return ARM_STATE_ARM;
62 }
63
64 /*----------------------------------------------------------------------*/
65
66 static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
67 {
68 return mem_ap_write_u32(armv8->debug_ap,
69 armv8->debug_base + CPUV8_DBG_DTRRX, data);
70 }
71
72 static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
73 {
74 int ret;
75 ret = mem_ap_write_u32(armv8->debug_ap,
76 armv8->debug_base + CPUV8_DBG_DTRRX, data);
77 if (ret == ERROR_OK)
78 ret = mem_ap_write_u32(armv8->debug_ap,
79 armv8->debug_base + CPUV8_DBG_DTRTX, data >> 32);
80 return ret;
81 }
82
83 static int dpmv8_read_dcc(struct armv8_common *armv8, uint32_t *data,
84 uint32_t *dscr_p)
85 {
86 uint32_t dscr = DSCR_ITE;
87 int retval;
88
89 if (dscr_p)
90 dscr = *dscr_p;
91
92 /* Wait for DTRRXfull */
93 long long then = timeval_ms();
94 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
95 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
96 armv8->debug_base + CPUV8_DBG_DSCR,
97 &dscr);
98 if (retval != ERROR_OK)
99 return retval;
100 if (timeval_ms() > then + 1000) {
101 LOG_ERROR("Timeout waiting for read dcc");
102 return ERROR_FAIL;
103 }
104 }
105
106 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
107 armv8->debug_base + CPUV8_DBG_DTRTX,
108 data);
109 if (retval != ERROR_OK)
110 return retval;
111
112 if (dscr_p)
113 *dscr_p = dscr;
114
115 return retval;
116 }
117
118 static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
119 uint32_t *dscr_p)
120 {
121 uint32_t dscr = DSCR_ITE;
122 uint32_t higher;
123 int retval;
124
125 if (dscr_p)
126 dscr = *dscr_p;
127
128 /* Wait for DTRRXfull */
129 long long then = timeval_ms();
130 while ((dscr & DSCR_DTR_TX_FULL) == 0) {
131 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
132 armv8->debug_base + CPUV8_DBG_DSCR,
133 &dscr);
134 if (retval != ERROR_OK)
135 return retval;
136 if (timeval_ms() > then + 1000) {
137 LOG_ERROR("Timeout waiting for DTR_TX_FULL, dscr = 0x%08" PRIx32, dscr);
138 return ERROR_FAIL;
139 }
140 }
141
142 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
143 armv8->debug_base + CPUV8_DBG_DTRTX,
144 (uint32_t *)data);
145 if (retval != ERROR_OK)
146 return retval;
147
148 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
149 armv8->debug_base + CPUV8_DBG_DTRRX,
150 &higher);
151 if (retval != ERROR_OK)
152 return retval;
153
154 *data = *(uint32_t *)data | (uint64_t)higher << 32;
155
156 if (dscr_p)
157 *dscr_p = dscr;
158
159 return retval;
160 }
161
162 static int dpmv8_dpm_prepare(struct arm_dpm *dpm)
163 {
164 struct armv8_common *armv8 = dpm->arm->arch_info;
165 uint32_t dscr;
166 int retval;
167
168 /* set up invariant: ITE is set after ever DPM operation */
169 long long then = timeval_ms();
170 for (;; ) {
171 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
172 armv8->debug_base + CPUV8_DBG_DSCR,
173 &dscr);
174 if (retval != ERROR_OK)
175 return retval;
176 if ((dscr & DSCR_ITE) != 0)
177 break;
178 if (timeval_ms() > then + 1000) {
179 LOG_ERROR("Timeout waiting for dpm prepare");
180 return ERROR_FAIL;
181 }
182 }
183
184 /* update the stored copy of dscr */
185 dpm->dscr = dscr;
186
187 /* this "should never happen" ... */
188 if (dscr & DSCR_DTR_RX_FULL) {
189 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
190 /* Clear DCCRX */
191 retval = mem_ap_read_u32(armv8->debug_ap,
192 armv8->debug_base + CPUV8_DBG_DTRRX, &dscr);
193 if (retval != ERROR_OK)
194 return retval;
195 }
196
197 return retval;
198 }
199
200 static int dpmv8_dpm_finish(struct arm_dpm *dpm)
201 {
202 /* REVISIT what could be done here? */
203 return ERROR_OK;
204 }
205
206 static int dpmv8_exec_opcode(struct arm_dpm *dpm,
207 uint32_t opcode, uint32_t *p_dscr)
208 {
209 struct armv8_common *armv8 = dpm->arm->arch_info;
210 uint32_t dscr = dpm->dscr;
211 int retval;
212
213 if (p_dscr)
214 dscr = *p_dscr;
215
216 /* Wait for InstrCompl bit to be set */
217 long long then = timeval_ms();
218 while ((dscr & DSCR_ITE) == 0) {
219 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
220 armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
221 if (retval != ERROR_OK) {
222 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
223 return retval;
224 }
225 if (timeval_ms() > then + 1000) {
226 LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
227 return ERROR_FAIL;
228 }
229 }
230
231 if (armv8_dpm_get_core_state(dpm) != ARM_STATE_AARCH64)
232 opcode = T32_FMTITR(opcode);
233
234 retval = mem_ap_write_u32(armv8->debug_ap,
235 armv8->debug_base + CPUV8_DBG_ITR, opcode);
236 if (retval != ERROR_OK)
237 return retval;
238
239 then = timeval_ms();
240 do {
241 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
242 armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
243 if (retval != ERROR_OK) {
244 LOG_ERROR("Could not read DSCR register");
245 return retval;
246 }
247 if (timeval_ms() > then + 1000) {
248 LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
249 return ERROR_FAIL;
250 }
251 } while ((dscr & DSCR_ITE) == 0); /* Wait for InstrCompl bit to be set */
252
253 /* update dscr and el after each command execution */
254 dpm->dscr = dscr;
255 if (dpm->last_el != ((dscr >> 8) & 3))
256 LOG_DEBUG("EL %i -> %i", dpm->last_el, (dscr >> 8) & 3);
257 dpm->last_el = (dscr >> 8) & 3;
258
259 if (dscr & DSCR_ERR) {
260 LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
261 armv8_dpm_handle_exception(dpm, true);
262 retval = ERROR_FAIL;
263 }
264
265 if (p_dscr)
266 *p_dscr = dscr;
267
268 return retval;
269 }
270
271 static int dpmv8_instr_execute(struct arm_dpm *dpm, uint32_t opcode)
272 {
273 return dpmv8_exec_opcode(dpm, opcode, NULL);
274 }
275
276 static int dpmv8_instr_write_data_dcc(struct arm_dpm *dpm,
277 uint32_t opcode, uint32_t data)
278 {
279 struct armv8_common *armv8 = dpm->arm->arch_info;
280 int retval;
281
282 retval = dpmv8_write_dcc(armv8, data);
283 if (retval != ERROR_OK)
284 return retval;
285
286 return dpmv8_exec_opcode(dpm, opcode, 0);
287 }
288
289 static int dpmv8_instr_write_data_dcc_64(struct arm_dpm *dpm,
290 uint32_t opcode, uint64_t data)
291 {
292 struct armv8_common *armv8 = dpm->arm->arch_info;
293 int retval;
294
295 retval = dpmv8_write_dcc_64(armv8, data);
296 if (retval != ERROR_OK)
297 return retval;
298
299 return dpmv8_exec_opcode(dpm, opcode, 0);
300 }
301
302 static int dpmv8_instr_write_data_r0(struct arm_dpm *dpm,
303 uint32_t opcode, uint32_t data)
304 {
305 struct armv8_common *armv8 = dpm->arm->arch_info;
306 uint32_t dscr = DSCR_ITE;
307 int retval;
308
309 retval = dpmv8_write_dcc(armv8, data);
310 if (retval != ERROR_OK)
311 return retval;
312
313 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, READ_REG_DTRRX), &dscr);
314 if (retval != ERROR_OK)
315 return retval;
316
317 /* then the opcode, taking data from R0 */
318 return dpmv8_exec_opcode(dpm, opcode, &dscr);
319 }
320
321 static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm,
322 uint32_t opcode, uint64_t data)
323 {
324 struct armv8_common *armv8 = dpm->arm->arch_info;
325 int retval;
326
327 if (dpm->arm->core_state != ARM_STATE_AARCH64)
328 return dpmv8_instr_write_data_r0(dpm, opcode, data);
329
330 /* transfer data from DCC to R0 */
331 retval = dpmv8_write_dcc_64(armv8, data);
332 if (retval == ERROR_OK)
333 retval = dpmv8_exec_opcode(dpm, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
334
335 /* then the opcode, taking data from R0 */
336 if (retval == ERROR_OK)
337 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
338
339 return retval;
340 }
341
342 static int dpmv8_instr_cpsr_sync(struct arm_dpm *dpm)
343 {
344 int retval;
345 struct armv8_common *armv8 = dpm->arm->arch_info;
346
347 /* "Prefetch flush" after modifying execution status in CPSR */
348 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_DSB_SY), &dpm->dscr);
349 if (retval == ERROR_OK)
350 dpmv8_exec_opcode(dpm, armv8_opcode(armv8, ARMV8_OPC_ISB_SY), &dpm->dscr);
351 return retval;
352 }
353
354 static int dpmv8_instr_read_data_dcc(struct arm_dpm *dpm,
355 uint32_t opcode, uint32_t *data)
356 {
357 struct armv8_common *armv8 = dpm->arm->arch_info;
358 int retval;
359
360 /* the opcode, writing data to DCC */
361 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
362 if (retval != ERROR_OK)
363 return retval;
364
365 return dpmv8_read_dcc(armv8, data, &dpm->dscr);
366 }
367
368 static int dpmv8_instr_read_data_dcc_64(struct arm_dpm *dpm,
369 uint32_t opcode, uint64_t *data)
370 {
371 struct armv8_common *armv8 = dpm->arm->arch_info;
372 int retval;
373
374 /* the opcode, writing data to DCC */
375 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
376 if (retval != ERROR_OK)
377 return retval;
378
379 return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
380 }
381
382 static int dpmv8_instr_read_data_r0(struct arm_dpm *dpm,
383 uint32_t opcode, uint32_t *data)
384 {
385 struct armv8_common *armv8 = dpm->arm->arch_info;
386 int retval;
387
388 /* the opcode, writing data to R0 */
389 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
390 if (retval != ERROR_OK)
391 return retval;
392
393 /* write R0 to DCC */
394 retval = dpmv8_exec_opcode(dpm, armv8_opcode(armv8, WRITE_REG_DTRTX), &dpm->dscr);
395 if (retval != ERROR_OK)
396 return retval;
397
398 return dpmv8_read_dcc(armv8, data, &dpm->dscr);
399 }
400
401 static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
402 uint32_t opcode, uint64_t *data)
403 {
404 struct armv8_common *armv8 = dpm->arm->arch_info;
405 int retval;
406
407 if (dpm->arm->core_state != ARM_STATE_AARCH64) {
408 uint32_t tmp;
409 retval = dpmv8_instr_read_data_r0(dpm, opcode, &tmp);
410 if (retval == ERROR_OK)
411 *data = tmp;
412 return retval;
413 }
414
415 /* the opcode, writing data to R0 */
416 retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr);
417 if (retval != ERROR_OK)
418 return retval;
419
420 /* write R0 to DCC */
421 retval = dpmv8_exec_opcode(dpm, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dpm->dscr);
422 if (retval != ERROR_OK)
423 return retval;
424
425 return dpmv8_read_dcc_64(armv8, data, &dpm->dscr);
426 }
427
428 #if 0
429 static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
430 target_addr_t addr, uint32_t control)
431 {
432 struct armv8_common *armv8 = dpm->arm->arch_info;
433 uint32_t vr = armv8->debug_base;
434 uint32_t cr = armv8->debug_base;
435 int retval;
436
437 switch (index_t) {
438 case 0 ... 15: /* breakpoints */
439 vr += CPUV8_DBG_BVR_BASE;
440 cr += CPUV8_DBG_BCR_BASE;
441 break;
442 case 16 ... 31: /* watchpoints */
443 vr += CPUV8_DBG_WVR_BASE;
444 cr += CPUV8_DBG_WCR_BASE;
445 index_t -= 16;
446 break;
447 default:
448 return ERROR_FAIL;
449 }
450 vr += 16 * index_t;
451 cr += 16 * index_t;
452
453 LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
454 (unsigned) vr, (unsigned) cr);
455
456 retval = mem_ap_write_atomic_u32(armv8->debug_ap, vr, addr);
457 if (retval != ERROR_OK)
458 return retval;
459 return mem_ap_write_atomic_u32(armv8->debug_ap, cr, control);
460 }
461 #endif
462
463 static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
464 {
465 struct armv8_common *armv8 = dpm->arm->arch_info;
466 uint32_t cr;
467
468 switch (index_t) {
469 case 0 ... 15:
470 cr = armv8->debug_base + CPUV8_DBG_BCR_BASE;
471 break;
472 case 16 ... 31:
473 cr = armv8->debug_base + CPUV8_DBG_WCR_BASE;
474 index_t -= 16;
475 break;
476 default:
477 return ERROR_FAIL;
478 }
479 cr += 16 * index_t;
480
481 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
482
483 /* clear control register */
484 return mem_ap_write_atomic_u32(armv8->debug_ap, cr, 0);
485 }
486
487 /*
488 * Coprocessor support
489 */
490
491 /* Read coprocessor */
492 static int dpmv8_mrc(struct target *target, int cpnum,
493 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
494 uint32_t *value)
495 {
496 struct arm *arm = target_to_arm(target);
497 struct arm_dpm *dpm = arm->dpm;
498 int retval;
499
500 retval = dpm->prepare(dpm);
501 if (retval != ERROR_OK)
502 return retval;
503
504 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
505 (int) op1, (int) CRn,
506 (int) CRm, (int) op2);
507
508 /* read coprocessor register into R0; return via DCC */
509 retval = dpm->instr_read_data_r0(dpm,
510 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
511 value);
512
513 /* (void) */ dpm->finish(dpm);
514 return retval;
515 }
516
517 static int dpmv8_mcr(struct target *target, int cpnum,
518 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
519 uint32_t value)
520 {
521 struct arm *arm = target_to_arm(target);
522 struct arm_dpm *dpm = arm->dpm;
523 int retval;
524
525 retval = dpm->prepare(dpm);
526 if (retval != ERROR_OK)
527 return retval;
528
529 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
530 (int) op1, (int) CRn,
531 (int) CRm, (int) op2);
532
533 /* read DCC into r0; then write coprocessor register from R0 */
534 retval = dpm->instr_write_data_r0(dpm,
535 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
536 value);
537
538 /* (void) */ dpm->finish(dpm);
539 return retval;
540 }
541
542 /*----------------------------------------------------------------------*/
543
544 /*
545 * Register access utilities
546 */
547
548 int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
549 {
550 struct armv8_common *armv8 = (struct armv8_common *)dpm->arm->arch_info;
551 int retval = ERROR_OK;
552 unsigned int target_el;
553 enum arm_state core_state;
554 uint32_t cpsr;
555
556 /* restore previous mode */
557 if (mode == ARM_MODE_ANY) {
558 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
559
560 LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
561
562 } else {
563 LOG_DEBUG("setting mode 0x%"PRIx32, mode);
564 cpsr = mode;
565 }
566
567 switch (cpsr & 0x1f) {
568 /* aarch32 modes */
569 case ARM_MODE_USR:
570 target_el = 0;
571 break;
572 case ARM_MODE_SVC:
573 case ARM_MODE_ABT:
574 case ARM_MODE_IRQ:
575 case ARM_MODE_FIQ:
576 case ARM_MODE_SYS:
577 target_el = 1;
578 break;
579 /*
580 * TODO: handle ARM_MODE_HYP
581 * case ARM_MODE_HYP:
582 * target_el = 2;
583 * break;
584 */
585 case ARM_MODE_MON:
586 target_el = 3;
587 break;
588 /* aarch64 modes */
589 default:
590 target_el = (cpsr >> 2) & 3;
591 }
592
593 if (target_el > SYSTEM_CUREL_EL3) {
594 LOG_ERROR("%s: Invalid target exception level %i", __func__, target_el);
595 return ERROR_FAIL;
596 }
597
598 LOG_DEBUG("target_el = %i, last_el = %i", target_el, dpm->last_el);
599 if (target_el > dpm->last_el) {
600 retval = dpm->instr_execute(dpm,
601 armv8_opcode(armv8, ARMV8_OPC_DCPS) | target_el);
602
603 /* DCPS clobbers registers just like an exception taken */
604 armv8_dpm_handle_exception(dpm, false);
605 } else {
606 core_state = armv8_dpm_get_core_state(dpm);
607 if (core_state != ARM_STATE_AARCH64) {
608 /* cannot do DRPS/ERET when already in EL0 */
609 if (dpm->last_el != 0) {
610 /* load SPSR with the desired mode and execute DRPS */
611 LOG_DEBUG("SPSR = 0x%08"PRIx32, cpsr);
612 retval = dpm->instr_write_data_r0(dpm,
613 ARMV8_MSR_GP_xPSR_T1(1, 0, 15), cpsr);
614 if (retval == ERROR_OK)
615 retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
616 }
617 } else {
618 /*
619 * need to execute multiple DRPS instructions until target_el
620 * is reached
621 */
622 while (retval == ERROR_OK && dpm->last_el != target_el) {
623 unsigned int cur_el = dpm->last_el;
624 retval = dpm->instr_execute(dpm, armv8_opcode(armv8, ARMV8_OPC_DRPS));
625 if (cur_el == dpm->last_el) {
626 LOG_INFO("Cannot reach EL %i, SPSR corrupted?", target_el);
627 break;
628 }
629 }
630 }
631
632 /* On executing DRPS, DSPSR and DLR become UNKNOWN, mark them as dirty */
633 dpm->arm->cpsr->dirty = true;
634 dpm->arm->pc->dirty = true;
635
636 /*
637 * re-evaluate the core state, we might be in Aarch32 state now
638 * we rely on dpm->dscr being up-to-date
639 */
640 core_state = armv8_dpm_get_core_state(dpm);
641 armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
642 armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
643 }
644
645 return retval;
646 }
647
648 /*
649 * Common register read, relies on armv8_select_reg_access() having been called.
650 */
651 static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
652 {
653 struct armv8_common *armv8 = dpm->arm->arch_info;
654 int retval = ERROR_FAIL;
655
656 if (r->size <= 64) {
657 uint64_t value_64;
658 retval = armv8->read_reg_u64(armv8, regnum, &value_64);
659
660 if (retval == ERROR_OK) {
661 r->valid = true;
662 r->dirty = false;
663 buf_set_u64(r->value, 0, r->size, value_64);
664 if (r->size == 64)
665 LOG_DEBUG("READ: %s, %16.8llx", r->name, (unsigned long long) value_64);
666 else
667 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned int) value_64);
668 }
669 } else if (r->size <= 128) {
670 uint64_t lvalue = 0, hvalue = 0;
671 retval = armv8->read_reg_u128(armv8, regnum, &lvalue, &hvalue);
672
673 if (retval == ERROR_OK) {
674 r->valid = true;
675 r->dirty = false;
676
677 buf_set_u64(r->value, 0, 64, lvalue);
678 buf_set_u64(r->value + 8, 0, r->size - 64, hvalue);
679
680 LOG_DEBUG("READ: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
681 LOG_DEBUG("READ: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
682 }
683 }
684 return retval;
685 }
686
687 /*
688 * Common register write, relies on armv8_select_reg_access() having been called.
689 */
690 static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
691 {
692 struct armv8_common *armv8 = dpm->arm->arch_info;
693 int retval = ERROR_FAIL;
694
695 if (r->size <= 64) {
696 uint64_t value_64;
697
698 value_64 = buf_get_u64(r->value, 0, r->size);
699 retval = armv8->write_reg_u64(armv8, regnum, value_64);
700
701 if (retval == ERROR_OK) {
702 r->dirty = false;
703 if (r->size == 64)
704 LOG_DEBUG("WRITE: %s, %16.8llx", r->name, (unsigned long long)value_64);
705 else
706 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned int)value_64);
707 }
708 } else if (r->size <= 128) {
709 uint64_t lvalue, hvalue;
710
711 lvalue = buf_get_u64(r->value, 0, 64);
712 hvalue = buf_get_u64(r->value + 8, 0, r->size - 64);
713 retval = armv8->write_reg_u128(armv8, regnum, lvalue, hvalue);
714
715 if (retval == ERROR_OK) {
716 r->dirty = false;
717
718 LOG_DEBUG("WRITE: %s, lvalue=%16.8llx", r->name, (unsigned long long) lvalue);
719 LOG_DEBUG("WRITE: %s, hvalue=%16.8llx", r->name, (unsigned long long) hvalue);
720 }
721 }
722
723 return retval;
724 }
725
726 /**
727 * Read basic registers of the the current context: R0 to R15, and CPSR;
728 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
729 * In normal operation this is called on entry to halting debug state,
730 * possibly after some other operations supporting restore of debug state
731 * or making sure the CPU is fully idle (drain write buffer, etc).
732 */
733 int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
734 {
735 struct arm *arm = dpm->arm;
736 struct armv8_common *armv8 = (struct armv8_common *)arm->arch_info;
737 struct reg_cache *cache;
738 struct reg *r;
739 uint32_t cpsr;
740 int retval;
741
742 retval = dpm->prepare(dpm);
743 if (retval != ERROR_OK)
744 return retval;
745
746 cache = arm->core_cache;
747
748 /* read R0 first (it's used for scratch), then CPSR */
749 r = cache->reg_list + ARMV8_R0;
750 if (!r->valid) {
751 retval = dpmv8_read_reg(dpm, r, ARMV8_R0);
752 if (retval != ERROR_OK)
753 goto fail;
754 }
755 r->dirty = true;
756
757 /* read R1, too, it will be clobbered during memory access */
758 r = cache->reg_list + ARMV8_R1;
759 if (!r->valid) {
760 retval = dpmv8_read_reg(dpm, r, ARMV8_R1);
761 if (retval != ERROR_OK)
762 goto fail;
763 }
764
765 /* read cpsr to r0 and get it back */
766 retval = dpm->instr_read_data_r0(dpm,
767 armv8_opcode(armv8, READ_REG_DSPSR), &cpsr);
768 if (retval != ERROR_OK)
769 goto fail;
770
771 /* update core mode and state */
772 armv8_set_cpsr(arm, cpsr);
773
774 for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
775 struct arm_reg *arm_reg;
776
777 r = armv8_reg_current(arm, i);
778 if (r->valid)
779 continue;
780
781 /* Skip reading FP-SIMD registers */
782 if (r->number >= ARMV8_V0 && r->number <= ARMV8_FPCR)
783 continue;
784
785 /*
786 * Only read registers that are available from the
787 * current EL (or core mode).
788 */
789 arm_reg = r->arch_info;
790 if (arm_reg->mode != ARM_MODE_ANY &&
791 dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
792 continue;
793
794 /* Special case: ARM_MODE_SYS has no SPSR at EL1 */
795 if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS)
796 continue;
797
798 retval = dpmv8_read_reg(dpm, r, i);
799 if (retval != ERROR_OK)
800 goto fail;
801
802 }
803
804 fail:
805 dpm->finish(dpm);
806 return retval;
807 }
808
809 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
810 * unless they're removed, or need updating because of single-stepping
811 * or running debugger code.
812 */
813 static int dpmv8_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
814 struct dpm_bpwp *xp, int *set_p)
815 {
816 int retval = ERROR_OK;
817 bool disable;
818
819 if (!set_p) {
820 if (!xp->dirty)
821 goto done;
822 xp->dirty = false;
823 /* removed or startup; we must disable it */
824 disable = true;
825 } else if (bpwp) {
826 if (!xp->dirty)
827 goto done;
828 /* disabled, but we must set it */
829 xp->dirty = disable = false;
830 *set_p = true;
831 } else {
832 if (!*set_p)
833 goto done;
834 /* set, but we must temporarily disable it */
835 xp->dirty = disable = true;
836 *set_p = false;
837 }
838
839 if (disable)
840 retval = dpm->bpwp_disable(dpm, xp->number);
841 else
842 retval = dpm->bpwp_enable(dpm, xp->number,
843 xp->address, xp->control);
844
845 if (retval != ERROR_OK)
846 LOG_ERROR("%s: can't %s HW %spoint %d",
847 disable ? "disable" : "enable",
848 target_name(dpm->arm->target),
849 (xp->number < 16) ? "break" : "watch",
850 xp->number & 0xf);
851 done:
852 return retval;
853 }
854
855 static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp);
856
857 /**
858 * Writes all modified core registers for all processor modes. In normal
859 * operation this is called on exit from halting debug state.
860 *
861 * @param dpm: represents the processor
862 * @param bpwp: true ensures breakpoints and watchpoints are set,
863 * false ensures they are cleared
864 */
865 int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
866 {
867 struct arm *arm = dpm->arm;
868 struct reg_cache *cache = arm->core_cache;
869 int retval;
870
871 retval = dpm->prepare(dpm);
872 if (retval != ERROR_OK)
873 goto done;
874
875 /* If we're managing hardware breakpoints for this core, enable
876 * or disable them as requested.
877 *
878 * REVISIT We don't yet manage them for ANY cores. Eventually
879 * we should be able to assume we handle them; but until then,
880 * cope with the hand-crafted breakpoint code.
881 */
882 if (arm->target->type->add_breakpoint == dpmv8_add_breakpoint) {
883 for (unsigned i = 0; i < dpm->nbp; i++) {
884 struct dpm_bp *dbp = dpm->dbp + i;
885 struct breakpoint *bp = dbp->bp;
886
887 retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
888 bp ? &bp->set : NULL);
889 if (retval != ERROR_OK)
890 goto done;
891 }
892 }
893
894 /* enable/disable watchpoints */
895 for (unsigned i = 0; i < dpm->nwp; i++) {
896 struct dpm_wp *dwp = dpm->dwp + i;
897 struct watchpoint *wp = dwp->wp;
898
899 retval = dpmv8_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
900 wp ? &wp->set : NULL);
901 if (retval != ERROR_OK)
902 goto done;
903 }
904
905 /* NOTE: writes to breakpoint and watchpoint registers might
906 * be queued, and need (efficient/batched) flushing later.
907 */
908
909 /* Restore original core mode and state */
910 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
911 if (retval != ERROR_OK)
912 goto done;
913
914 /* check everything except our scratch register R0 */
915 for (unsigned i = 1; i < cache->num_regs; i++) {
916 struct arm_reg *r;
917
918 /* skip PC and CPSR */
919 if (i == ARMV8_PC || i == ARMV8_xPSR)
920 continue;
921 /* skip invalid */
922 if (!cache->reg_list[i].valid)
923 continue;
924 /* skip non-dirty */
925 if (!cache->reg_list[i].dirty)
926 continue;
927
928 /* skip all registers not on the current EL */
929 r = cache->reg_list[i].arch_info;
930 if (r->mode != ARM_MODE_ANY &&
931 dpm->last_el != armv8_curel_from_core_mode(r->mode))
932 continue;
933
934 retval = dpmv8_write_reg(dpm, &cache->reg_list[i], i);
935 if (retval != ERROR_OK)
936 break;
937 }
938
939 /* flush CPSR and PC */
940 if (retval == ERROR_OK)
941 retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_xPSR], ARMV8_xPSR);
942 if (retval == ERROR_OK)
943 retval = dpmv8_write_reg(dpm, &cache->reg_list[ARMV8_PC], ARMV8_PC);
944 /* flush R0 -- it's *very* dirty by now */
945 if (retval == ERROR_OK)
946 retval = dpmv8_write_reg(dpm, &cache->reg_list[0], 0);
947 if (retval == ERROR_OK)
948 dpm->instr_cpsr_sync(dpm);
949 done:
950 dpm->finish(dpm);
951 return retval;
952 }
953
954 /*
955 * Standard ARM register accessors ... there are three methods
956 * in "struct arm", to support individual read/write and bulk read
957 * of registers.
958 */
959
960 static int armv8_dpm_read_core_reg(struct target *target, struct reg *r,
961 int regnum, enum arm_mode mode)
962 {
963 struct arm *arm = target_to_arm(target);
964 struct arm_dpm *dpm = target_to_arm(target)->dpm;
965 int retval;
966 int max = arm->core_cache->num_regs;
967
968 if (regnum < 0 || regnum >= max)
969 return ERROR_COMMAND_SYNTAX_ERROR;
970
971 /*
972 * REVISIT what happens if we try to read SPSR in a core mode
973 * which has no such register?
974 */
975 retval = dpm->prepare(dpm);
976 if (retval != ERROR_OK)
977 return retval;
978
979 retval = dpmv8_read_reg(dpm, r, regnum);
980 if (retval != ERROR_OK)
981 goto fail;
982
983 fail:
984 /* (void) */ dpm->finish(dpm);
985 return retval;
986 }
987
988 static int armv8_dpm_write_core_reg(struct target *target, struct reg *r,
989 int regnum, enum arm_mode mode, uint8_t *value)
990 {
991 struct arm *arm = target_to_arm(target);
992 struct arm_dpm *dpm = target_to_arm(target)->dpm;
993 int retval;
994 int max = arm->core_cache->num_regs;
995
996 if (regnum < 0 || regnum > max)
997 return ERROR_COMMAND_SYNTAX_ERROR;
998
999 /* REVISIT what happens if we try to write SPSR in a core mode
1000 * which has no such register?
1001 */
1002
1003 retval = dpm->prepare(dpm);
1004 if (retval != ERROR_OK)
1005 return retval;
1006
1007 retval = dpmv8_write_reg(dpm, r, regnum);
1008
1009 /* always clean up, regardless of error */
1010 dpm->finish(dpm);
1011
1012 return retval;
1013 }
1014
1015 static int armv8_dpm_full_context(struct target *target)
1016 {
1017 struct arm *arm = target_to_arm(target);
1018 struct arm_dpm *dpm = arm->dpm;
1019 struct reg_cache *cache = arm->core_cache;
1020 int retval;
1021 bool did_read;
1022
1023 retval = dpm->prepare(dpm);
1024 if (retval != ERROR_OK)
1025 goto done;
1026
1027 do {
1028 enum arm_mode mode = ARM_MODE_ANY;
1029
1030 did_read = false;
1031
1032 /* We "know" arm_dpm_read_current_registers() was called so
1033 * the unmapped registers (R0..R7, PC, AND CPSR) and some
1034 * view of R8..R14 are current. We also "know" oddities of
1035 * register mapping: special cases for R8..R12 and SPSR.
1036 *
1037 * Pick some mode with unread registers and read them all.
1038 * Repeat until done.
1039 */
1040 for (unsigned i = 0; i < cache->num_regs; i++) {
1041 struct arm_reg *r;
1042
1043 if (cache->reg_list[i].valid)
1044 continue;
1045 r = cache->reg_list[i].arch_info;
1046
1047 /* may need to pick a mode and set CPSR */
1048 if (!did_read) {
1049 did_read = true;
1050 mode = r->mode;
1051
1052 /* For regular (ARM_MODE_ANY) R8..R12
1053 * in case we've entered debug state
1054 * in FIQ mode we need to patch mode.
1055 */
1056 if (mode != ARM_MODE_ANY)
1057 retval = armv8_dpm_modeswitch(dpm, mode);
1058 else
1059 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_USR);
1060
1061 if (retval != ERROR_OK)
1062 goto done;
1063 }
1064 if (r->mode != mode)
1065 continue;
1066
1067 /* CPSR was read, so "R16" must mean SPSR */
1068 retval = dpmv8_read_reg(dpm,
1069 &cache->reg_list[i],
1070 (r->num == 16) ? 17 : r->num);
1071 if (retval != ERROR_OK)
1072 goto done;
1073 }
1074
1075 } while (did_read);
1076
1077 retval = armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
1078 /* (void) */ dpm->finish(dpm);
1079 done:
1080 return retval;
1081 }
1082
1083
1084 /*----------------------------------------------------------------------*/
1085
1086 /*
1087 * Breakpoint and Watchpoint support.
1088 *
1089 * Hardware {break,watch}points are usually left active, to minimize
1090 * debug entry/exit costs. When they are set or cleared, it's done in
1091 * batches. Also, DPM-conformant hardware can update debug registers
1092 * regardless of whether the CPU is running or halted ... though that
1093 * fact isn't currently leveraged.
1094 */
1095
1096 static int dpmv8_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
1097 uint32_t addr, uint32_t length)
1098 {
1099 uint32_t control;
1100
1101 control = (1 << 0) /* enable */
1102 | (3 << 1); /* both user and privileged access */
1103
1104 /* Match 1, 2, or all 4 byte addresses in this word.
1105 *
1106 * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP.
1107 * Support larger length, when addr is suitably aligned. In
1108 * particular, allow watchpoints on 8 byte "double" values.
1109 *
1110 * REVISIT allow watchpoints on unaligned 2-bit values; and on
1111 * v7 hardware, unaligned 4-byte ones too.
1112 */
1113 switch (length) {
1114 case 1:
1115 control |= (1 << (addr & 3)) << 5;
1116 break;
1117 case 2:
1118 /* require 2-byte alignment */
1119 if (!(addr & 1)) {
1120 control |= (3 << (addr & 2)) << 5;
1121 break;
1122 }
1123 /* FALL THROUGH */
1124 case 4:
1125 /* require 4-byte alignment */
1126 if (!(addr & 3)) {
1127 control |= 0xf << 5;
1128 break;
1129 }
1130 /* FALL THROUGH */
1131 default:
1132 LOG_ERROR("unsupported {break,watch}point length/alignment");
1133 return ERROR_COMMAND_SYNTAX_ERROR;
1134 }
1135
1136 /* other shared control bits:
1137 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
1138 * bit 20 == 0 ... not linked to a context ID
1139 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
1140 */
1141
1142 xp->address = addr & ~3;
1143 xp->control = control;
1144 xp->dirty = true;
1145
1146 LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
1147 xp->address, control, xp->number);
1148
1149 /* hardware is updated in write_dirty_registers() */
1150 return ERROR_OK;
1151 }
1152
1153 static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp)
1154 {
1155 struct arm *arm = target_to_arm(target);
1156 struct arm_dpm *dpm = arm->dpm;
1157 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1158
1159 if (bp->length < 2)
1160 return ERROR_COMMAND_SYNTAX_ERROR;
1161 if (!dpm->bpwp_enable)
1162 return retval;
1163
1164 /* FIXME we need a generic solution for software breakpoints. */
1165 if (bp->type == BKPT_SOFT)
1166 LOG_DEBUG("using HW bkpt, not SW...");
1167
1168 for (unsigned i = 0; i < dpm->nbp; i++) {
1169 if (!dpm->dbp[i].bp) {
1170 retval = dpmv8_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
1171 bp->address, bp->length);
1172 if (retval == ERROR_OK)
1173 dpm->dbp[i].bp = bp;
1174 break;
1175 }
1176 }
1177
1178 return retval;
1179 }
1180
1181 static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
1182 {
1183 struct arm *arm = target_to_arm(target);
1184 struct arm_dpm *dpm = arm->dpm;
1185 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1186
1187 for (unsigned i = 0; i < dpm->nbp; i++) {
1188 if (dpm->dbp[i].bp == bp) {
1189 dpm->dbp[i].bp = NULL;
1190 dpm->dbp[i].bpwp.dirty = true;
1191
1192 /* hardware is updated in write_dirty_registers() */
1193 retval = ERROR_OK;
1194 break;
1195 }
1196 }
1197
1198 return retval;
1199 }
1200
1201 static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
1202 struct watchpoint *wp)
1203 {
1204 int retval;
1205 struct dpm_wp *dwp = dpm->dwp + index_t;
1206 uint32_t control;
1207
1208 /* this hardware doesn't support data value matching or masking */
1209 if (wp->value || wp->mask != ~(uint32_t)0) {
1210 LOG_DEBUG("watchpoint values and masking not supported");
1211 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1212 }
1213
1214 retval = dpmv8_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
1215 if (retval != ERROR_OK)
1216 return retval;
1217
1218 control = dwp->bpwp.control;
1219 switch (wp->rw) {
1220 case WPT_READ:
1221 control |= 1 << 3;
1222 break;
1223 case WPT_WRITE:
1224 control |= 2 << 3;
1225 break;
1226 case WPT_ACCESS:
1227 control |= 3 << 3;
1228 break;
1229 }
1230 dwp->bpwp.control = control;
1231
1232 dpm->dwp[index_t].wp = wp;
1233
1234 return retval;
1235 }
1236
1237 static int dpmv8_add_watchpoint(struct target *target, struct watchpoint *wp)
1238 {
1239 struct arm *arm = target_to_arm(target);
1240 struct arm_dpm *dpm = arm->dpm;
1241 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1242
1243 if (dpm->bpwp_enable) {
1244 for (unsigned i = 0; i < dpm->nwp; i++) {
1245 if (!dpm->dwp[i].wp) {
1246 retval = dpmv8_watchpoint_setup(dpm, i, wp);
1247 break;
1248 }
1249 }
1250 }
1251
1252 return retval;
1253 }
1254
1255 static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp)
1256 {
1257 struct arm *arm = target_to_arm(target);
1258 struct arm_dpm *dpm = arm->dpm;
1259 int retval = ERROR_COMMAND_SYNTAX_ERROR;
1260
1261 for (unsigned i = 0; i < dpm->nwp; i++) {
1262 if (dpm->dwp[i].wp == wp) {
1263 dpm->dwp[i].wp = NULL;
1264 dpm->dwp[i].bpwp.dirty = true;
1265
1266 /* hardware is updated in write_dirty_registers() */
1267 retval = ERROR_OK;
1268 break;
1269 }
1270 }
1271
1272 return retval;
1273 }
1274
1275 void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr)
1276 {
1277 switch (dpm->arm->core_state) {
1278 case ARM_STATE_ARM:
1279 case ARM_STATE_AARCH64:
1280 addr -= 8;
1281 break;
1282 case ARM_STATE_THUMB:
1283 case ARM_STATE_THUMB_EE:
1284 addr -= 4;
1285 break;
1286 case ARM_STATE_JAZELLE:
1287 /* ?? */
1288 break;
1289 default:
1290 LOG_DEBUG("Unknown core_state");
1291 break;
1292 }
1293 dpm->wp_pc = addr;
1294 }
1295
1296 /*
1297 * Handle exceptions taken in debug state. This happens mostly for memory
1298 * accesses that violated a MMU policy. Taking an exception while in debug
1299 * state clobbers certain state registers on the target exception level.
1300 * Just mark those registers dirty so that they get restored on resume.
1301 * This works both for Aarch32 and Aarch64 states.
1302 *
1303 * This function must not perform any actions that trigger another exception
1304 * or a recursion will happen.
1305 */
1306 void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore)
1307 {
1308 struct armv8_common *armv8 = dpm->arm->arch_info;
1309 struct reg_cache *cache = dpm->arm->core_cache;
1310 enum arm_state core_state;
1311 uint64_t dlr;
1312 uint32_t dspsr;
1313 unsigned int el;
1314
1315 static const int clobbered_regs_by_el[3][5] = {
1316 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL1, ARMV8_ESR_EL1, ARMV8_SPSR_EL1 },
1317 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL2, ARMV8_ESR_EL2, ARMV8_SPSR_EL2 },
1318 { ARMV8_PC, ARMV8_xPSR, ARMV8_ELR_EL3, ARMV8_ESR_EL3, ARMV8_SPSR_EL3 },
1319 };
1320
1321 el = (dpm->dscr >> 8) & 3;
1322
1323 /* safety check, must not happen since EL0 cannot be a target for an exception */
1324 if (el < SYSTEM_CUREL_EL1 || el > SYSTEM_CUREL_EL3) {
1325 LOG_ERROR("%s: EL %i is invalid, DSCR corrupted?", __func__, el);
1326 return;
1327 }
1328
1329 /* Clear sticky error */
1330 mem_ap_write_u32(armv8->debug_ap,
1331 armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
1332
1333 armv8->read_reg_u64(armv8, ARMV8_xPSR, &dlr);
1334 dspsr = dlr;
1335 armv8->read_reg_u64(armv8, ARMV8_PC, &dlr);
1336
1337 LOG_DEBUG("Exception taken to EL %i, DLR=0x%016"PRIx64" DSPSR=0x%08"PRIx32,
1338 el, dlr, dspsr);
1339
1340 /* mark all clobbered registers as dirty */
1341 for (int i = 0; i < 5; i++)
1342 cache->reg_list[clobbered_regs_by_el[el-1][i]].dirty = true;
1343
1344 /*
1345 * re-evaluate the core state, we might be in Aarch64 state now
1346 * we rely on dpm->dscr being up-to-date
1347 */
1348 core_state = armv8_dpm_get_core_state(dpm);
1349 armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
1350 armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
1351
1352 if (do_restore)
1353 armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
1354 }
1355
1356 /*----------------------------------------------------------------------*/
1357
1358 /*
1359 * Other debug and support utilities
1360 */
1361
1362 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
1363 {
1364 struct target *target = dpm->arm->target;
1365
1366 dpm->dscr = dscr;
1367 dpm->last_el = (dscr >> 8) & 3;
1368
1369 /* Examine debug reason */
1370 switch (DSCR_ENTRY(dscr)) {
1371 /* FALL THROUGH -- assume a v6 core in abort mode */
1372 case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */
1373 target->debug_reason = DBG_REASON_DBGRQ;
1374 break;
1375 case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */
1376 case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/
1377 case DSCRV8_ENTRY_HALT_STEP:
1378 target->debug_reason = DBG_REASON_SINGLESTEP;
1379 break;
1380 case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */
1381 case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */
1382 case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */
1383 case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/
1384 case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/
1385 target->debug_reason = DBG_REASON_BREAKPOINT;
1386 break;
1387 case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */
1388 target->debug_reason = DBG_REASON_WATCHPOINT;
1389 break;
1390 case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/
1391 target->debug_reason = DBG_REASON_EXC_CATCH;
1392 break;
1393 default:
1394 target->debug_reason = DBG_REASON_UNDEFINED;
1395 break;
1396 }
1397
1398 }
1399
1400 /*----------------------------------------------------------------------*/
1401
1402 /*
1403 * Setup and management support.
1404 */
1405
1406 /**
1407 * Hooks up this DPM to its associated target; call only once.
1408 * Initially this only covers the register cache.
1409 *
1410 * Oh, and watchpoints. Yeah.
1411 */
1412 int armv8_dpm_setup(struct arm_dpm *dpm)
1413 {
1414 struct arm *arm = dpm->arm;
1415 struct target *target = arm->target;
1416 struct reg_cache *cache;
1417 arm->dpm = dpm;
1418
1419 /* register access setup */
1420 arm->full_context = armv8_dpm_full_context;
1421 arm->read_core_reg = armv8_dpm_read_core_reg;
1422 arm->write_core_reg = armv8_dpm_write_core_reg;
1423
1424 if (arm->core_cache == NULL) {
1425 cache = armv8_build_reg_cache(target);
1426 if (!cache)
1427 return ERROR_FAIL;
1428 }
1429
1430 /* coprocessor access setup */
1431 arm->mrc = dpmv8_mrc;
1432 arm->mcr = dpmv8_mcr;
1433
1434 dpm->prepare = dpmv8_dpm_prepare;
1435 dpm->finish = dpmv8_dpm_finish;
1436
1437 dpm->instr_execute = dpmv8_instr_execute;
1438 dpm->instr_write_data_dcc = dpmv8_instr_write_data_dcc;
1439 dpm->instr_write_data_dcc_64 = dpmv8_instr_write_data_dcc_64;
1440 dpm->instr_write_data_r0 = dpmv8_instr_write_data_r0;
1441 dpm->instr_write_data_r0_64 = dpmv8_instr_write_data_r0_64;
1442 dpm->instr_cpsr_sync = dpmv8_instr_cpsr_sync;
1443
1444 dpm->instr_read_data_dcc = dpmv8_instr_read_data_dcc;
1445 dpm->instr_read_data_dcc_64 = dpmv8_instr_read_data_dcc_64;
1446 dpm->instr_read_data_r0 = dpmv8_instr_read_data_r0;
1447 dpm->instr_read_data_r0_64 = dpmv8_instr_read_data_r0_64;
1448
1449 dpm->arm_reg_current = armv8_reg_current;
1450
1451 /* dpm->bpwp_enable = dpmv8_bpwp_enable; */
1452 dpm->bpwp_disable = dpmv8_bpwp_disable;
1453
1454 /* breakpoint setup -- optional until it works everywhere */
1455 if (!target->type->add_breakpoint) {
1456 target->type->add_breakpoint = dpmv8_add_breakpoint;
1457 target->type->remove_breakpoint = dpmv8_remove_breakpoint;
1458 }
1459
1460 /* watchpoint setup */
1461 target->type->add_watchpoint = dpmv8_add_watchpoint;
1462 target->type->remove_watchpoint = dpmv8_remove_watchpoint;
1463
1464 /* FIXME add vector catch support */
1465
1466 dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
1467 dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
1468
1469 dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
1470 dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
1471
1472 if (!dpm->dbp || !dpm->dwp) {
1473 free(dpm->dbp);
1474 free(dpm->dwp);
1475 return ERROR_FAIL;
1476 }
1477
1478 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1479 target_name(target), dpm->nbp, dpm->nwp);
1480
1481 /* REVISIT ... and some of those breakpoints could match
1482 * execution context IDs...
1483 */
1484
1485 return ERROR_OK;
1486 }
1487
1488 /**
1489 * Reinitializes DPM state at the beginning of a new debug session
1490 * or after a reset which may have affected the debug module.
1491 */
1492 int armv8_dpm_initialize(struct arm_dpm *dpm)
1493 {
1494 /* Disable all breakpoints and watchpoints at startup. */
1495 if (dpm->bpwp_disable) {
1496 unsigned i;
1497
1498 for (i = 0; i < dpm->nbp; i++) {
1499 dpm->dbp[i].bpwp.number = i;
1500 (void) dpm->bpwp_disable(dpm, i);
1501 }
1502 for (i = 0; i < dpm->nwp; i++) {
1503 dpm->dwp[i].bpwp.number = 16 + i;
1504 (void) dpm->bpwp_disable(dpm, 16 + i);
1505 }
1506 } else
1507 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1508 target_name(dpm->arm->target));
1509
1510 return ERROR_OK;
1511 }
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