1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
69 #define ARMV8_COMMON_MAGIC 0x0A450AAA
71 /* VA to PA translation operations opc2 values*/
80 /* L210/L220 cache controller support */
81 struct armv8_l2x_cache
{
86 struct armv8_cachesize
{
88 /* cache dimensionning */
90 uint32_t associativity
;
93 /* info for set way operation on cache */
100 struct armv8_cache_common
{
102 struct armv8_cachesize d_u_size
; /* data cache */
103 struct armv8_cachesize i_size
; /* instruction cache */
105 int d_u_cache_enabled
;
106 /* l2 external unified cache if some */
108 int (*flush_all_data_cache
)(struct target
*target
);
109 int (*display_cache_info
)(struct command_context
*cmd_ctx
,
110 struct armv8_cache_common
*armv8_cache
);
113 struct armv8_mmu_common
{
114 /* following field mmu working way */
115 int32_t ttbr1_used
; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
116 uint64_t ttbr0_mask
;/* masked to be used */
119 int (*read_physical_memory
)(struct target
*target
, target_addr_t address
,
120 uint32_t size
, uint32_t count
, uint8_t *buffer
);
121 struct armv8_cache_common armv8_cache
;
122 uint32_t mmu_enabled
;
125 struct armv8_common
{
128 struct reg_cache
*core_cache
;
130 /* Core Debug Unit */
135 struct adiv5_ap
*debug_ap
;
136 struct adiv5_ap
*memory_ap
;
137 bool memory_ap_available
;
139 uint8_t multi_processor_system
;
143 /* armv8 aarch64 need below information for page translation */
149 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
150 struct armv8_mmu_common armv8_mmu
;
152 /* Direct processor core register read and writes */
153 int (*load_core_reg_u64
)(struct target
*target
, uint32_t num
, uint64_t *value
);
154 int (*store_core_reg_u64
)(struct target
*target
, uint32_t num
, uint64_t value
);
156 int (*examine_debug_reason
)(struct target
*target
);
157 int (*post_debug_entry
)(struct target
*target
);
159 void (*pre_restore_context
)(struct target
*target
);
162 static inline struct armv8_common
*
163 target_to_armv8(struct target
*target
)
165 return container_of(target
->arch_info
, struct armv8_common
, arm
);
168 /* register offsets from armv8.debug_base */
169 #define CPUV8_DBG_MAINID0 0xD00
170 #define CPUV8_DBG_CPUFEATURE0 0xD20
171 #define CPUV8_DBG_DBGFEATURE0 0xD28
172 #define CPUV8_DBG_MEMFEATURE0 0xD38
174 #define CPUV8_DBG_LOCKACCESS 0xFB0
175 #define CPUV8_DBG_LOCKSTATUS 0xFB4
177 #define CPUV8_DBG_EDESR 0x20
178 #define CPUV8_DBG_EDECR 0x24
179 #define CPUV8_DBG_WFAR0 0x30
180 #define CPUV8_DBG_WFAR1 0x34
181 #define CPUV8_DBG_DSCR 0x088
182 #define CPUV8_DBG_DRCR 0x090
183 #define CPUV8_DBG_PRCR 0x310
184 #define CPUV8_DBG_PRSR 0x314
186 #define CPUV8_DBG_DTRRX 0x080
187 #define CPUV8_DBG_ITR 0x084
188 #define CPUV8_DBG_SCR 0x088
189 #define CPUV8_DBG_DTRTX 0x08c
191 #define CPUV8_DBG_BVR_BASE 0x400
192 #define CPUV8_DBG_BCR_BASE 0x408
193 #define CPUV8_DBG_WVR_BASE 0x800
194 #define CPUV8_DBG_WCR_BASE 0x808
195 #define CPUV8_DBG_VCR 0x01C
197 #define CPUV8_DBG_OSLAR 0x300
199 #define CPUV8_DBG_AUTHSTATUS 0xFB8
201 /*define CTI(cross trigger interface)*/
203 #define CTI_INACK 0x10
204 #define CTI_APPSET 0x14
205 #define CTI_APPCLEAR 0x18
206 #define CTI_APPPULSE 0x1C
207 #define CTI_INEN0 0x20
208 #define CTI_INEN1 0x24
209 #define CTI_INEN2 0x28
210 #define CTI_INEN3 0x2C
211 #define CTI_INEN4 0x30
212 #define CTI_INEN5 0x34
213 #define CTI_INEN6 0x38
214 #define CTI_INEN7 0x3C
215 #define CTI_OUTEN0 0xA0
216 #define CTI_OUTEN1 0xA4
217 #define CTI_OUTEN2 0xA8
218 #define CTI_OUTEN3 0xAC
219 #define CTI_OUTEN4 0xB0
220 #define CTI_OUTEN5 0xB4
221 #define CTI_OUTEN6 0xB8
222 #define CTI_OUTEN7 0xBC
223 #define CTI_TRIN_STATUS 0x130
224 #define CTI_TROUT_STATUS 0x134
225 #define CTI_CHIN_STATUS 0x138
226 #define CTI_CHOU_STATUS 0x13C
227 #define CTI_GATE 0x140
228 #define CTI_UNLOCK 0xFB0
230 #define PAGE_SIZE_4KB 0x1000
231 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
232 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
233 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
234 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
236 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
237 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
238 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
239 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
241 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
243 int armv8_arch_state(struct target
*target
);
244 int armv8_identify_cache(struct target
*target
);
245 int armv8_init_arch_info(struct target
*target
, struct armv8_common
*armv8
);
246 int armv8_mmu_translate_va_pa(struct target
*target
, target_addr_t va
,
247 target_addr_t
*val
, int meminfo
);
248 int armv8_mmu_translate_va(struct target
*target
, uint32_t va
, uint32_t *val
);
250 int armv8_handle_cache_info_command(struct command_context
*cmd_ctx
,
251 struct armv8_cache_common
*armv8_cache
);
253 void armv8_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
255 extern const struct command_registration armv8_command_handlers
[];
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)