src/target/armv8.h

   1 /***************************************************************************
   2  *   Copyright (C) 2015 by David Ung                                       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_ARMV8_H
  20 #define OPENOCD_TARGET_ARMV8_H
  21
  22 #include "arm_adi_v5.h"
  23 #include "arm.h"
  24 #include "armv4_5_mmu.h"
  25 #include "armv4_5_cache.h"
  26 #include "armv8_dpm.h"
  27
  28 enum {
  29         ARMV8_R0 = 0,
  30         ARMV8_R1,
  31         ARMV8_R2,
  32         ARMV8_R3,
  33         ARMV8_R4,
  34         ARMV8_R5,
  35         ARMV8_R6,
  36         ARMV8_R7,
  37         ARMV8_R8,
  38         ARMV8_R9,
  39         ARMV8_R10,
  40         ARMV8_R11,
  41         ARMV8_R12,
  42         ARMV8_R13,
  43         ARMV8_R14,
  44         ARMV8_R15,
  45         ARMV8_R16,
  46         ARMV8_R17,
  47         ARMV8_R18,
  48         ARMV8_R19,
  49         ARMV8_R20,
  50         ARMV8_R21,
  51         ARMV8_R22,
  52         ARMV8_R23,
  53         ARMV8_R24,
  54         ARMV8_R25,
  55         ARMV8_R26,
  56         ARMV8_R27,
  57         ARMV8_R28,
  58         ARMV8_R29,
  59         ARMV8_R30,
  60
  61         ARMV8_SP = 31,
  62         ARMV8_PC = 32,
  63         ARMV8_xPSR = 33,
  64
  65         ARMV8_ELR_EL1 = 34,
  66         ARMV8_ESR_EL1 = 35,
  67         ARMV8_SPSR_EL1 = 36,
  68
  69         ARMV8_ELR_EL2 = 37,
  70         ARMV8_ESR_EL2 = 38,
  71         ARMV8_SPSR_EL2 = 39,
  72
  73         ARMV8_ELR_EL3 = 40,
  74         ARMV8_ESR_EL3 = 41,
  75         ARMV8_SPSR_EL3 = 42,
  76
  77         ARMV8_LAST_REG,
  78 };
  79
  80
  81 #define ARMV8_COMMON_MAGIC 0x0A450AAA
  82
  83 /* VA to PA translation operations opc2 values*/
  84 #define V2PCWPR  0
  85 #define V2PCWPW  1
  86 #define V2PCWUR  2
  87 #define V2PCWUW  3
  88 #define V2POWPR  4
  89 #define V2POWPW  5
  90 #define V2POWUR  6
  91 #define V2POWUW  7
  92 /*   L210/L220 cache controller support */
  93 struct armv8_l2x_cache {
  94         uint32_t base;
  95         uint32_t way;
  96 };
  97
  98 struct armv8_cachesize {
  99         uint32_t level_num;
 100         /*  cache dimensionning */
 101         uint32_t linelen;
 102         uint32_t associativity;
 103         uint32_t nsets;
 104         uint32_t cachesize;
 105         /* info for set way operation on cache */
 106         uint32_t index;
 107         uint32_t index_shift;
 108         uint32_t way;
 109         uint32_t way_shift;
 110 };
 111
 112 /* information about one architecture cache at any level */
 113 struct armv8_arch_cache {
 114         int ctype;                              /* cache type, CLIDR encoding */
 115         struct armv8_cachesize d_u_size;        /* data cache */
 116         struct armv8_cachesize i_size;          /* instruction cache */
 117 };
 118
 119 struct armv8_cache_common {
 120         int info;
 121         int loc;
 122         uint32_t iminline;
 123         uint32_t dminline;
 124         struct armv8_arch_cache arch[6];        /* cache info, L1 - L7 */
 125         int i_cache_enabled;
 126         int d_u_cache_enabled;
 127
 128         /* l2 external unified cache if some */
 129         void *l2_cache;
 130         int (*flush_all_data_cache)(struct target *target);
 131         int (*display_cache_info)(struct command_context *cmd_ctx,
 132                         struct armv8_cache_common *armv8_cache);
 133 };
 134
 135 struct armv8_mmu_common {
 136         /* following field mmu working way */
 137         int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
 138         uint64_t ttbr0_mask;/*  masked to be used  */
 139
 140         uint32_t ttbcr;     /* cache for ttbcr register */
 141         uint32_t ttbr_mask[2];
 142         uint32_t ttbr_range[2];
 143
 144         int (*read_physical_memory)(struct target *target, target_addr_t address,
 145                         uint32_t size, uint32_t count, uint8_t *buffer);
 146         struct armv8_cache_common armv8_cache;
 147         uint32_t mmu_enabled;
 148 };
 149
 150 struct armv8_common {
 151         struct arm arm;
 152         int common_magic;
 153         struct reg_cache *core_cache;
 154
 155         /* Core Debug Unit */
 156         struct arm_dpm dpm;
 157         uint32_t debug_base;
 158         uint32_t cti_base;
 159         struct adiv5_ap *debug_ap;
 160
 161         const uint32_t *opcodes;
 162
 163         /* mdir */
 164         uint8_t multi_processor_system;
 165         uint8_t cluster_id;
 166         uint8_t cpu_id;
 167
 168         /* armv8 aarch64 need below information for page translation */
 169         uint8_t va_size;
 170         uint8_t pa_size;
 171         uint32_t page_size;
 172         uint64_t ttbr_base;
 173
 174         struct armv8_mmu_common armv8_mmu;
 175
 176         /* Direct processor core register read and writes */
 177         int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
 178         int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
 179
 180         int (*examine_debug_reason)(struct target *target);
 181         int (*post_debug_entry)(struct target *target);
 182
 183         void (*pre_restore_context)(struct target *target);
 184 };
 185
 186 static inline struct armv8_common *
 187 target_to_armv8(struct target *target)
 188 {
 189         return container_of(target->arch_info, struct armv8_common, arm);
 190 }
 191
 192 /* register offsets from armv8.debug_base */
 193 #define CPUV8_DBG_MAINID0               0xD00
 194 #define CPUV8_DBG_CPUFEATURE0   0xD20
 195 #define CPUV8_DBG_DBGFEATURE0   0xD28
 196 #define CPUV8_DBG_MEMFEATURE0   0xD38
 197
 198 #define CPUV8_DBG_LOCKACCESS 0xFB0
 199 #define CPUV8_DBG_LOCKSTATUS 0xFB4
 200
 201 #define CPUV8_DBG_EDESR         0x20
 202 #define CPUV8_DBG_EDECR         0x24
 203 #define CPUV8_DBG_WFAR0         0x30
 204 #define CPUV8_DBG_WFAR1         0x34
 205 #define CPUV8_DBG_DSCR          0x088
 206 #define CPUV8_DBG_DRCR          0x090
 207 #define CPUV8_DBG_PRCR          0x310
 208 #define CPUV8_DBG_PRSR          0x314
 209
 210 #define CPUV8_DBG_DTRRX         0x080
 211 #define CPUV8_DBG_ITR           0x084
 212 #define CPUV8_DBG_SCR           0x088
 213 #define CPUV8_DBG_DTRTX         0x08c
 214
 215 #define CPUV8_DBG_BVR_BASE      0x400
 216 #define CPUV8_DBG_BCR_BASE      0x408
 217 #define CPUV8_DBG_WVR_BASE      0x800
 218 #define CPUV8_DBG_WCR_BASE      0x808
 219 #define CPUV8_DBG_VCR           0x01C
 220
 221 #define CPUV8_DBG_OSLAR         0x300
 222
 223 #define CPUV8_DBG_AUTHSTATUS    0xFB8
 224
 225 /*define CTI(cross trigger interface)*/
 226 #define CTI_CTR                         0x0
 227 #define CTI_INACK                       0x10
 228 #define CTI_APPSET                      0x14
 229 #define CTI_APPCLEAR            0x18
 230 #define CTI_APPPULSE            0x1C
 231 #define CTI_INEN0                       0x20
 232 #define CTI_INEN1                       0x24
 233 #define CTI_INEN2                       0x28
 234 #define CTI_INEN3                       0x2C
 235 #define CTI_INEN4                       0x30
 236 #define CTI_INEN5                       0x34
 237 #define CTI_INEN6                       0x38
 238 #define CTI_INEN7                       0x3C
 239 #define CTI_OUTEN0                      0xA0
 240 #define CTI_OUTEN1                      0xA4
 241 #define CTI_OUTEN2                      0xA8
 242 #define CTI_OUTEN3                      0xAC
 243 #define CTI_OUTEN4                      0xB0
 244 #define CTI_OUTEN5                      0xB4
 245 #define CTI_OUTEN6                      0xB8
 246 #define CTI_OUTEN7                      0xBC
 247 #define CTI_TRIN_STATUS         0x130
 248 #define CTI_TROUT_STATUS        0x134
 249 #define CTI_CHIN_STATUS         0x138
 250 #define CTI_CHOU_STATUS         0x13C
 251 #define CTI_GATE                        0x140
 252 #define CTI_UNLOCK                      0xFB0
 253
 254 #define CTI_CHNL(x)                     (1 << x)
 255 #define CTI_TRIG_HALT           0
 256 #define CTI_TRIG_RESUME         1
 257 #define CTI_TRIG(n)                     (1 << CTI_TRIG_##n)
 258
 259 #define PAGE_SIZE_4KB                           0x1000
 260 #define PAGE_SIZE_4KB_LEVEL0_BITS       39
 261 #define PAGE_SIZE_4KB_LEVEL1_BITS       30
 262 #define PAGE_SIZE_4KB_LEVEL2_BITS       21
 263 #define PAGE_SIZE_4KB_LEVEL3_BITS       12
 264
 265 #define PAGE_SIZE_4KB_LEVEL0_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
 266 #define PAGE_SIZE_4KB_LEVEL1_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
 267 #define PAGE_SIZE_4KB_LEVEL2_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
 268 #define PAGE_SIZE_4KB_LEVEL3_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
 269
 270 #define PAGE_SIZE_4KB_TRBBASE_MASK      0xFFFFFFFFF000
 271
 272 int armv8_arch_state(struct target *target);
 273 int armv8_read_mpidr(struct armv8_common *armv8);
 274 int armv8_identify_cache(struct armv8_common *armv8);
 275 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
 276 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 277                 target_addr_t *val, int meminfo);
 278 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 279
 280 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
 281                 struct armv8_cache_common *armv8_cache);
 282
 283 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
 284
 285 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 286 {
 287         switch (core_mode) {
 288         /* Aarch32 modes */
 289         case ARM_MODE_USR:
 290                 return 0;
 291         case ARM_MODE_SVC:
 292         case ARM_MODE_ABT: /* FIXME: EL3? */
 293         case ARM_MODE_IRQ: /* FIXME: EL3? */
 294         case ARM_MODE_FIQ: /* FIXME: EL3? */
 295         case ARM_MODE_UND: /* FIXME: EL3? */
 296         case ARM_MODE_SYS: /* FIXME: EL3? */
 297                 return 1;
 298         /* case ARM_MODE_HYP:
 299          *     return 2;
 300          */
 301         case ARM_MODE_MON:
 302                 return 3;
 303         /* all Aarch64 modes */
 304         default:
 305                 return (core_mode >> 6) & 3;
 306         }
 307 }
 308
 309 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 310 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 311
 312 extern const struct command_registration armv8_command_handlers[];
 313
 314 #endif /* OPENOCD_TARGET_ARMV8_H */