aarch64: add basic Aarch32 support
[openocd.git] / src / target / armv8.h
1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
18
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
21
22 #include "arm_adi_v5.h"
23 #include "arm.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
27
28 enum {
29 ARMV8_R0,
30 ARMV8_R1,
31 ARMV8_R2,
32 ARMV8_R3,
33 ARMV8_R4,
34 ARMV8_R5,
35 ARMV8_R6,
36 ARMV8_R7,
37 ARMV8_R8,
38 ARMV8_R9,
39 ARMV8_R10,
40 ARMV8_R11,
41 ARMV8_R12,
42 ARMV8_R13,
43 ARMV8_R14,
44 ARMV8_R15,
45 ARMV8_R16,
46 ARMV8_R17,
47 ARMV8_R18,
48 ARMV8_R19,
49 ARMV8_R20,
50 ARMV8_R21,
51 ARMV8_R22,
52 ARMV8_R23,
53 ARMV8_R24,
54 ARMV8_R25,
55 ARMV8_R26,
56 ARMV8_R27,
57 ARMV8_R28,
58 ARMV8_R29,
59 ARMV8_R30,
60 ARMV8_R31,
61
62 ARMV8_PC = 32,
63 ARMV8_xPSR = 33,
64
65 ARMV8_LAST_REG,
66 };
67
68
69 #define ARMV8_COMMON_MAGIC 0x0A450AAA
70
71 /* VA to PA translation operations opc2 values*/
72 #define V2PCWPR 0
73 #define V2PCWPW 1
74 #define V2PCWUR 2
75 #define V2PCWUW 3
76 #define V2POWPR 4
77 #define V2POWPW 5
78 #define V2POWUR 6
79 #define V2POWUW 7
80 /* L210/L220 cache controller support */
81 struct armv8_l2x_cache {
82 uint32_t base;
83 uint32_t way;
84 };
85
86 struct armv8_cachesize {
87 uint32_t level_num;
88 /* cache dimensionning */
89 uint32_t linelen;
90 uint32_t associativity;
91 uint32_t nsets;
92 uint32_t cachesize;
93 /* info for set way operation on cache */
94 uint32_t index;
95 uint32_t index_shift;
96 uint32_t way;
97 uint32_t way_shift;
98 };
99
100 struct armv8_cache_common {
101 int ctype;
102 struct armv8_cachesize d_u_size; /* data cache */
103 struct armv8_cachesize i_size; /* instruction cache */
104 int i_cache_enabled;
105 int d_u_cache_enabled;
106 /* l2 external unified cache if some */
107 void *l2_cache;
108 int (*flush_all_data_cache)(struct target *target);
109 int (*display_cache_info)(struct command_context *cmd_ctx,
110 struct armv8_cache_common *armv8_cache);
111 };
112
113 struct armv8_mmu_common {
114 /* following field mmu working way */
115 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
116 uint64_t ttbr0_mask;/* masked to be used */
117 uint32_t os_border;
118
119 uint32_t ttbcr; /* cache for ttbcr register */
120 uint32_t ttbr_mask[2];
121 uint32_t ttbr_range[2];
122
123 int (*read_physical_memory)(struct target *target, target_addr_t address,
124 uint32_t size, uint32_t count, uint8_t *buffer);
125 struct armv8_cache_common armv8_cache;
126 uint32_t mmu_enabled;
127 };
128
129 struct armv8_common {
130 struct arm arm;
131 int common_magic;
132 struct reg_cache *core_cache;
133
134 /* Core Debug Unit */
135 struct arm_dpm dpm;
136 uint32_t debug_base;
137 uint32_t cti_base;
138 struct adiv5_ap *debug_ap;
139
140 const uint32_t *opcodes;
141
142 /* mdir */
143 uint8_t multi_processor_system;
144 uint8_t cluster_id;
145 uint8_t cpu_id;
146
147 /* armv8 aarch64 need below information for page translation */
148 uint8_t va_size;
149 uint8_t pa_size;
150 uint32_t page_size;
151 uint64_t ttbr_base;
152
153 struct armv8_mmu_common armv8_mmu;
154
155 /* Direct processor core register read and writes */
156 int (*load_core_reg_u64)(struct target *target, uint32_t num, uint64_t *value);
157 int (*store_core_reg_u64)(struct target *target, uint32_t num, uint64_t value);
158
159 int (*examine_debug_reason)(struct target *target);
160 int (*post_debug_entry)(struct target *target);
161
162 void (*pre_restore_context)(struct target *target);
163 };
164
165 static inline struct armv8_common *
166 target_to_armv8(struct target *target)
167 {
168 return container_of(target->arch_info, struct armv8_common, arm);
169 }
170
171 /* register offsets from armv8.debug_base */
172 #define CPUV8_DBG_MAINID0 0xD00
173 #define CPUV8_DBG_CPUFEATURE0 0xD20
174 #define CPUV8_DBG_DBGFEATURE0 0xD28
175 #define CPUV8_DBG_MEMFEATURE0 0xD38
176
177 #define CPUV8_DBG_LOCKACCESS 0xFB0
178 #define CPUV8_DBG_LOCKSTATUS 0xFB4
179
180 #define CPUV8_DBG_EDESR 0x20
181 #define CPUV8_DBG_EDECR 0x24
182 #define CPUV8_DBG_WFAR0 0x30
183 #define CPUV8_DBG_WFAR1 0x34
184 #define CPUV8_DBG_DSCR 0x088
185 #define CPUV8_DBG_DRCR 0x090
186 #define CPUV8_DBG_PRCR 0x310
187 #define CPUV8_DBG_PRSR 0x314
188
189 #define CPUV8_DBG_DTRRX 0x080
190 #define CPUV8_DBG_ITR 0x084
191 #define CPUV8_DBG_SCR 0x088
192 #define CPUV8_DBG_DTRTX 0x08c
193
194 #define CPUV8_DBG_BVR_BASE 0x400
195 #define CPUV8_DBG_BCR_BASE 0x408
196 #define CPUV8_DBG_WVR_BASE 0x800
197 #define CPUV8_DBG_WCR_BASE 0x808
198 #define CPUV8_DBG_VCR 0x01C
199
200 #define CPUV8_DBG_OSLAR 0x300
201
202 #define CPUV8_DBG_AUTHSTATUS 0xFB8
203
204 /*define CTI(cross trigger interface)*/
205 #define CTI_CTR 0x0
206 #define CTI_INACK 0x10
207 #define CTI_APPSET 0x14
208 #define CTI_APPCLEAR 0x18
209 #define CTI_APPPULSE 0x1C
210 #define CTI_INEN0 0x20
211 #define CTI_INEN1 0x24
212 #define CTI_INEN2 0x28
213 #define CTI_INEN3 0x2C
214 #define CTI_INEN4 0x30
215 #define CTI_INEN5 0x34
216 #define CTI_INEN6 0x38
217 #define CTI_INEN7 0x3C
218 #define CTI_OUTEN0 0xA0
219 #define CTI_OUTEN1 0xA4
220 #define CTI_OUTEN2 0xA8
221 #define CTI_OUTEN3 0xAC
222 #define CTI_OUTEN4 0xB0
223 #define CTI_OUTEN5 0xB4
224 #define CTI_OUTEN6 0xB8
225 #define CTI_OUTEN7 0xBC
226 #define CTI_TRIN_STATUS 0x130
227 #define CTI_TROUT_STATUS 0x134
228 #define CTI_CHIN_STATUS 0x138
229 #define CTI_CHOU_STATUS 0x13C
230 #define CTI_GATE 0x140
231 #define CTI_UNLOCK 0xFB0
232
233 #define CTI_CHNL(x) (1 << x)
234 #define CTI_TRIG_HALT 0
235 #define CTI_TRIG_RESUME 1
236 #define CTI_TRIG(n) (1 << CTI_TRIG_##n)
237
238 #define PAGE_SIZE_4KB 0x1000
239 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
240 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
241 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
242 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
243
244 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
245 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
246 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
247 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
248
249 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
250
251 int armv8_arch_state(struct target *target);
252 int armv8_identify_cache(struct target *target);
253 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
254 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
255 target_addr_t *val, int meminfo);
256 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
257
258 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
259 struct armv8_cache_common *armv8_cache);
260
261 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
262
263 extern const struct command_registration armv8_command_handlers[];
264
265 #endif