1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
22 #include "arm_adi_v5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
69 #define ARMV8_COMMON_MAGIC 0x0A450AAA
71 /* VA to PA translation operations opc2 values*/
80 /* L210/L220 cache controller support */
81 struct armv8_l2x_cache
{
86 struct armv8_cachesize
{
88 /* cache dimensionning */
90 uint32_t associativity
;
93 /* info for set way operation on cache */
100 struct armv8_cache_common
{
102 struct armv8_cachesize d_u_size
; /* data cache */
103 struct armv8_cachesize i_size
; /* instruction cache */
105 int d_u_cache_enabled
;
106 /* l2 external unified cache if some */
108 int (*flush_all_data_cache
)(struct target
*target
);
109 int (*display_cache_info
)(struct command_context
*cmd_ctx
,
110 struct armv8_cache_common
*armv8_cache
);
113 struct armv8_mmu_common
{
114 /* following field mmu working way */
115 int32_t ttbr1_used
; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
116 uint32_t ttbr0_mask
;/* masked to be used */
119 int (*read_physical_memory
)(struct target
*target
, target_addr_t address
,
120 uint32_t size
, uint32_t count
, uint8_t *buffer
);
121 struct armv8_cache_common armv8_cache
;
122 uint32_t mmu_enabled
;
125 struct armv8_common
{
128 struct reg_cache
*core_cache
;
130 /* Core Debug Unit */
133 struct adiv5_ap
*debug_ap
;
134 struct adiv5_ap
*memory_ap
;
135 bool memory_ap_available
;
137 uint8_t multi_processor_system
;
142 /* cache specific to V7 Memory Management Unit compatible with v4_5*/
143 struct armv8_mmu_common armv8_mmu
;
145 /* Direct processor core register read and writes */
146 int (*load_core_reg_u64
)(struct target
*target
, uint32_t num
, uint64_t *value
);
147 int (*store_core_reg_u64
)(struct target
*target
, uint32_t num
, uint64_t value
);
149 int (*examine_debug_reason
)(struct target
*target
);
150 int (*post_debug_entry
)(struct target
*target
);
152 void (*pre_restore_context
)(struct target
*target
);
155 static inline struct armv8_common
*
156 target_to_armv8(struct target
*target
)
158 return container_of(target
->arch_info
, struct armv8_common
, arm
);
161 /* register offsets from armv8.debug_base */
163 #define CPUDBG_WFAR 0x018
164 #define CPUDBG_DESR 0x020
165 #define CPUDBG_DECR 0x024
166 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
167 #define CPUDBG_DSCR 0x088
168 #define CPUDBG_DRCR 0x090
169 #define CPUDBG_PRCR 0x310
170 #define CPUDBG_PRSR 0x314
172 #define CPUDBG_DTRRX 0x080
173 #define CPUDBG_ITR 0x084
174 #define CPUDBG_DTRTX 0x08c
176 #define CPUDBG_BVR_BASE 0x400
177 #define CPUDBG_BCR_BASE 0x408
178 #define CPUDBG_WVR_BASE 0x180
179 #define CPUDBG_WCR_BASE 0x1C0
180 #define CPUDBG_VCR 0x01C
182 #define CPUDBG_OSLAR 0x300
183 #define CPUDBG_OSLSR 0x304
184 #define CPUDBG_OSSRR 0x308
185 #define CPUDBG_ECR 0x024
187 #define CPUDBG_DSCCR 0x028
189 #define CPUDBG_AUTHSTATUS 0xFB8
191 int armv8_arch_state(struct target
*target
);
192 int armv8_identify_cache(struct target
*target
);
193 int armv8_init_arch_info(struct target
*target
, struct armv8_common
*armv8
);
194 int armv8_mmu_translate_va_pa(struct target
*target
, target_addr_t va
,
195 target_addr_t
*val
, int meminfo
);
196 int armv8_mmu_translate_va(struct target
*target
, uint32_t va
, uint32_t *val
);
198 int armv8_handle_cache_info_command(struct command_context
*cmd_ctx
,
199 struct armv8_cache_common
*armv8_cache
);
201 void armv8_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
203 extern const struct command_registration armv8_command_handlers
[];
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)