src/target/armv8.h

   1 /***************************************************************************
   2  *   Copyright (C) 2015 by David Ung                                       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_ARMV8_H
  20 #define OPENOCD_TARGET_ARMV8_H
  21
  22 #include "arm_adi_v5.h"
  23 #include "arm.h"
  24 #include "armv4_5_mmu.h"
  25 #include "armv4_5_cache.h"
  26 #include "armv8_dpm.h"
  27 #include "arm_cti.h"
  28
  29 enum {
  30         ARMV8_R0 = 0,
  31         ARMV8_R1,
  32         ARMV8_R2,
  33         ARMV8_R3,
  34         ARMV8_R4,
  35         ARMV8_R5,
  36         ARMV8_R6,
  37         ARMV8_R7,
  38         ARMV8_R8,
  39         ARMV8_R9,
  40         ARMV8_R10,
  41         ARMV8_R11,
  42         ARMV8_R12,
  43         ARMV8_R13,
  44         ARMV8_R14,
  45         ARMV8_R15,
  46         ARMV8_R16,
  47         ARMV8_R17,
  48         ARMV8_R18,
  49         ARMV8_R19,
  50         ARMV8_R20,
  51         ARMV8_R21,
  52         ARMV8_R22,
  53         ARMV8_R23,
  54         ARMV8_R24,
  55         ARMV8_R25,
  56         ARMV8_R26,
  57         ARMV8_R27,
  58         ARMV8_R28,
  59         ARMV8_R29,
  60         ARMV8_R30,
  61
  62         ARMV8_SP = 31,
  63         ARMV8_PC = 32,
  64         ARMV8_xPSR = 33,
  65
  66         ARMV8_V0 = 34,
  67         ARMV8_V1,
  68         ARMV8_V2,
  69         ARMV8_V3,
  70         ARMV8_V4,
  71         ARMV8_V5,
  72         ARMV8_V6,
  73         ARMV8_V7,
  74         ARMV8_V8,
  75         ARMV8_V9,
  76         ARMV8_V10,
  77         ARMV8_V11,
  78         ARMV8_V12,
  79         ARMV8_V13,
  80         ARMV8_V14,
  81         ARMV8_V15,
  82         ARMV8_V16,
  83         ARMV8_V17,
  84         ARMV8_V18,
  85         ARMV8_V19,
  86         ARMV8_V20,
  87         ARMV8_V21,
  88         ARMV8_V22,
  89         ARMV8_V23,
  90         ARMV8_V24,
  91         ARMV8_V25,
  92         ARMV8_V26,
  93         ARMV8_V27,
  94         ARMV8_V28,
  95         ARMV8_V29,
  96         ARMV8_V30,
  97         ARMV8_V31,
  98         ARMV8_FPSR,
  99         ARMV8_FPCR,
 100
 101         ARMV8_ELR_EL1 = 68,
 102         ARMV8_ESR_EL1 = 69,
 103         ARMV8_SPSR_EL1 = 70,
 104
 105         ARMV8_ELR_EL2 = 71,
 106         ARMV8_ESR_EL2 = 72,
 107         ARMV8_SPSR_EL2 = 73,
 108
 109         ARMV8_ELR_EL3 = 74,
 110         ARMV8_ESR_EL3 = 75,
 111         ARMV8_SPSR_EL3 = 76,
 112
 113         ARMV8_LAST_REG,
 114 };
 115
 116
 117 #define ARMV8_COMMON_MAGIC 0x0A450AAA
 118
 119 /* VA to PA translation operations opc2 values*/
 120 #define V2PCWPR  0
 121 #define V2PCWPW  1
 122 #define V2PCWUR  2
 123 #define V2PCWUW  3
 124 #define V2POWPR  4
 125 #define V2POWPW  5
 126 #define V2POWUR  6
 127 #define V2POWUW  7
 128 /*   L210/L220 cache controller support */
 129 struct armv8_l2x_cache {
 130         uint32_t base;
 131         uint32_t way;
 132 };
 133
 134 struct armv8_cachesize {
 135         uint32_t level_num;
 136         /*  cache dimensionning */
 137         uint32_t linelen;
 138         uint32_t associativity;
 139         uint32_t nsets;
 140         uint32_t cachesize;
 141         /* info for set way operation on cache */
 142         uint32_t index;
 143         uint32_t index_shift;
 144         uint32_t way;
 145         uint32_t way_shift;
 146 };
 147
 148 /* information about one architecture cache at any level */
 149 struct armv8_arch_cache {
 150         int ctype;                              /* cache type, CLIDR encoding */
 151         struct armv8_cachesize d_u_size;        /* data cache */
 152         struct armv8_cachesize i_size;          /* instruction cache */
 153 };
 154
 155 struct armv8_cache_common {
 156         int info;
 157         int loc;
 158         uint32_t iminline;
 159         uint32_t dminline;
 160         struct armv8_arch_cache arch[6];        /* cache info, L1 - L7 */
 161         int i_cache_enabled;
 162         int d_u_cache_enabled;
 163
 164         /* l2 external unified cache if some */
 165         void *l2_cache;
 166         int (*flush_all_data_cache)(struct target *target);
 167         int (*display_cache_info)(struct command_context *cmd_ctx,
 168                         struct armv8_cache_common *armv8_cache);
 169 };
 170
 171 struct armv8_mmu_common {
 172         /* following field mmu working way */
 173         int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
 174         uint64_t ttbr0_mask;/*  masked to be used  */
 175
 176         uint32_t ttbcr;     /* cache for ttbcr register */
 177         uint32_t ttbr_mask[2];
 178         uint32_t ttbr_range[2];
 179
 180         int (*read_physical_memory)(struct target *target, target_addr_t address,
 181                         uint32_t size, uint32_t count, uint8_t *buffer);
 182         struct armv8_cache_common armv8_cache;
 183         uint32_t mmu_enabled;
 184 };
 185
 186 struct armv8_common {
 187         struct arm arm;
 188         int common_magic;
 189         struct reg_cache *core_cache;
 190
 191         /* Core Debug Unit */
 192         struct arm_dpm dpm;
 193         uint32_t debug_base;
 194         struct adiv5_ap *debug_ap;
 195
 196         const uint32_t *opcodes;
 197
 198         /* mdir */
 199         uint8_t multi_processor_system;
 200         uint8_t cluster_id;
 201         uint8_t cpu_id;
 202
 203         /* armv8 aarch64 need below information for page translation */
 204         uint8_t va_size;
 205         uint8_t pa_size;
 206         uint32_t page_size;
 207         uint64_t ttbr_base;
 208
 209         struct armv8_mmu_common armv8_mmu;
 210
 211         struct arm_cti *cti;
 212
 213         /* Direct processor core register read and writes */
 214         int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
 215         int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
 216
 217         /* SIMD/FPU registers read/write interface */
 218         int (*read_reg_u128)(struct armv8_common *armv8, int num,
 219                         uint64_t *lvalue, uint64_t *hvalue);
 220         int (*write_reg_u128)(struct armv8_common *armv8, int num,
 221                         uint64_t lvalue, uint64_t hvalue);
 222
 223         int (*examine_debug_reason)(struct target *target);
 224         int (*post_debug_entry)(struct target *target);
 225
 226         void (*pre_restore_context)(struct target *target);
 227 };
 228
 229 static inline struct armv8_common *
 230 target_to_armv8(struct target *target)
 231 {
 232         return container_of(target->arch_info, struct armv8_common, arm);
 233 }
 234
 235 /* register offsets from armv8.debug_base */
 236 #define CPUV8_DBG_MAINID0               0xD00
 237 #define CPUV8_DBG_CPUFEATURE0   0xD20
 238 #define CPUV8_DBG_DBGFEATURE0   0xD28
 239 #define CPUV8_DBG_MEMFEATURE0   0xD38
 240
 241 #define CPUV8_DBG_LOCKACCESS 0xFB0
 242 #define CPUV8_DBG_LOCKSTATUS 0xFB4
 243
 244 #define CPUV8_DBG_EDESR         0x20
 245 #define CPUV8_DBG_EDECR         0x24
 246 #define CPUV8_DBG_WFAR0         0x30
 247 #define CPUV8_DBG_WFAR1         0x34
 248 #define CPUV8_DBG_DSCR          0x088
 249 #define CPUV8_DBG_DRCR          0x090
 250 #define CPUV8_DBG_PRCR          0x310
 251 #define CPUV8_DBG_PRSR          0x314
 252
 253 #define CPUV8_DBG_DTRRX         0x080
 254 #define CPUV8_DBG_ITR           0x084
 255 #define CPUV8_DBG_SCR           0x088
 256 #define CPUV8_DBG_DTRTX         0x08c
 257
 258 #define CPUV8_DBG_BVR_BASE      0x400
 259 #define CPUV8_DBG_BCR_BASE      0x408
 260 #define CPUV8_DBG_WVR_BASE      0x800
 261 #define CPUV8_DBG_WCR_BASE      0x808
 262 #define CPUV8_DBG_VCR           0x01C
 263
 264 #define CPUV8_DBG_OSLAR         0x300
 265
 266 #define CPUV8_DBG_AUTHSTATUS    0xFB8
 267
 268 #define PAGE_SIZE_4KB                           0x1000
 269 #define PAGE_SIZE_4KB_LEVEL0_BITS       39
 270 #define PAGE_SIZE_4KB_LEVEL1_BITS       30
 271 #define PAGE_SIZE_4KB_LEVEL2_BITS       21
 272 #define PAGE_SIZE_4KB_LEVEL3_BITS       12
 273
 274 #define PAGE_SIZE_4KB_LEVEL0_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
 275 #define PAGE_SIZE_4KB_LEVEL1_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
 276 #define PAGE_SIZE_4KB_LEVEL2_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
 277 #define PAGE_SIZE_4KB_LEVEL3_MASK       ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
 278
 279 #define PAGE_SIZE_4KB_TRBBASE_MASK      0xFFFFFFFFF000
 280
 281 int armv8_arch_state(struct target *target);
 282 int armv8_read_mpidr(struct armv8_common *armv8);
 283 int armv8_identify_cache(struct armv8_common *armv8);
 284 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
 285 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 286                 target_addr_t *val, int meminfo);
 287 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 288
 289 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
 290                 struct armv8_cache_common *armv8_cache);
 291
 292 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
 293
 294 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 295 {
 296         switch (core_mode) {
 297         /* Aarch32 modes */
 298         case ARM_MODE_USR:
 299                 return 0;
 300         case ARM_MODE_SVC:
 301         case ARM_MODE_ABT: /* FIXME: EL3? */
 302         case ARM_MODE_IRQ: /* FIXME: EL3? */
 303         case ARM_MODE_FIQ: /* FIXME: EL3? */
 304         case ARM_MODE_UND: /* FIXME: EL3? */
 305         case ARM_MODE_SYS: /* FIXME: EL3? */
 306                 return 1;
 307         /* case ARM_MODE_HYP:
 308          *     return 2;
 309          */
 310         case ARM_MODE_MON:
 311                 return 3;
 312         /* all Aarch64 modes */
 313         default:
 314                 return (core_mode >> 2) & 3;
 315         }
 316 }
 317
 318 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 319 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 320
 321 extern const struct command_registration armv8_command_handlers[];
 322
 323 #endif /* OPENOCD_TARGET_ARMV8_H */