target/armv8: change prototype of display_cache_info()
[openocd.git] / src / target / armv8.h
1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
18
19 #ifndef OPENOCD_TARGET_ARMV8_H
20 #define OPENOCD_TARGET_ARMV8_H
21
22 #include "arm_adi_v5.h"
23 #include "arm.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26 #include "armv8_dpm.h"
27 #include "arm_cti.h"
28
29 enum {
30 ARMV8_R0 = 0,
31 ARMV8_R1,
32 ARMV8_R2,
33 ARMV8_R3,
34 ARMV8_R4,
35 ARMV8_R5,
36 ARMV8_R6,
37 ARMV8_R7,
38 ARMV8_R8,
39 ARMV8_R9,
40 ARMV8_R10,
41 ARMV8_R11,
42 ARMV8_R12,
43 ARMV8_R13,
44 ARMV8_R14,
45 ARMV8_R15,
46 ARMV8_R16,
47 ARMV8_R17,
48 ARMV8_R18,
49 ARMV8_R19,
50 ARMV8_R20,
51 ARMV8_R21,
52 ARMV8_R22,
53 ARMV8_R23,
54 ARMV8_R24,
55 ARMV8_R25,
56 ARMV8_R26,
57 ARMV8_R27,
58 ARMV8_R28,
59 ARMV8_R29,
60 ARMV8_R30,
61
62 ARMV8_SP = 31,
63 ARMV8_PC = 32,
64 ARMV8_xPSR = 33,
65
66 ARMV8_V0 = 34,
67 ARMV8_V1,
68 ARMV8_V2,
69 ARMV8_V3,
70 ARMV8_V4,
71 ARMV8_V5,
72 ARMV8_V6,
73 ARMV8_V7,
74 ARMV8_V8,
75 ARMV8_V9,
76 ARMV8_V10,
77 ARMV8_V11,
78 ARMV8_V12,
79 ARMV8_V13,
80 ARMV8_V14,
81 ARMV8_V15,
82 ARMV8_V16,
83 ARMV8_V17,
84 ARMV8_V18,
85 ARMV8_V19,
86 ARMV8_V20,
87 ARMV8_V21,
88 ARMV8_V22,
89 ARMV8_V23,
90 ARMV8_V24,
91 ARMV8_V25,
92 ARMV8_V26,
93 ARMV8_V27,
94 ARMV8_V28,
95 ARMV8_V29,
96 ARMV8_V30,
97 ARMV8_V31,
98 ARMV8_FPSR,
99 ARMV8_FPCR,
100
101 ARMV8_ELR_EL1 = 68,
102 ARMV8_ESR_EL1 = 69,
103 ARMV8_SPSR_EL1 = 70,
104
105 ARMV8_ELR_EL2 = 71,
106 ARMV8_ESR_EL2 = 72,
107 ARMV8_SPSR_EL2 = 73,
108
109 ARMV8_ELR_EL3 = 74,
110 ARMV8_ESR_EL3 = 75,
111 ARMV8_SPSR_EL3 = 76,
112
113 ARMV8_LAST_REG,
114 };
115
116 enum run_control_op {
117 ARMV8_RUNCONTROL_UNKNOWN = 0,
118 ARMV8_RUNCONTROL_RESUME = 1,
119 ARMV8_RUNCONTROL_HALT = 2,
120 ARMV8_RUNCONTROL_STEP = 3,
121 };
122
123 #define ARMV8_COMMON_MAGIC 0x0A450AAA
124
125 /* VA to PA translation operations opc2 values*/
126 #define V2PCWPR 0
127 #define V2PCWPW 1
128 #define V2PCWUR 2
129 #define V2PCWUW 3
130 #define V2POWPR 4
131 #define V2POWPW 5
132 #define V2POWUR 6
133 #define V2POWUW 7
134 /* L210/L220 cache controller support */
135 struct armv8_l2x_cache {
136 uint32_t base;
137 uint32_t way;
138 };
139
140 struct armv8_cachesize {
141 uint32_t level_num;
142 /* cache dimensionning */
143 uint32_t linelen;
144 uint32_t associativity;
145 uint32_t nsets;
146 uint32_t cachesize;
147 /* info for set way operation on cache */
148 uint32_t index;
149 uint32_t index_shift;
150 uint32_t way;
151 uint32_t way_shift;
152 };
153
154 /* information about one architecture cache at any level */
155 struct armv8_arch_cache {
156 int ctype; /* cache type, CLIDR encoding */
157 struct armv8_cachesize d_u_size; /* data cache */
158 struct armv8_cachesize i_size; /* instruction cache */
159 };
160
161 struct armv8_cache_common {
162 int info;
163 int loc;
164 uint32_t iminline;
165 uint32_t dminline;
166 struct armv8_arch_cache arch[6]; /* cache info, L1 - L7 */
167 int i_cache_enabled;
168 int d_u_cache_enabled;
169
170 /* l2 external unified cache if some */
171 void *l2_cache;
172 int (*flush_all_data_cache)(struct target *target);
173 int (*display_cache_info)(struct command_invocation *cmd,
174 struct armv8_cache_common *armv8_cache);
175 };
176
177 struct armv8_mmu_common {
178 /* following field mmu working way */
179 int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
180 uint64_t ttbr0_mask;/* masked to be used */
181
182 uint32_t ttbcr; /* cache for ttbcr register */
183 uint32_t ttbr_mask[2];
184 uint32_t ttbr_range[2];
185
186 int (*read_physical_memory)(struct target *target, target_addr_t address,
187 uint32_t size, uint32_t count, uint8_t *buffer);
188 struct armv8_cache_common armv8_cache;
189 uint32_t mmu_enabled;
190 };
191
192 struct armv8_common {
193 struct arm arm;
194 int common_magic;
195 struct reg_cache *core_cache;
196
197 /* Core Debug Unit */
198 struct arm_dpm dpm;
199 uint32_t debug_base;
200 struct adiv5_ap *debug_ap;
201
202 const uint32_t *opcodes;
203
204 /* mdir */
205 uint8_t multi_processor_system;
206 uint8_t cluster_id;
207 uint8_t cpu_id;
208
209 /* armv8 aarch64 need below information for page translation */
210 uint8_t va_size;
211 uint8_t pa_size;
212 uint32_t page_size;
213 uint64_t ttbr_base;
214
215 struct armv8_mmu_common armv8_mmu;
216
217 struct arm_cti *cti;
218
219 /* last run-control command issued to this target (resume, halt, step) */
220 enum run_control_op last_run_control_op;
221
222 /* Direct processor core register read and writes */
223 int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
224 int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
225
226 /* SIMD/FPU registers read/write interface */
227 int (*read_reg_u128)(struct armv8_common *armv8, int num,
228 uint64_t *lvalue, uint64_t *hvalue);
229 int (*write_reg_u128)(struct armv8_common *armv8, int num,
230 uint64_t lvalue, uint64_t hvalue);
231
232 int (*examine_debug_reason)(struct target *target);
233 int (*post_debug_entry)(struct target *target);
234
235 void (*pre_restore_context)(struct target *target);
236 };
237
238 static inline struct armv8_common *
239 target_to_armv8(struct target *target)
240 {
241 return container_of(target->arch_info, struct armv8_common, arm);
242 }
243
244 static inline bool is_armv8(struct armv8_common *armv8)
245 {
246 return armv8->common_magic == ARMV8_COMMON_MAGIC;
247 }
248
249 /* register offsets from armv8.debug_base */
250 #define CPUV8_DBG_MAINID0 0xD00
251 #define CPUV8_DBG_CPUFEATURE0 0xD20
252 #define CPUV8_DBG_DBGFEATURE0 0xD28
253 #define CPUV8_DBG_MEMFEATURE0 0xD38
254
255 #define CPUV8_DBG_LOCKACCESS 0xFB0
256 #define CPUV8_DBG_LOCKSTATUS 0xFB4
257
258 #define CPUV8_DBG_EDESR 0x20
259 #define CPUV8_DBG_EDECR 0x24
260 #define CPUV8_DBG_WFAR0 0x30
261 #define CPUV8_DBG_WFAR1 0x34
262 #define CPUV8_DBG_DSCR 0x088
263 #define CPUV8_DBG_DRCR 0x090
264 #define CPUV8_DBG_ECCR 0x098
265 #define CPUV8_DBG_PRCR 0x310
266 #define CPUV8_DBG_PRSR 0x314
267
268 #define CPUV8_DBG_DTRRX 0x080
269 #define CPUV8_DBG_ITR 0x084
270 #define CPUV8_DBG_SCR 0x088
271 #define CPUV8_DBG_DTRTX 0x08c
272
273 #define CPUV8_DBG_BVR_BASE 0x400
274 #define CPUV8_DBG_BCR_BASE 0x408
275 #define CPUV8_DBG_WVR_BASE 0x800
276 #define CPUV8_DBG_WCR_BASE 0x808
277 #define CPUV8_DBG_VCR 0x01C
278
279 #define CPUV8_DBG_OSLAR 0x300
280
281 #define CPUV8_DBG_AUTHSTATUS 0xFB8
282
283 #define PAGE_SIZE_4KB 0x1000
284 #define PAGE_SIZE_4KB_LEVEL0_BITS 39
285 #define PAGE_SIZE_4KB_LEVEL1_BITS 30
286 #define PAGE_SIZE_4KB_LEVEL2_BITS 21
287 #define PAGE_SIZE_4KB_LEVEL3_BITS 12
288
289 #define PAGE_SIZE_4KB_LEVEL0_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL0_BITS)
290 #define PAGE_SIZE_4KB_LEVEL1_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL1_BITS)
291 #define PAGE_SIZE_4KB_LEVEL2_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL2_BITS)
292 #define PAGE_SIZE_4KB_LEVEL3_MASK ((0x1FFULL) << PAGE_SIZE_4KB_LEVEL3_BITS)
293
294 #define PAGE_SIZE_4KB_TRBBASE_MASK 0xFFFFFFFFF000
295
296 int armv8_arch_state(struct target *target);
297 int armv8_read_mpidr(struct armv8_common *armv8);
298 int armv8_identify_cache(struct armv8_common *armv8);
299 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
300 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
301 target_addr_t *val, int meminfo);
302 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
303
304 int armv8_handle_cache_info_command(struct command_invocation *cmd,
305 struct armv8_cache_common *armv8_cache);
306
307 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
308
309 static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
310 {
311 switch (core_mode) {
312 /* Aarch32 modes */
313 case ARM_MODE_USR:
314 return 0;
315 case ARM_MODE_SVC:
316 case ARM_MODE_ABT: /* FIXME: EL3? */
317 case ARM_MODE_IRQ: /* FIXME: EL3? */
318 case ARM_MODE_FIQ: /* FIXME: EL3? */
319 case ARM_MODE_UND: /* FIXME: EL3? */
320 case ARM_MODE_SYS: /* FIXME: EL3? */
321 return 1;
322 /* case ARM_MODE_HYP:
323 * return 2;
324 */
325 case ARM_MODE_MON:
326 return 3;
327 /* all Aarch64 modes */
328 default:
329 return (core_mode >> 2) & 3;
330 }
331 }
332
333 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
334 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
335
336 extern void armv8_free_reg_cache(struct target *target);
337
338 extern const struct command_registration armv8_command_handlers[];
339
340 #endif /* OPENOCD_TARGET_ARMV8_H */