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aarch64: remove bogus os_border calculation
[openocd.git] / src / target / armv8.c
1 /***************************************************************************
2 * Copyright (C) 2015 by David Ung *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/replacements.h>
24
25 #include "armv8.h"
26 #include "arm_disassembler.h"
27
28 #include "register.h"
29 #include <helper/binarybuffer.h>
30 #include <helper/command.h>
31
32 #include <stdlib.h>
33 #include <string.h>
34 #include <unistd.h>
35
36 #include "armv8_opcodes.h"
37 #include "target.h"
38 #include "target_type.h"
39
40 #define __unused __attribute__((unused))
41
42 static const char * const armv8_state_strings[] = {
43 "AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
44 };
45
46 static const struct {
47 const char *name;
48 unsigned psr;
49 /* For user and system modes, these list indices for all registers.
50 * otherwise they're just indices for the shadow registers and SPSR.
51 */
52 unsigned short n_indices;
53 const uint8_t *indices;
54 } armv8_mode_data[] = {
55 /* These special modes are currently only supported
56 * by ARMv6M and ARMv7M profiles */
57 {
58 .name = "USR",
59 .psr = ARM_MODE_USR,
60 },
61 {
62 .name = "FIQ",
63 .psr = ARM_MODE_FIQ,
64 },
65 {
66 .name = "IRQ",
67 .psr = ARM_MODE_IRQ,
68 },
69 {
70 .name = "SVC",
71 .psr = ARM_MODE_SVC,
72 },
73 {
74 .name = "MON",
75 .psr = ARM_MODE_MON,
76 },
77 {
78 .name = "ABT",
79 .psr = ARM_MODE_ABT,
80 },
81 {
82 .name = "EL0T",
83 .psr = ARMV8_64_EL0T,
84 },
85 {
86 .name = "EL1T",
87 .psr = ARMV8_64_EL1T,
88 },
89 {
90 .name = "EL1H",
91 .psr = ARMV8_64_EL1H,
92 },
93 {
94 .name = "EL2T",
95 .psr = ARMV8_64_EL2T,
96 },
97 {
98 .name = "EL2H",
99 .psr = ARMV8_64_EL2H,
100 },
101 {
102 .name = "EL3T",
103 .psr = ARMV8_64_EL3T,
104 },
105 {
106 .name = "EL3H",
107 .psr = ARMV8_64_EL3H,
108 },
109 };
110
111 /** Map PSR mode bits to the name of an ARM processor operating mode. */
112 const char *armv8_mode_name(unsigned psr_mode)
113 {
114 for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
115 if (armv8_mode_data[i].psr == psr_mode)
116 return armv8_mode_data[i].name;
117 }
118 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
119 return "UNRECOGNIZED";
120 }
121
122 int armv8_mode_to_number(enum arm_mode mode)
123 {
124 switch (mode) {
125 case ARM_MODE_ANY:
126 /* map MODE_ANY to user mode */
127 case ARM_MODE_USR:
128 return 0;
129 case ARM_MODE_FIQ:
130 return 1;
131 case ARM_MODE_IRQ:
132 return 2;
133 case ARM_MODE_SVC:
134 return 3;
135 case ARM_MODE_ABT:
136 return 4;
137 case ARM_MODE_UND:
138 return 5;
139 case ARM_MODE_SYS:
140 return 6;
141 case ARM_MODE_MON:
142 return 7;
143 case ARMV8_64_EL0T:
144 return 8;
145 case ARMV8_64_EL1T:
146 return 9;
147 case ARMV8_64_EL1H:
148 return 10;
149 case ARMV8_64_EL2T:
150 return 11;
151 case ARMV8_64_EL2H:
152 return 12;
153 case ARMV8_64_EL3T:
154 return 13;
155 case ARMV8_64_EL3H:
156 return 14;
157
158 default:
159 LOG_ERROR("invalid mode value encountered %d", mode);
160 return -1;
161 }
162 }
163
164
165 static int armv8_read_core_reg(struct target *target, struct reg *r,
166 int num, enum arm_mode mode)
167 {
168 uint64_t reg_value;
169 int retval;
170 struct arm_reg *armv8_core_reg;
171 struct armv8_common *armv8 = target_to_armv8(target);
172
173 assert(num < (int)armv8->arm.core_cache->num_regs);
174
175 armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
176 retval = armv8->load_core_reg_u64(target,
177 armv8_core_reg->num, &reg_value);
178
179 buf_set_u64(armv8->arm.core_cache->reg_list[num].value, 0, 64, reg_value);
180 armv8->arm.core_cache->reg_list[num].valid = 1;
181 armv8->arm.core_cache->reg_list[num].dirty = 0;
182
183 return retval;
184 }
185
186 #if 0
187 static int armv8_write_core_reg(struct target *target, struct reg *r,
188 int num, enum arm_mode mode, target_addr_t value)
189 {
190 int retval;
191 struct arm_reg *armv8_core_reg;
192 struct armv8_common *armv8 = target_to_armv8(target);
193
194 assert(num < (int)armv8->arm.core_cache->num_regs);
195
196 armv8_core_reg = armv8->arm.core_cache->reg_list[num].arch_info;
197 retval = armv8->store_core_reg_u64(target,
198 armv8_core_reg->num,
199 value);
200 if (retval != ERROR_OK) {
201 LOG_ERROR("JTAG failure");
202 armv8->arm.core_cache->reg_list[num].dirty = armv8->arm.core_cache->reg_list[num].valid;
203 return ERROR_JTAG_DEVICE_ERROR;
204 }
205
206 LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, value);
207 armv8->arm.core_cache->reg_list[num].valid = 1;
208 armv8->arm.core_cache->reg_list[num].dirty = 0;
209
210 return ERROR_OK;
211 }
212 #endif
213
214 /* retrieve core id cluster id */
215 int armv8_read_mpidr(struct armv8_common *armv8)
216 {
217 int retval = ERROR_FAIL;
218 struct arm_dpm *dpm = armv8->arm.dpm;
219 uint32_t mpidr;
220
221 retval = dpm->prepare(dpm);
222 if (retval != ERROR_OK)
223 goto done;
224
225 retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
226 if (retval != ERROR_OK)
227 goto done;
228 if (mpidr & 1<<31) {
229 armv8->multi_processor_system = (mpidr >> 30) & 1;
230 armv8->cluster_id = (mpidr >> 8) & 0xf;
231 armv8->cpu_id = mpidr & 0x3;
232 LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
233 armv8->cluster_id,
234 armv8->cpu_id,
235 armv8->multi_processor_system == 0 ? "multi core" : "mono core");
236
237 } else
238 LOG_ERROR("mpdir not in multiprocessor format");
239
240 done:
241 dpm->finish(dpm);
242 return retval;
243 }
244
245 /**
246 * Configures host-side ARM records to reflect the specified CPSR.
247 * Later, code can use arm_reg_current() to map register numbers
248 * according to how they are exposed by this mode.
249 */
250 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
251 {
252 uint32_t mode = cpsr & 0x1F;
253
254 /* NOTE: this may be called very early, before the register
255 * cache is set up. We can't defend against many errors, in
256 * particular against CPSRs that aren't valid *here* ...
257 */
258 if (arm->cpsr) {
259 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
260 arm->cpsr->valid = 1;
261 arm->cpsr->dirty = 0;
262 }
263
264 /* Older ARMs won't have the J bit */
265 enum arm_state state = 0xFF;
266
267 if (((cpsr & 0x10) >> 4) == 0) {
268 state = ARM_STATE_AARCH64;
269 } else {
270 if (cpsr & (1 << 5)) { /* T */
271 if (cpsr & (1 << 24)) { /* J */
272 LOG_WARNING("ThumbEE -- incomplete support");
273 state = ARM_STATE_THUMB_EE;
274 } else
275 state = ARM_STATE_THUMB;
276 } else {
277 if (cpsr & (1 << 24)) { /* J */
278 LOG_ERROR("Jazelle state handling is BROKEN!");
279 state = ARM_STATE_JAZELLE;
280 } else
281 state = ARM_STATE_ARM;
282 }
283 }
284 arm->core_state = state;
285 if (arm->core_state == ARM_STATE_AARCH64) {
286 switch (mode) {
287 case SYSTEM_AAR64_MODE_EL0t:
288 arm->core_mode = ARMV8_64_EL0T;
289 break;
290 case SYSTEM_AAR64_MODE_EL1t:
291 arm->core_mode = ARMV8_64_EL0T;
292 break;
293 case SYSTEM_AAR64_MODE_EL1h:
294 arm->core_mode = ARMV8_64_EL1H;
295 break;
296 case SYSTEM_AAR64_MODE_EL2t:
297 arm->core_mode = ARMV8_64_EL2T;
298 break;
299 case SYSTEM_AAR64_MODE_EL2h:
300 arm->core_mode = ARMV8_64_EL2H;
301 break;
302 case SYSTEM_AAR64_MODE_EL3t:
303 arm->core_mode = ARMV8_64_EL3T;
304 break;
305 case SYSTEM_AAR64_MODE_EL3h:
306 arm->core_mode = ARMV8_64_EL3H;
307 break;
308 default:
309 LOG_DEBUG("unknow mode 0x%x", (unsigned) (mode));
310 break;
311 }
312 } else {
313 arm->core_mode = mode;
314 }
315
316 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
317 armv8_mode_name(arm->core_mode),
318 armv8_state_strings[arm->core_state]);
319 }
320
321 static void armv8_show_fault_registers32(struct armv8_common *armv8)
322 {
323 uint32_t dfsr, ifsr, dfar, ifar;
324 struct arm_dpm *dpm = armv8->arm.dpm;
325 int retval;
326
327 retval = dpm->prepare(dpm);
328 if (retval != ERROR_OK)
329 return;
330
331 /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
332
333 /* c5/c0 - {data, instruction} fault status registers */
334 retval = dpm->instr_read_data_r0(dpm,
335 T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 0)),
336 &dfsr);
337 if (retval != ERROR_OK)
338 goto done;
339
340 retval = dpm->instr_read_data_r0(dpm,
341 T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 5, 0, 1)),
342 &ifsr);
343 if (retval != ERROR_OK)
344 goto done;
345
346 /* c6/c0 - {data, instruction} fault address registers */
347 retval = dpm->instr_read_data_r0(dpm,
348 T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 0)),
349 &dfar);
350 if (retval != ERROR_OK)
351 goto done;
352
353 retval = dpm->instr_read_data_r0(dpm,
354 T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 6, 0, 2)),
355 &ifar);
356 if (retval != ERROR_OK)
357 goto done;
358
359 LOG_USER("Data fault registers DFSR: %8.8" PRIx32
360 ", DFAR: %8.8" PRIx32, dfsr, dfar);
361 LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
362 ", IFAR: %8.8" PRIx32, ifsr, ifar);
363
364 done:
365 /* (void) */ dpm->finish(dpm);
366 }
367
368 static void armv8_show_fault_registers(struct target *target)
369 {
370 struct armv8_common *armv8 = target_to_armv8(target);
371
372 if (armv8->arm.core_state != ARM_STATE_AARCH64)
373 armv8_show_fault_registers32(armv8);
374 }
375
376 static uint8_t armv8_pa_size(uint32_t ps)
377 {
378 uint8_t ret = 0;
379 switch (ps) {
380 case 0:
381 ret = 32;
382 break;
383 case 1:
384 ret = 36;
385 break;
386 case 2:
387 ret = 40;
388 break;
389 case 3:
390 ret = 42;
391 break;
392 case 4:
393 ret = 44;
394 break;
395 case 5:
396 ret = 48;
397 break;
398 default:
399 LOG_INFO("Unknow physicall address size");
400 break;
401 }
402 return ret;
403 }
404
405 static __unused int armv8_read_ttbcr32(struct target *target)
406 {
407 struct armv8_common *armv8 = target_to_armv8(target);
408 struct arm_dpm *dpm = armv8->arm.dpm;
409 uint32_t ttbcr, ttbcr_n;
410 int retval = dpm->prepare(dpm);
411 if (retval != ERROR_OK)
412 goto done;
413 /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
414 retval = dpm->instr_read_data_r0(dpm,
415 T32_FMTITR(ARMV4_5_MRC(15, 0, 0, 2, 0, 2)),
416 &ttbcr);
417 if (retval != ERROR_OK)
418 goto done;
419
420 LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
421
422 ttbcr_n = ttbcr & 0x7;
423 armv8->armv8_mmu.ttbcr = ttbcr;
424
425 /*
426 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
427 * document # ARM DDI 0406C
428 */
429 armv8->armv8_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
430 armv8->armv8_mmu.ttbr_range[1] = 0xffffffff;
431 armv8->armv8_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
432 armv8->armv8_mmu.ttbr_mask[1] = 0xffffffff << 14;
433
434 LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
435 (ttbcr_n != 0) ? "used" : "not used",
436 armv8->armv8_mmu.ttbr_mask[0],
437 armv8->armv8_mmu.ttbr_mask[1]);
438
439 done:
440 dpm->finish(dpm);
441 return retval;
442 }
443
444 static __unused int armv8_read_ttbcr(struct target *target)
445 {
446 struct armv8_common *armv8 = target_to_armv8(target);
447 struct arm_dpm *dpm = armv8->arm.dpm;
448 struct arm *arm = &armv8->arm;
449 uint32_t ttbcr;
450 uint64_t ttbcr_64;
451
452 int retval = dpm->prepare(dpm);
453 if (retval != ERROR_OK)
454 goto done;
455
456 /* claaer ttrr1_used and ttbr0_mask */
457 memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
458 memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
459
460 switch (arm->core_mode) {
461 case ARMV8_64_EL3H:
462 case ARMV8_64_EL3T:
463 retval = dpm->instr_read_data_r0(dpm,
464 ARMV8_MRS(SYSTEM_TCR_EL3, 0),
465 &ttbcr);
466 retval += dpm->instr_read_data_r0_64(dpm,
467 ARMV8_MRS(SYSTEM_TTBR0_EL3, 0),
468 &armv8->ttbr_base);
469 if (retval != ERROR_OK)
470 goto done;
471 armv8->va_size = 64 - (ttbcr & 0x3F);
472 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
473 armv8->page_size = (ttbcr >> 14) & 3;
474 break;
475 case ARMV8_64_EL2T:
476 case ARMV8_64_EL2H:
477 retval = dpm->instr_read_data_r0(dpm,
478 ARMV8_MRS(SYSTEM_TCR_EL2, 0),
479 &ttbcr);
480 retval += dpm->instr_read_data_r0_64(dpm,
481 ARMV8_MRS(SYSTEM_TTBR0_EL2, 0),
482 &armv8->ttbr_base);
483 if (retval != ERROR_OK)
484 goto done;
485 armv8->va_size = 64 - (ttbcr & 0x3F);
486 armv8->pa_size = armv8_pa_size((ttbcr >> 16) & 7);
487 armv8->page_size = (ttbcr >> 14) & 3;
488 break;
489 case ARMV8_64_EL0T:
490 case ARMV8_64_EL1T:
491 case ARMV8_64_EL1H:
492 retval = dpm->instr_read_data_r0_64(dpm,
493 ARMV8_MRS(SYSTEM_TCR_EL1, 0),
494 &ttbcr_64);
495 armv8->va_size = 64 - (ttbcr_64 & 0x3F);
496 armv8->pa_size = armv8_pa_size((ttbcr_64 >> 32) & 7);
497 armv8->page_size = (ttbcr_64 >> 14) & 3;
498 armv8->armv8_mmu.ttbr1_used = (((ttbcr_64 >> 16) & 0x3F) != 0) ? 1 : 0;
499 armv8->armv8_mmu.ttbr0_mask = 0x0000FFFFFFFFFFFF;
500 retval += dpm->instr_read_data_r0_64(dpm,
501 ARMV8_MRS(SYSTEM_TTBR0_EL1 | (armv8->armv8_mmu.ttbr1_used), 0),
502 &armv8->ttbr_base);
503 if (retval != ERROR_OK)
504 goto done;
505 break;
506 default:
507 LOG_ERROR("unknow core state");
508 retval = ERROR_FAIL;
509 break;
510 }
511 if (retval != ERROR_OK)
512 goto done;
513
514 if (armv8->armv8_mmu.ttbr1_used == 1)
515 LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
516
517 done:
518 dpm->finish(dpm);
519 return retval;
520 }
521
522 /* method adapted to cortex A : reused arm v4 v5 method*/
523 int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
524 {
525 return ERROR_OK;
526 }
527
528 /* V8 method VA TO PA */
529 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
530 target_addr_t *val, int meminfo)
531 {
532 return ERROR_OK;
533 }
534
535 int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
536 struct armv8_cache_common *armv8_cache)
537 {
538 if (armv8_cache->info == -1) {
539 command_print(cmd_ctx, "cache not yet identified");
540 return ERROR_OK;
541 }
542
543 if (armv8_cache->display_cache_info)
544 armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
545 return ERROR_OK;
546 }
547
548 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
549 {
550 struct arm *arm = &armv8->arm;
551 arm->arch_info = armv8;
552 target->arch_info = &armv8->arm;
553 /* target is useful in all function arm v4 5 compatible */
554 armv8->arm.target = target;
555 armv8->arm.common_magic = ARM_COMMON_MAGIC;
556 armv8->common_magic = ARMV8_COMMON_MAGIC;
557
558 arm->read_core_reg = armv8_read_core_reg;
559 #if 0
560 arm->write_core_reg = armv8_write_core_reg;
561 #endif
562
563 armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
564 armv8->armv8_mmu.armv8_cache.info = -1;
565 armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
566 armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
567 return ERROR_OK;
568 }
569
570 int armv8_aarch64_state(struct target *target)
571 {
572 struct arm *arm = target_to_arm(target);
573
574 if (arm->common_magic != ARM_COMMON_MAGIC) {
575 LOG_ERROR("BUG: called for a non-ARM target");
576 return ERROR_FAIL;
577 }
578
579 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
580 "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
581 armv8_state_strings[arm->core_state],
582 debug_reason_name(target),
583 armv8_mode_name(arm->core_mode),
584 buf_get_u32(arm->cpsr->value, 0, 32),
585 buf_get_u64(arm->pc->value, 0, 64),
586 arm->is_semihosting ? ", semihosting" : "");
587
588 return ERROR_OK;
589 }
590
591 int armv8_arch_state(struct target *target)
592 {
593 static const char * const state[] = {
594 "disabled", "enabled"
595 };
596
597 struct armv8_common *armv8 = target_to_armv8(target);
598 struct arm *arm = &armv8->arm;
599
600 if (armv8->common_magic != ARMV8_COMMON_MAGIC) {
601 LOG_ERROR("BUG: called for a non-Armv8 target");
602 return ERROR_COMMAND_SYNTAX_ERROR;
603 }
604
605 if (arm->core_state == ARM_STATE_AARCH64)
606 armv8_aarch64_state(target);
607 else
608 arm_arch_state(target);
609
610 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
611 state[armv8->armv8_mmu.mmu_enabled],
612 state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
613 state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
614
615 if (arm->core_mode == ARM_MODE_ABT)
616 armv8_show_fault_registers(target);
617
618 if (target->debug_reason == DBG_REASON_WATCHPOINT)
619 LOG_USER("Watchpoint triggered at PC %#08x",
620 (unsigned) armv8->dpm.wp_pc);
621
622 return ERROR_OK;
623 }
624
625 static const struct {
626 unsigned id;
627 const char *name;
628 unsigned bits;
629 enum reg_type type;
630 const char *group;
631 const char *feature;
632 } armv8_regs[] = {
633 { ARMV8_R0, "x0", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
634 { ARMV8_R1, "x1", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
635 { ARMV8_R2, "x2", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
636 { ARMV8_R3, "x3", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
637 { ARMV8_R4, "x4", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
638 { ARMV8_R5, "x5", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
639 { ARMV8_R6, "x6", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
640 { ARMV8_R7, "x7", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
641 { ARMV8_R8, "x8", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
642 { ARMV8_R9, "x9", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
643 { ARMV8_R10, "x10", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
644 { ARMV8_R11, "x11", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
645 { ARMV8_R12, "x12", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
646 { ARMV8_R13, "x13", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
647 { ARMV8_R14, "x14", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
648 { ARMV8_R15, "x15", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
649 { ARMV8_R16, "x16", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
650 { ARMV8_R17, "x17", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
651 { ARMV8_R18, "x18", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
652 { ARMV8_R19, "x19", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
653 { ARMV8_R20, "x20", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
654 { ARMV8_R21, "x21", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
655 { ARMV8_R22, "x22", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
656 { ARMV8_R23, "x23", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
657 { ARMV8_R24, "x24", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
658 { ARMV8_R25, "x25", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
659 { ARMV8_R26, "x26", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
660 { ARMV8_R27, "x27", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
661 { ARMV8_R28, "x28", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
662 { ARMV8_R29, "x29", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
663 { ARMV8_R30, "x30", 64, REG_TYPE_UINT64, "general", "org.gnu.gdb.aarch64.core" },
664
665 { ARMV8_R31, "sp", 64, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core" },
666 { ARMV8_PC, "pc", 64, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core" },
667
668 { ARMV8_xPSR, "CPSR", 32, REG_TYPE_UINT32, "general", "org.gnu.gdb.aarch64.core" },
669 };
670
671 #define ARMV8_NUM_REGS ARRAY_SIZE(armv8_regs)
672
673
674 static int armv8_get_core_reg(struct reg *reg)
675 {
676 int retval;
677 struct arm_reg *armv8_reg = reg->arch_info;
678 struct target *target = armv8_reg->target;
679 struct arm *arm = target_to_arm(target);
680
681 if (target->state != TARGET_HALTED)
682 return ERROR_TARGET_NOT_HALTED;
683
684 retval = arm->read_core_reg(target, reg, armv8_reg->num, arm->core_mode);
685
686 return retval;
687 }
688
689 static int armv8_set_core_reg(struct reg *reg, uint8_t *buf)
690 {
691 struct arm_reg *armv8_reg = reg->arch_info;
692 struct target *target = armv8_reg->target;
693 struct arm *arm = target_to_arm(target);
694 uint64_t value = buf_get_u64(buf, 0, 64);
695
696 if (target->state != TARGET_HALTED)
697 return ERROR_TARGET_NOT_HALTED;
698
699 if (reg == arm->cpsr) {
700 armv8_set_cpsr(arm, (uint32_t)value);
701 } else {
702 buf_set_u64(reg->value, 0, 64, value);
703 reg->valid = 1;
704 }
705
706 reg->dirty = 1;
707
708 return ERROR_OK;
709 }
710
711 static const struct reg_arch_type armv8_reg_type = {
712 .get = armv8_get_core_reg,
713 .set = armv8_set_core_reg,
714 };
715
716 /** Builds cache of architecturally defined registers. */
717 struct reg_cache *armv8_build_reg_cache(struct target *target)
718 {
719 struct armv8_common *armv8 = target_to_armv8(target);
720 struct arm *arm = &armv8->arm;
721 int num_regs = ARMV8_NUM_REGS;
722 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
723 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
724 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
725 struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
726 struct reg_feature *feature;
727 int i;
728
729 /* Build the process context cache */
730 cache->name = "arm v8 registers";
731 cache->next = NULL;
732 cache->reg_list = reg_list;
733 cache->num_regs = num_regs;
734 (*cache_p) = cache;
735
736 for (i = 0; i < num_regs; i++) {
737 arch_info[i].num = armv8_regs[i].id;
738 arch_info[i].target = target;
739 arch_info[i].arm = arm;
740
741 reg_list[i].name = armv8_regs[i].name;
742 reg_list[i].size = armv8_regs[i].bits;
743 reg_list[i].value = calloc(1, 8);
744 reg_list[i].dirty = 0;
745 reg_list[i].valid = 0;
746 reg_list[i].type = &armv8_reg_type;
747 reg_list[i].arch_info = &arch_info[i];
748
749 reg_list[i].group = armv8_regs[i].group;
750 reg_list[i].number = i;
751 reg_list[i].exist = true;
752 reg_list[i].caller_save = true; /* gdb defaults to true */
753
754 feature = calloc(1, sizeof(struct reg_feature));
755 if (feature) {
756 feature->name = armv8_regs[i].feature;
757 reg_list[i].feature = feature;
758 } else
759 LOG_ERROR("unable to allocate feature list");
760
761 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
762 if (reg_list[i].reg_data_type)
763 reg_list[i].reg_data_type->type = armv8_regs[i].type;
764 else
765 LOG_ERROR("unable to allocate reg type list");
766 }
767
768 arm->cpsr = reg_list + ARMV8_xPSR;
769 arm->pc = reg_list + ARMV8_PC;
770 arm->core_cache = cache;
771
772 return cache;
773 }
774
775 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
776 {
777 struct reg *r;
778
779 if (regnum > (ARMV8_LAST_REG - 1))
780 return NULL;
781
782 r = arm->core_cache->reg_list + regnum;
783 return r;
784 }
785
786 const struct command_registration armv8_command_handlers[] = {
787 {
788 .chain = dap_command_handlers,
789 },
790 COMMAND_REGISTRATION_DONE
791 };
792
793
794 int armv8_get_gdb_reg_list(struct target *target,
795 struct reg **reg_list[], int *reg_list_size,
796 enum target_register_class reg_class)
797 {
798 struct arm *arm = target_to_arm(target);
799 int i;
800
801 switch (reg_class) {
802 case REG_CLASS_GENERAL:
803 case REG_CLASS_ALL:
804 *reg_list_size = ARMV8_LAST_REG;
805 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
806
807 for (i = 0; i < ARMV8_LAST_REG; i++)
808 (*reg_list)[i] = armv8_reg_current(arm, i);
809
810 return ERROR_OK;
811
812 default:
813 LOG_ERROR("not a valid register class type in query.");
814 return ERROR_FAIL;
815 break;
816 }
817 }
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