1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
29 #include "arm_adi_v5.h"
31 /* define for enabling armv7 gdb workarounds */
33 #define ARMV7_GDB_HACKS
38 ARMV7M_MODE_THREAD
= 0,
39 ARMV7M_MODE_USER_THREAD
= 1,
40 ARMV7M_MODE_HANDLER
= 2,
44 extern char *armv7m_mode_strings
[];
48 ARMV7M_REGISTER_CORE_GP
,
49 ARMV7M_REGISTER_CORE_SP
,
50 ARMV7M_REGISTER_MEMMAP
53 extern char *armv7m_exception_string(int number
);
55 /* offsets into armv7m core register cache */
58 /* for convenience, the first set of indices match
59 * the Cortex-M3 DCRSR selectors
85 /* this next set of indices is arbitrary */
92 #define ARMV7M_COMMON_MAGIC 0x2A452A45
94 typedef struct armv7m_common_s
97 reg_cache_t
*core_cache
;
98 enum armv7m_mode core_mode
;
100 swjdp_common_t swjdp_info
;
103 /* Direct processor core register read and writes */
104 int (*load_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, uint32_t num
, uint32_t *value
);
105 int (*store_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, uint32_t num
, uint32_t value
);
106 /* register cache to processor synchronization */
107 int (*read_core_reg
)(struct target_s
*target
, int num
);
108 int (*write_core_reg
)(struct target_s
*target
, int num
);
110 int (*examine_debug_reason
)(target_t
*target
);
111 void (*post_debug_entry
)(target_t
*target
);
113 void (*pre_restore_context
)(target_t
*target
);
114 void (*post_restore_context
)(target_t
*target
);
119 typedef struct armv7m_algorithm_s
123 enum armv7m_mode core_mode
;
124 } armv7m_algorithm_t
;
126 typedef struct armv7m_core_reg_s
129 enum armv7m_regtype type
;
131 armv7m_common_t
*armv7m_common
;
134 extern reg_cache_t
*armv7m_build_reg_cache(target_t
*target
);
135 extern enum armv7m_mode
armv7m_number_to_mode(int number
);
136 extern int armv7m_mode_to_number(enum armv7m_mode mode
);
138 extern int armv7m_arch_state(struct target_s
*target
);
139 extern int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
);
141 extern int armv7m_register_commands(struct command_context_s
*cmd_ctx
);
142 extern int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
);
144 extern int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, uint32_t entry_point
, uint32_t exit_point
, int timeout_ms
, void *arch_info
);
146 extern int armv7m_invalidate_core_regs(target_t
*target
);
148 extern int armv7m_restore_context(target_t
*target
);
150 extern int armv7m_checksum_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* checksum
);
151 extern int armv7m_blank_check_memory(struct target_s
*target
, uint32_t address
, uint32_t count
, uint32_t* blank
);
153 /* Thumb mode instructions
156 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
157 * Rd: destination register
158 * SYSm: source special register
160 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
162 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
163 * Rd: source register
164 * SYSm: destination special register
166 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
168 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
169 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
170 * Rd: source register
175 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
176 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
178 /* Breakpoint (Thumb mode) v5 onwards
179 * Im: immediate value used by debugger
181 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
183 /* Store register (Thumb mode)
184 * Rd: source register
187 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
189 /* Load register (Thumb state)
190 * Rd: destination register
193 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
195 /* Load multiple (Thumb state)
197 * List: for each bit in list: store register
199 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
201 /* Load register with PC relative addressing
202 * Rd: register to load
204 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
206 /* Move hi register (Thumb mode)
207 * Rd: destination register
208 * Rm: source register
210 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
212 /* No operation (Thumb mode)
214 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
216 /* Move immediate to register (Thumb state)
217 * Rd: destination register
218 * Im: 8-bit immediate value
220 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
222 /* Branch and Exchange
223 * Rm: register containing branch target
225 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
227 /* Branch (Thumb state)
230 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
232 #endif /* ARMV7M_H */
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