src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARMV7M_COMMON_H
  24 #define ARMV7M_COMMON_H
  25
  26 #include "register.h"
  27 #include "target.h"
  28 #include "arm_jtag.h"
  29
  30 enum armv7m_mode
  31 {
  32         ARMV7M_MODE_THREAD = 0,
  33         ARMV7M_MODE_USER_THREAD = 1,
  34         ARMV7M_MODE_HANDLER = 2,
  35         ARMV7M_MODE_ANY = -1
  36 };
  37
  38 extern char* armv7m_mode_strings[];
  39
  40 enum armv7m_regtype
  41 {
  42         ARMV7M_REGISTER_CORE_GP,
  43         ARMV7M_REGISTER_CORE_SP,
  44         ARMV7M_REGISTER_MEMMAP
  45 };
  46
  47 extern char* armv7m_exception_strings[];
  48
  49 extern char *armv7m_exception_string(int number);
  50
  51 /* offsets into armv7m core register cache */
  52 enum
  53 {
  54         ARMV7M_PC = 15,
  55         ARMV7M_xPSR = 16,
  56         ARMV7M_MSP,
  57         ARMV7M_PSP,
  58         ARMV7M_PRIMASK,
  59         ARMV7M_BASEPRI,
  60         ARMV7M_FAULTMASK,
  61         ARMV7M_CONTROL,
  62         ARMV7NUMCOREREGS
  63 };
  64
  65 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  66
  67 typedef struct armv7m_common_s
  68 {
  69         int common_magic;
  70         reg_cache_t *core_cache;
  71         enum armv7m_mode core_mode;
  72         int exception_number;
  73
  74         /* Direct processor core register read and writes */
  75         int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
  76         int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
  77         /* register cache to processor synchronization */
  78         int (*read_core_reg)(struct target_s *target, int num);
  79         int (*write_core_reg)(struct target_s *target, int num);
  80
  81         arm_jtag_t jtag_info;
  82
  83         int (*examine_debug_reason)(target_t *target);
  84         void (*pre_debug_entry)(target_t *target);
  85         void (*post_debug_entry)(target_t *target);
  86
  87         void (*pre_restore_context)(target_t *target);
  88         void (*post_restore_context)(target_t *target);
  89
  90         void *arch_info;
  91 } armv7m_common_t;
  92
  93 typedef struct armv7m_algorithm_s
  94 {
  95         int common_magic;
  96
  97         enum armv7m_mode core_mode;
  98 } armv7m_algorithm_t;
  99
 100 typedef struct armv7m_core_reg_s
 101 {
 102         u32 num;
 103         enum armv7m_regtype type;
 104         enum armv7m_mode mode;
 105         target_t *target;
 106         armv7m_common_t *armv7m_common;
 107 } armv7m_core_reg_t;
 108
 109 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
 110 extern enum armv7m_mode armv7m_number_to_mode(int number);
 111 extern int armv7m_mode_to_number(enum armv7m_mode mode);
 112
 113 extern int armv7m_arch_state(struct target_s *target);
 114 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 115 extern int armv7m_invalidate_core_regs(target_t *target);
 116
 117 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
 118 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 119
 120 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 121
 122 extern int armv7m_invalidate_core_regs(target_t *target);
 123
 124 extern int armv7m_restore_context(target_t *target);
 125
 126 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 127
 128 /* Thumb mode instructions
 129  */
 130
 131 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 132  * Rd: destination register
 133  * SYSm: source special register
 134  */
 135 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
 136
 137 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 138  * Rd: source register
 139  * SYSm: destination special register
 140  */
 141 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
 142
 143 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 144  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 145  * Rd: source register
 146  * IF:
 147  */
 148 #define I_FLAG 2
 149 #define F_FLAG 1
 150 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
 151 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
 152
 153 /* Breakpoint (Thumb mode) v5 onwards
 154  * Im: immediate value used by debugger
 155  */
 156 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
 157
 158 /* Store register (Thumb mode)
 159  * Rd: source register
 160  * Rn: base register
 161  */
 162 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 163
 164 /* Load register (Thumb state)
 165  * Rd: destination register
 166  * Rn: base register
 167  */
 168 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 169
 170 /* Load multiple (Thumb state)
 171  * Rn: base register
 172  * List: for each bit in list: store register
 173  */
 174 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 175
 176 /* Load register with PC relative addressing
 177  * Rd: register to load
 178  */
 179 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 180
 181 /* Move hi register (Thumb mode)
 182  * Rd: destination register
 183  * Rm: source register
 184  */
 185 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 186
 187 /* No operation (Thumb mode)
 188  */
 189 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 190
 191 /* Move immediate to register (Thumb state)
 192  * Rd: destination register
 193  * Im: 8-bit immediate value
 194  */
 195 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 196
 197 /* Branch and Exchange
 198  * Rm: register containing branch target
 199  */
 200 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 201
 202 /* Branch (Thumb state)
 203  * Imm: Branch target
 204  */
 205 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 206
 207 #endif /* ARMV7M_H */