1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifndef ARMV7M_COMMON_H
24 #define ARMV7M_COMMON_H
32 ARMV7M_MODE_HANDLER
= 0,
33 ARMV7M_MODE_THREAD
= 1,
37 extern char* armv7m_mode_strings
[];
47 ARMV7M_REGISTER_CORE_GP
,
48 ARMV7M_REGISTER_CORE_SP
,
49 ARMV7M_REGISTER_MEMMAP
52 enum armv7m_runcontext
54 ARMV7M_PROCESS_CONTEXT
,
58 extern char* armv7m_state_strings
[];
59 extern char* armv7m_exception_strings
[];
61 extern char *armv7m_exception_string(int number
);
63 /* offsets into armv7m core register cache */
77 #define ARMV7M_COMMON_MAGIC 0x2A452A45
79 typedef struct armv7m_common_s
82 reg_cache_t
*core_cache
;
83 reg_cache_t
*process_context
;
84 reg_cache_t
*debug_context
;
85 enum armv7m_mode core_mode
;
86 enum armv7m_state core_state
;
88 int (*full_context
)(struct target_s
*target
);
89 /* Direct processor core register read and writes */
90 int (*load_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, u32 num
, u32
*value
);
91 int (*store_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, u32 num
, u32 value
);
92 /* register cache to processor synchronization */
93 int (*read_core_reg
)(struct target_s
*target
, int num
);
94 int (*write_core_reg
)(struct target_s
*target
, int num
);
95 /* get or set register through cache, return error if target is running and synchronisation is impossible */
96 int (*get_core_reg_32
)(struct target_s
*target
, int num
, u32
* value
);
97 int (*set_core_reg_32
)(struct target_s
*target
, int num
, u32 value
);
100 reg_cache_t
*eice_cache
;
101 reg_cache_t
*etm_cache
;
103 int (*examine_debug_reason
)(target_t
*target
);
105 void (*change_to_arm
)(target_t
*target
, u32
*r0
, u32
*pc
);
107 // void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
108 // void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
109 // void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
112 void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
114 void (*load_word_regs)(target_t *target, u32 mask);
115 void (*load_hword_reg)(target_t *target, int num);
116 void (*load_byte_reg)(target_t *target, int num);
118 void (*store_word_regs)(target_t *target, u32 mask);
119 void (*store_hword_reg)(target_t *target, int num);
120 void (*store_byte_reg)(target_t *target, int num);
122 void (*write_pc)(target_t *target, u32 pc);
123 void (*branch_resume)(target_t *target);
126 void (*pre_debug_entry
)(target_t
*target
);
127 void (*post_debug_entry
)(target_t
*target
);
129 void (*pre_restore_context
)(target_t
*target
);
130 void (*post_restore_context
)(target_t
*target
);
135 typedef struct armv7m_algorithm_s
139 enum armv7m_mode core_mode
;
140 enum armv7m_state core_state
;
141 } armv7m_algorithm_t
;
143 typedef struct armv7m_core_reg_s
146 enum armv7m_regtype type
;
147 enum armv7m_mode mode
;
149 armv7m_common_t
*armv7m_common
;
152 extern reg_cache_t
*armv7m_build_reg_cache(target_t
*target
);
153 extern enum armv7m_mode
armv7m_number_to_mode(int number
);
154 extern int armv7m_mode_to_number(enum armv7m_mode mode
);
156 extern int armv7m_arch_state(struct target_s
*target
);
157 extern int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
);
158 extern int armv7m_invalidate_core_regs(target_t
*target
);
160 extern int armv7m_register_commands(struct command_context_s
*cmd_ctx
);
161 extern int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
);
163 extern int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
);
165 extern int armv7m_invalidate_core_regs(target_t
*target
);
167 extern enum armv7m_runcontext
armv7m_get_context(target_t
*target
);
168 extern int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
);
169 extern enum armv7m_runcontext
armv7m_get_context(target_t
*target
);
170 extern int armv7m_restore_context(target_t
*target
);
172 extern int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
);
174 /* Thumb mode instructions
177 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
178 * Rd: destination register
179 * SYSm: source special register
181 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
183 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
184 * Rd: source register
185 * SYSm: destination special register
187 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
189 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
190 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
191 * Rd: source register
196 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
197 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
199 /* Breakpoint (Thumb mode) v5 onwards
200 * Im: immediate value used by debugger
202 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
204 /* Store register (Thumb mode)
205 * Rd: source register
208 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
210 /* Load register (Thumb state)
211 * Rd: destination register
214 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
216 /* Load multiple (Thumb state)
218 * List: for each bit in list: store register
220 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
222 /* Load register with PC relative addressing
223 * Rd: register to load
225 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
227 /* Move hi register (Thumb mode)
228 * Rd: destination register
229 * Rm: source register
231 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
233 /* No operation (Thumb mode)
235 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
237 /* Move immediate to register (Thumb state)
238 * Rd: destination register
239 * Im: 8-bit immediate value
241 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
243 /* Branch and Exchange
244 * Rm: register containing branch target
246 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
248 /* Branch (Thumb state)
251 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
253 #endif /* ARMV7M_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)