1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifndef ARMV7M_COMMON_H
24 #define ARMV7M_COMMON_H
32 ARMV7M_MODE_HANDLER
= 0,
33 ARMV7M_MODE_THREAD
= 1,
37 extern char* armv7m_mode_strings
[];
47 ARMV7M_REGISTER_CORE_GP
,
48 ARMV7M_REGISTER_CORE_SP
,
49 ARMV7M_REGISTER_MEMMAP
52 enum armv7m_runcontext
54 ARMV7M_PROCESS_CONTEXT
,
58 extern char* armv7m_state_strings
[];
59 extern char* armv7m_exception_strings
[];
61 extern char *armv7m_exception_string(int number
);
63 /* offsets into armv7m core register cache */
77 #define ARMV7M_COMMON_MAGIC 0x2A452A45
79 typedef struct armv7m_common_s
82 reg_cache_t
*core_cache
;
83 reg_cache_t
*process_context
;
84 reg_cache_t
*debug_context
;
85 enum armv7m_mode core_mode
;
86 enum armv7m_state core_state
;
88 int (*full_context
)(struct target_s
*target
);
89 /* Direct processor core register read and writes */
90 int (*load_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, u32 num
, u32
*value
);
91 int (*store_core_reg_u32
)(struct target_s
*target
, enum armv7m_regtype type
, u32 num
, u32 value
);
92 /* register cache to processor synchronization */
93 int (*read_core_reg
)(struct target_s
*target
, int num
);
94 int (*write_core_reg
)(struct target_s
*target
, int num
);
95 /* get or set register through cache, return error if target is running and synchronisation is impossible */
96 int (*get_core_reg_32
)(struct target_s
*target
, int num
, u32
* value
);
97 int (*set_core_reg_32
)(struct target_s
*target
, int num
, u32 value
);
100 reg_cache_t
*eice_cache
;
101 reg_cache_t
*etm_cache
;
103 int (*examine_debug_reason
)(target_t
*target
);
105 void (*change_to_arm
)(target_t
*target
, u32
*r0
, u32
*pc
);
108 void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
109 void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
110 void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
114 void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
116 void (*load_word_regs)(target_t *target, u32 mask);
117 void (*load_hword_reg)(target_t *target, int num);
118 void (*load_byte_reg)(target_t *target, int num);
120 void (*store_word_regs)(target_t *target, u32 mask);
121 void (*store_hword_reg)(target_t *target, int num);
122 void (*store_byte_reg)(target_t *target, int num);
124 void (*write_pc)(target_t *target, u32 pc);
125 void (*branch_resume)(target_t *target);
128 void (*pre_debug_entry
)(target_t
*target
);
129 void (*post_debug_entry
)(target_t
*target
);
131 void (*pre_restore_context
)(target_t
*target
);
132 void (*post_restore_context
)(target_t
*target
);
137 typedef struct armv7m_algorithm_s
141 enum armv7m_mode core_mode
;
142 enum armv7m_state core_state
;
143 } armv7m_algorithm_t
;
145 typedef struct armv7m_core_reg_s
148 enum armv7m_regtype type
;
149 enum armv7m_mode mode
;
151 armv7m_common_t
*armv7m_common
;
154 extern reg_cache_t
*armv7m_build_reg_cache(target_t
*target
);
155 extern enum armv7m_mode
armv7m_number_to_mode(int number
);
156 extern int armv7m_mode_to_number(enum armv7m_mode mode
);
158 extern int armv7m_arch_state(struct target_s
*target
);
159 extern int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
);
160 extern int armv7m_invalidate_core_regs(target_t
*target
);
162 extern int armv7m_register_commands(struct command_context_s
*cmd_ctx
);
163 extern int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
);
165 extern int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
);
167 extern int armv7m_invalidate_core_regs(target_t
*target
);
169 extern enum armv7m_runcontext
armv7m_get_context(target_t
*target
);
170 extern int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
);
171 extern enum armv7m_runcontext
armv7m_get_context(target_t
*target
);
172 extern int armv7m_restore_context(target_t
*target
);
174 extern int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
);
176 /* Thumb mode instructions
179 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
180 * Rd: destination register
181 * SYSm: source special register
183 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
185 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
186 * Rd: source register
187 * SYSm: destination special register
189 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
191 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
192 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
193 * Rd: source register
198 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
199 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
201 /* Breakpoint (Thumb mode) v5 onwards
202 * Im: immediate value used by debugger
204 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
206 /* Store register (Thumb mode)
207 * Rd: source register
210 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
212 /* Load register (Thumb state)
213 * Rd: destination register
216 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
218 /* Load multiple (Thumb state)
220 * List: for each bit in list: store register
222 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
224 /* Load register with PC relative addressing
225 * Rd: register to load
227 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
229 /* Move hi register (Thumb mode)
230 * Rd: destination register
231 * Rm: source register
233 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
235 /* No operation (Thumb mode)
237 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
239 /* Move immediate to register (Thumb state)
240 * Rd: destination register
241 * Im: 8-bit immediate value
243 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
245 /* Branch and Exchange
246 * Rm: register containing branch target
248 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
250 /* Branch (Thumb state)
253 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
255 #endif /* ARMV7M_H */
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