src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2006 by Magnus Lundin                                   *
   5  *   lundin@mlu.mine.nu                                                    *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifndef ARMV7M_COMMON_H
  23 #define ARMV7M_COMMON_H
  24
  25 #include "register.h"
  26 #include "target.h"
  27 #include "arm_jtag.h"
  28
  29
  30 enum armv7m_mode
  31 {
  32         ARMV7M_MODE_HANDLER = 0,
  33         ARMV7M_MODE_THREAD = 1,
  34         ARMV7M_MODE_ANY = -1
  35 };
  36
  37 extern char* armv7m_mode_strings[];
  38
  39 enum armv7m_state
  40 {
  41         ARMV7M_STATE_THUMB,
  42         ARMV7M_STATE_DEBUG,
  43 };
  44
  45 enum armv7m_regtype
  46 {
  47         ARMV7M_REGISTER_CORE_GP,
  48         ARMV7M_REGISTER_CORE_SP,
  49         ARMV7M_REGISTER_MEMMAP
  50 };
  51
  52 enum armv7m_runcontext
  53 {
  54         ARMV7M_PROCESS_CONTEXT,
  55         ARMV7M_DEBUG_CONTEXT
  56 };
  57
  58 extern char* armv7m_state_strings[];
  59
  60 //#define ARMV7NUMCOREREGS 23
  61
  62 /* offsets into armv7m core register cache */
  63 enum
  64 {
  65         ARMV7M_PC = 15,
  66         ARMV7M_xPSR = 16,
  67         ARMV7M_MSP ,
  68         ARMV7M_PSP ,
  69         ARMV7M_PRIMASK ,
  70         ARMV7M_BASEPRI,
  71         ARMV7M_FAULTMASK,
  72         ARMV7M_CONTROL,
  73         ARMV7NUMCOREREGS
  74 };
  75
  76 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  77
  78 typedef struct armv7m_common_s
  79 {
  80         int common_magic;
  81         reg_cache_t *core_cache;
  82         reg_cache_t *process_context;
  83         reg_cache_t *debug_context;
  84         enum armv7m_mode core_mode;
  85         enum armv7m_state core_state;
  86         int  exception_number;
  87         int (*full_context)(struct target_s *target);
  88         /* Direct processor core register read and writes */
  89         int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
  90         int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
  91         /* register cache to processor synchronization */
  92         int (*read_core_reg)(struct target_s *target, int num);
  93         int (*write_core_reg)(struct target_s *target, int num);
  94         /* get or set register through cache, return error if target is running and synchronisation is impossible */
  95         int (*get_core_reg_32)(struct target_s *target, int num, u32* value);
  96         int (*set_core_reg_32)(struct target_s *target, int num, u32 value);
  97
  98         arm_jtag_t jtag_info;
  99         reg_cache_t *eice_cache;
 100         reg_cache_t *etm_cache;
 101
 102         int (*examine_debug_reason)(target_t *target);
 103
 104         void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
 105
 106 //      void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
 107 //      void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
 108 //      void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
 109
 110 /*
 111         void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
 112
 113         void (*load_word_regs)(target_t *target, u32 mask);
 114         void (*load_hword_reg)(target_t *target, int num);
 115         void (*load_byte_reg)(target_t *target, int num);
 116
 117         void (*store_word_regs)(target_t *target, u32 mask);
 118         void (*store_hword_reg)(target_t *target, int num);
 119         void (*store_byte_reg)(target_t *target, int num);
 120
 121         void (*write_pc)(target_t *target, u32 pc);
 122         void (*branch_resume)(target_t *target);
 123 */
 124
 125         void (*pre_debug_entry)(target_t *target);
 126         void (*post_debug_entry)(target_t *target);
 127
 128         void (*pre_restore_context)(target_t *target);
 129         void (*post_restore_context)(target_t *target);
 130
 131         void *arch_info;
 132 } armv7m_common_t;
 133
 134 typedef struct armv7m_algorithm_s
 135 {
 136         int common_magic;
 137
 138         enum armv7m_mode core_mode;
 139         enum armv7m_state core_state;
 140 } armv7m_algorithm_t;
 141
 142 typedef struct armv7m_core_reg_s
 143 {
 144         u32 num;
 145         enum armv7m_regtype type;
 146         enum armv7m_mode mode;
 147         target_t *target;
 148         armv7m_common_t *armv7m_common;
 149 } armv7m_core_reg_t;
 150
 151 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
 152 extern enum armv7m_mode armv7m_number_to_mode(int number);
 153 extern int armv7m_mode_to_number(enum armv7m_mode mode);
 154
 155 extern int armv7m_arch_state(struct target_s *target, char *buf, int buf_size);
 156 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 157 extern int armv7m_invalidate_core_regs(target_t *target);
 158
 159 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
 160 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 161
 162 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 163
 164 extern int armv7m_invalidate_core_regs(target_t *target);
 165
 166
 167
 168
 169 /* Thumb mode instructions
 170  */
 171
 172 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 173  * Rd: destination register
 174  * SYSm: source special register
 175  */
 176 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
 177
 178 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 179  * Rd: source register
 180  * SYSm: destination special register
 181  */
 182 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
 183
 184 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 185  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 186  * Rd: source register
 187  * IF:
 188  */
 189 #define I_FLAG 2
 190 #define F_FLAG 1
 191 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
 192 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
 193
 194 /* Breakpoint (Thumb mode) v5 onwards
 195  * Im: immediate value used by debugger
 196  */
 197 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
 198
 199 /* Store register (Thumb mode)
 200  * Rd: source register
 201  * Rn: base register
 202  */
 203 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 204
 205 /* Load register (Thumb state)
 206  * Rd: destination register
 207  * Rn: base register
 208  */
 209 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 210
 211 /* Load multiple (Thumb state)
 212  * Rn: base register
 213  * List: for each bit in list: store register
 214  */
 215 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 216
 217 /* Load register with PC relative addressing
 218  * Rd: register to load
 219  */
 220 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 221
 222 /* Move hi register (Thumb mode)
 223  * Rd: destination register
 224  * Rm: source register
 225  */
 226 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 227
 228 /* No operation (Thumb mode)
 229  */
 230 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 231
 232 /* Move immediate to register (Thumb state)
 233  * Rd: destination register
 234  * Im: 8-bit immediate value
 235  */
 236 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 237
 238 /* Branch and Exchange
 239  * Rm: register containing branch target
 240  */
 241 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 242
 243 /* Branch (Thumb state)
 244  * Imm: Branch target
 245  */
 246 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 247
 248 #endif /* ARMV7M_H */