Documentation: mention bug database
[openocd.git] / src / target / armv7m.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
28
29 #include "arm_adi_v5.h"
30 #include "arm.h"
31
32 /* define for enabling armv7 gdb workarounds */
33 #if 1
34 #define ARMV7_GDB_HACKS
35 #endif
36
37 #ifdef ARMV7_GDB_HACKS
38 extern uint8_t armv7m_gdb_dummy_cpsr_value[];
39 extern struct reg armv7m_gdb_dummy_cpsr_reg;
40 #endif
41
42
43 enum armv7m_mode
44 {
45 ARMV7M_MODE_THREAD = 0,
46 ARMV7M_MODE_USER_THREAD = 1,
47 ARMV7M_MODE_HANDLER = 2,
48 ARMV7M_MODE_ANY = -1
49 };
50
51 extern char *armv7m_mode_strings[];
52
53 enum armv7m_regtype
54 {
55 ARMV7M_REGISTER_CORE_GP,
56 ARMV7M_REGISTER_CORE_SP,
57 ARMV7M_REGISTER_MEMMAP
58 };
59
60 char *armv7m_exception_string(int number);
61
62 /* offsets into armv7m core register cache */
63 enum
64 {
65 /* for convenience, the first set of indices match
66 * the Cortex-M3 DCRSR selectors
67 */
68 ARMV7M_R0,
69 ARMV7M_R1,
70 ARMV7M_R2,
71 ARMV7M_R3,
72
73 ARMV7M_R4,
74 ARMV7M_R5,
75 ARMV7M_R6,
76 ARMV7M_R7,
77
78 ARMV7M_R8,
79 ARMV7M_R9,
80 ARMV7M_R10,
81 ARMV7M_R11,
82
83 ARMV7M_R12,
84 ARMV7M_R13,
85 ARMV7M_R14,
86 ARMV7M_PC = 15,
87
88 ARMV7M_xPSR = 16,
89 ARMV7M_MSP,
90 ARMV7M_PSP,
91
92 /* this next set of indices is arbitrary */
93 ARMV7M_PRIMASK,
94 ARMV7M_BASEPRI,
95 ARMV7M_FAULTMASK,
96 ARMV7M_CONTROL,
97 };
98
99 #define ARMV7M_COMMON_MAGIC 0x2A452A45
100
101 struct armv7m_common
102 {
103 int common_magic;
104 struct reg_cache *core_cache;
105 enum armv7m_mode core_mode;
106 int exception_number;
107 struct swjdp_common swjdp_info;
108
109 uint32_t demcr;
110
111 /* Direct processor core register read and writes */
112 int (*load_core_reg_u32)(struct target *target,
113 enum armv7m_regtype type, uint32_t num, uint32_t *value);
114 int (*store_core_reg_u32)(struct target *target,
115 enum armv7m_regtype type, uint32_t num, uint32_t value);
116
117 /* register cache to processor synchronization */
118 int (*read_core_reg)(struct target *target, unsigned num);
119 int (*write_core_reg)(struct target *target, unsigned num);
120
121 int (*examine_debug_reason)(struct target *target);
122 void (*post_debug_entry)(struct target *target);
123
124 void (*pre_restore_context)(struct target *target);
125 void (*post_restore_context)(struct target *target);
126 };
127
128 static inline struct armv7m_common *
129 target_to_armv7m(struct target *target)
130 {
131 return target->arch_info;
132 }
133
134 struct armv7m_algorithm
135 {
136 int common_magic;
137
138 enum armv7m_mode core_mode;
139 };
140
141 struct armv7m_core_reg
142 {
143 uint32_t num;
144 enum armv7m_regtype type;
145 struct target *target;
146 struct armv7m_common *armv7m_common;
147 };
148
149 struct reg_cache *armv7m_build_reg_cache(struct target *target);
150 enum armv7m_mode armv7m_number_to_mode(int number);
151 int armv7m_mode_to_number(enum armv7m_mode mode);
152
153 int armv7m_arch_state(struct target *target);
154 int armv7m_get_gdb_reg_list(struct target *target,
155 struct reg **reg_list[], int *reg_list_size);
156
157 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
158
159 int armv7m_run_algorithm(struct target *target,
160 int num_mem_params, struct mem_param *mem_params,
161 int num_reg_params, struct reg_param *reg_params,
162 uint32_t entry_point, uint32_t exit_point,
163 int timeout_ms, void *arch_info);
164
165 int armv7m_invalidate_core_regs(struct target *target);
166
167 int armv7m_restore_context(struct target *target);
168
169 int armv7m_checksum_memory(struct target *target,
170 uint32_t address, uint32_t count, uint32_t* checksum);
171 int armv7m_blank_check_memory(struct target *target,
172 uint32_t address, uint32_t count, uint32_t* blank);
173
174 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
175
176 extern const struct command_registration armv7m_command_handlers[];
177
178 #endif /* ARMV7M_H */

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)