src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV7M_COMMON_H
  27 #define ARMV7M_COMMON_H
  28
  29 #include "register.h"
  30 #include "target.h"
  31 #include "arm_jtag.h"
  32
  33 /* define for enabling armv7 gdb workarounds */
  34 #if 1
  35 #define ARMV7_GDB_HACKS
  36 #endif
  37
  38 enum armv7m_mode
  39 {
  40         ARMV7M_MODE_THREAD = 0,
  41         ARMV7M_MODE_USER_THREAD = 1,
  42         ARMV7M_MODE_HANDLER = 2,
  43         ARMV7M_MODE_ANY = -1
  44 };
  45
  46 extern char* armv7m_mode_strings[];
  47
  48 enum armv7m_regtype
  49 {
  50         ARMV7M_REGISTER_CORE_GP,
  51         ARMV7M_REGISTER_CORE_SP,
  52         ARMV7M_REGISTER_MEMMAP
  53 };
  54
  55 extern char* armv7m_exception_strings[];
  56
  57 extern char *armv7m_exception_string(int number);
  58
  59 /* offsets into armv7m core register cache */
  60 enum
  61 {
  62         ARMV7M_PC = 15,
  63         ARMV7M_xPSR = 16,
  64         ARMV7M_MSP,
  65         ARMV7M_PSP,
  66         ARMV7M_PRIMASK,
  67         ARMV7M_BASEPRI,
  68         ARMV7M_FAULTMASK,
  69         ARMV7M_CONTROL,
  70         ARMV7NUMCOREREGS
  71 };
  72
  73 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  74
  75 typedef struct armv7m_common_s
  76 {
  77         int common_magic;
  78         reg_cache_t *core_cache;
  79         enum armv7m_mode core_mode;
  80         int exception_number;
  81
  82         /* Direct processor core register read and writes */
  83         int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
  84         int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
  85         /* register cache to processor synchronization */
  86         int (*read_core_reg)(struct target_s *target, int num);
  87         int (*write_core_reg)(struct target_s *target, int num);
  88
  89         int (*examine_debug_reason)(target_t *target);
  90         void (*pre_debug_entry)(target_t *target);
  91         void (*post_debug_entry)(target_t *target);
  92
  93         void (*pre_restore_context)(target_t *target);
  94         void (*post_restore_context)(target_t *target);
  95
  96         void *arch_info;
  97 } armv7m_common_t;
  98
  99 typedef struct armv7m_algorithm_s
 100 {
 101         int common_magic;
 102
 103         enum armv7m_mode core_mode;
 104 } armv7m_algorithm_t;
 105
 106 typedef struct armv7m_core_reg_s
 107 {
 108         u32 num;
 109         enum armv7m_regtype type;
 110         enum armv7m_mode mode;
 111         target_t *target;
 112         armv7m_common_t *armv7m_common;
 113 } armv7m_core_reg_t;
 114
 115 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
 116 extern enum armv7m_mode armv7m_number_to_mode(int number);
 117 extern int armv7m_mode_to_number(enum armv7m_mode mode);
 118
 119 extern int armv7m_arch_state(struct target_s *target);
 120 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 121 extern int armv7m_invalidate_core_regs(target_t *target);
 122
 123 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
 124 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
 125
 126 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
 127
 128 extern int armv7m_invalidate_core_regs(target_t *target);
 129
 130 extern int armv7m_restore_context(target_t *target);
 131
 132 extern int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
 133 extern int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
 134
 135 /* Thumb mode instructions
 136  */
 137
 138 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 139  * Rd: destination register
 140  * SYSm: source special register
 141  */
 142 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
 143
 144 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 145  * Rd: source register
 146  * SYSm: destination special register
 147  */
 148 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
 149
 150 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 151  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 152  * Rd: source register
 153  * IF:
 154  */
 155 #define I_FLAG 2
 156 #define F_FLAG 1
 157 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
 158 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
 159
 160 /* Breakpoint (Thumb mode) v5 onwards
 161  * Im: immediate value used by debugger
 162  */
 163 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
 164
 165 /* Store register (Thumb mode)
 166  * Rd: source register
 167  * Rn: base register
 168  */
 169 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 170
 171 /* Load register (Thumb state)
 172  * Rd: destination register
 173  * Rn: base register
 174  */
 175 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 176
 177 /* Load multiple (Thumb state)
 178  * Rn: base register
 179  * List: for each bit in list: store register
 180  */
 181 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 182
 183 /* Load register with PC relative addressing
 184  * Rd: register to load
 185  */
 186 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 187
 188 /* Move hi register (Thumb mode)
 189  * Rd: destination register
 190  * Rm: source register
 191  */
 192 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 193
 194 /* No operation (Thumb mode)
 195  */
 196 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 197
 198 /* Move immediate to register (Thumb state)
 199  * Rd: destination register
 200  * Im: 8-bit immediate value
 201  */
 202 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 203
 204 /* Branch and Exchange
 205  * Rm: register containing branch target
 206  */
 207 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 208
 209 /* Branch (Thumb state)
 210  * Imm: Branch target
 211  */
 212 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 213
 214 #endif /* ARMV7M_H */