- Fixes '<<' whitespace
[openocd.git] / src / target / armv7m.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifndef ARMV7M_COMMON_H
27 #define ARMV7M_COMMON_H
28
29 #include "arm_adi_v5.h"
30
31 /* define for enabling armv7 gdb workarounds */
32 #if 1
33 #define ARMV7_GDB_HACKS
34 #endif
35
36 enum armv7m_mode
37 {
38 ARMV7M_MODE_THREAD = 0,
39 ARMV7M_MODE_USER_THREAD = 1,
40 ARMV7M_MODE_HANDLER = 2,
41 ARMV7M_MODE_ANY = -1
42 };
43
44 extern char* armv7m_mode_strings[];
45
46 enum armv7m_regtype
47 {
48 ARMV7M_REGISTER_CORE_GP,
49 ARMV7M_REGISTER_CORE_SP,
50 ARMV7M_REGISTER_MEMMAP
51 };
52
53 extern char* armv7m_exception_strings[];
54
55 extern char *armv7m_exception_string(int number);
56
57 /* offsets into armv7m core register cache */
58 enum
59 {
60 ARMV7M_PC = 15,
61 ARMV7M_xPSR = 16,
62 ARMV7M_MSP,
63 ARMV7M_PSP,
64 ARMV7M_PRIMASK,
65 ARMV7M_BASEPRI,
66 ARMV7M_FAULTMASK,
67 ARMV7M_CONTROL,
68 ARMV7NUMCOREREGS
69 };
70
71 #define ARMV7M_COMMON_MAGIC 0x2A452A45
72
73 typedef struct armv7m_common_s
74 {
75 int common_magic;
76 reg_cache_t *core_cache;
77 enum armv7m_mode core_mode;
78 int exception_number;
79 swjdp_common_t swjdp_info;
80
81
82 /* Direct processor core register read and writes */
83 int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
84 int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
85 /* register cache to processor synchronization */
86 int (*read_core_reg)(struct target_s *target, int num);
87 int (*write_core_reg)(struct target_s *target, int num);
88
89 int (*examine_debug_reason)(target_t *target);
90 void (*pre_debug_entry)(target_t *target);
91 void (*post_debug_entry)(target_t *target);
92
93 void (*pre_restore_context)(target_t *target);
94 void (*post_restore_context)(target_t *target);
95
96 void *arch_info;
97 } armv7m_common_t;
98
99 typedef struct armv7m_algorithm_s
100 {
101 int common_magic;
102
103 enum armv7m_mode core_mode;
104 } armv7m_algorithm_t;
105
106 typedef struct armv7m_core_reg_s
107 {
108 uint32_t num;
109 enum armv7m_regtype type;
110 enum armv7m_mode mode;
111 target_t *target;
112 armv7m_common_t *armv7m_common;
113 } armv7m_core_reg_t;
114
115 extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
116 extern enum armv7m_mode armv7m_number_to_mode(int number);
117 extern int armv7m_mode_to_number(enum armv7m_mode mode);
118
119 extern int armv7m_arch_state(struct target_s *target);
120 extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
121
122 extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
123 extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
124
125 extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
126
127 extern int armv7m_invalidate_core_regs(target_t *target);
128
129 extern int armv7m_restore_context(target_t *target);
130
131 extern int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
132 extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
133
134 /* Thumb mode instructions
135 */
136
137 /* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
138 * Rd: destination register
139 * SYSm: source special register
140 */
141 #define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
142
143 /* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
144 * Rd: source register
145 * SYSm: destination special register
146 */
147 #define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16))
148
149 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
150 * special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
151 * Rd: source register
152 * IF:
153 */
154 #define I_FLAG 2
155 #define F_FLAG 1
156 #define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
157 #define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
158
159 /* Breakpoint (Thumb mode) v5 onwards
160 * Im: immediate value used by debugger
161 */
162 #define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
163
164 /* Store register (Thumb mode)
165 * Rd: source register
166 * Rn: base register
167 */
168 #define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
169
170 /* Load register (Thumb state)
171 * Rd: destination register
172 * Rn: base register
173 */
174 #define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
175
176 /* Load multiple (Thumb state)
177 * Rn: base register
178 * List: for each bit in list: store register
179 */
180 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
181
182 /* Load register with PC relative addressing
183 * Rd: register to load
184 */
185 #define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
186
187 /* Move hi register (Thumb mode)
188 * Rd: destination register
189 * Rm: source register
190 */
191 #define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
192
193 /* No operation (Thumb mode)
194 */
195 #define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
196
197 /* Move immediate to register (Thumb state)
198 * Rd: destination register
199 * Im: 8-bit immediate value
200 */
201 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
202
203 /* Branch and Exchange
204 * Rm: register containing branch target
205 */
206 #define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
207
208 /* Branch (Thumb state)
209 * Imm: Branch target
210 */
211 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
212
213 #endif /* ARMV7M_H */