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target: don't implicitly include "algorithm.h"
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
31 * *
32 ***************************************************************************/
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36
37 #include "breakpoints.h"
38 #include "armv7m.h"
39 #include "algorithm.h"
40
41 #define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
42
43
44 #if 0
45 #define _DEBUG_INSTRUCTION_EXECUTION_
46 #endif
47
48 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
49 char *armv7m_mode_strings[] =
50 {
51 "Thread", "Thread (User)", "Handler",
52 };
53
54 static char *armv7m_exception_strings[] =
55 {
56 "", "Reset", "NMI", "HardFault",
57 "MemManage", "BusFault", "UsageFault", "RESERVED",
58 "RESERVED", "RESERVED", "RESERVED", "SVCall",
59 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
60 };
61
62 /* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a
63 * ones... except for naming/scoping
64 */
65 static uint8_t armv7m_gdb_dummy_fp_value[12];
66
67 static struct reg armv7m_gdb_dummy_fp_reg =
68 {
69 .name = "GDB dummy floating-point register",
70 .value = armv7m_gdb_dummy_fp_value,
71 .dirty = 0,
72 .valid = 1,
73 .size = 96,
74 .arch_info = NULL,
75 .arch_type = 0,
76 };
77
78 static uint8_t armv7m_gdb_dummy_fps_value[4];
79
80 static struct reg armv7m_gdb_dummy_fps_reg =
81 {
82 .name = "GDB dummy floating-point status register",
83 .value = armv7m_gdb_dummy_fps_value,
84 .dirty = 0,
85 .valid = 1,
86 .size = 32,
87 .arch_info = NULL,
88 .arch_type = 0,
89 };
90
91 #ifdef ARMV7_GDB_HACKS
92 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
93
94 struct reg armv7m_gdb_dummy_cpsr_reg =
95 {
96 .name = "GDB dummy cpsr register",
97 .value = armv7m_gdb_dummy_cpsr_value,
98 .dirty = 0,
99 .valid = 1,
100 .size = 32,
101 .arch_info = NULL,
102 .arch_type = 0,
103 };
104 #endif
105
106 /*
107 * These registers are not memory-mapped. The ARMv7-M profile includes
108 * memory mapped registers too, such as for the NVIC (interrupt controller)
109 * and SysTick (timer) modules; those can mostly be treated as peripherals.
110 *
111 * The ARMv6-M profile is almost identical in this respect, except that it
112 * doesn't include basepri or faultmask registers.
113 */
114 static const struct {
115 unsigned id;
116 char *name;
117 unsigned bits;
118 } armv7m_regs[] = {
119 { ARMV7M_R0, "r0", 32 },
120 { ARMV7M_R1, "r1", 32 },
121 { ARMV7M_R2, "r2", 32 },
122 { ARMV7M_R3, "r3", 32 },
123
124 { ARMV7M_R4, "r4", 32 },
125 { ARMV7M_R5, "r5", 32 },
126 { ARMV7M_R6, "r6", 32 },
127 { ARMV7M_R7, "r7", 32 },
128
129 { ARMV7M_R8, "r8", 32 },
130 { ARMV7M_R9, "r9", 32 },
131 { ARMV7M_R10, "r10", 32 },
132 { ARMV7M_R11, "r11", 32 },
133
134 { ARMV7M_R12, "r12", 32 },
135 { ARMV7M_R13, "sp", 32 },
136 { ARMV7M_R14, "lr", 32 },
137 { ARMV7M_PC, "pc", 32 },
138
139 { ARMV7M_xPSR, "xPSR", 32 },
140 { ARMV7M_MSP, "msp", 32 },
141 { ARMV7M_PSP, "psp", 32 },
142
143 { ARMV7M_PRIMASK, "primask", 1 },
144 { ARMV7M_BASEPRI, "basepri", 8 },
145 { ARMV7M_FAULTMASK, "faultmask", 1 },
146 { ARMV7M_CONTROL, "control", 2 },
147 };
148
149 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
150
151 static int armv7m_core_reg_arch_type = -1;
152
153 /**
154 * Restores target context using the cache of core registers set up
155 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
156 */
157 int armv7m_restore_context(struct target *target)
158 {
159 int i;
160 struct armv7m_common *armv7m = target_to_armv7m(target);
161
162 LOG_DEBUG(" ");
163
164 if (armv7m->pre_restore_context)
165 armv7m->pre_restore_context(target);
166
167 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
168 {
169 if (armv7m->core_cache->reg_list[i].dirty)
170 {
171 armv7m->write_core_reg(target, i);
172 }
173 }
174
175 if (armv7m->post_restore_context)
176 armv7m->post_restore_context(target);
177
178 return ERROR_OK;
179 }
180
181 /* Core state functions */
182
183 /**
184 * Maps ISR number (from xPSR) to name.
185 * Note that while names and meanings for the first sixteen are standardized
186 * (with zero not a true exception), external interrupts are only numbered.
187 * They are assigned by vendors, which generally assign different numbers to
188 * peripherals (such as UART0 or a USB peripheral controller).
189 */
190 char *armv7m_exception_string(int number)
191 {
192 static char enamebuf[32];
193
194 if ((number < 0) | (number > 511))
195 return "Invalid exception";
196 if (number < 16)
197 return armv7m_exception_strings[number];
198 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
199 return enamebuf;
200 }
201
202 static int armv7m_get_core_reg(struct reg *reg)
203 {
204 int retval;
205 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
206 struct target *target = armv7m_reg->target;
207 struct armv7m_common *armv7m = target_to_armv7m(target);
208
209 if (target->state != TARGET_HALTED)
210 {
211 return ERROR_TARGET_NOT_HALTED;
212 }
213
214 retval = armv7m->read_core_reg(target, armv7m_reg->num);
215
216 return retval;
217 }
218
219 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
220 {
221 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
222 struct target *target = armv7m_reg->target;
223 uint32_t value = buf_get_u32(buf, 0, 32);
224
225 if (target->state != TARGET_HALTED)
226 {
227 return ERROR_TARGET_NOT_HALTED;
228 }
229
230 buf_set_u32(reg->value, 0, 32, value);
231 reg->dirty = 1;
232 reg->valid = 1;
233
234 return ERROR_OK;
235 }
236
237 static int armv7m_read_core_reg(struct target *target, int num)
238 {
239 uint32_t reg_value;
240 int retval;
241 struct armv7m_core_reg * armv7m_core_reg;
242 struct armv7m_common *armv7m = target_to_armv7m(target);
243
244 if ((num < 0) || (num >= ARMV7M_NUM_REGS))
245 return ERROR_INVALID_ARGUMENTS;
246
247 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
248 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
249 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
250 armv7m->core_cache->reg_list[num].valid = 1;
251 armv7m->core_cache->reg_list[num].dirty = 0;
252
253 return retval;
254 }
255
256 static int armv7m_write_core_reg(struct target *target, int num)
257 {
258 int retval;
259 uint32_t reg_value;
260 struct armv7m_core_reg *armv7m_core_reg;
261 struct armv7m_common *armv7m = target_to_armv7m(target);
262
263 if ((num < 0) || (num >= ARMV7M_NUM_REGS))
264 return ERROR_INVALID_ARGUMENTS;
265
266 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
267 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
268 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
269 if (retval != ERROR_OK)
270 {
271 LOG_ERROR("JTAG failure");
272 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
273 return ERROR_JTAG_DEVICE_ERROR;
274 }
275 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
276 armv7m->core_cache->reg_list[num].valid = 1;
277 armv7m->core_cache->reg_list[num].dirty = 0;
278
279 return ERROR_OK;
280 }
281
282 /** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
283 int armv7m_invalidate_core_regs(struct target *target)
284 {
285 struct armv7m_common *armv7m = target_to_armv7m(target);
286 int i;
287
288 for (i = 0; i < armv7m->core_cache->num_regs; i++)
289 {
290 armv7m->core_cache->reg_list[i].valid = 0;
291 armv7m->core_cache->reg_list[i].dirty = 0;
292 }
293
294 return ERROR_OK;
295 }
296
297 /**
298 * Returns generic ARM userspace registers to GDB.
299 * GDB doesn't quite understand that most ARMs don't have floating point
300 * hardware, so this also fakes a set of long-obsolete FPA registers that
301 * are not used in EABI based software stacks.
302 */
303 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
304 {
305 struct armv7m_common *armv7m = target_to_armv7m(target);
306 int i;
307
308 *reg_list_size = 26;
309 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
310
311 /*
312 * GDB register packet format for ARM:
313 * - the first 16 registers are r0..r15
314 * - (obsolete) 8 FPA registers
315 * - (obsolete) FPA status
316 * - CPSR
317 */
318 for (i = 0; i < 16; i++)
319 {
320 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
321 }
322
323 for (i = 16; i < 24; i++)
324 {
325 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
326 }
327
328 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
329
330 #ifdef ARMV7_GDB_HACKS
331 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
332 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
333
334 /* ARMV7M is always in thumb mode, try to make GDB understand this
335 * if it does not support this arch */
336 *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
337 #else
338 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
339 #endif
340
341 return ERROR_OK;
342 }
343
344 /* run to exit point. return error if exit point was not reached. */
345 static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
346 {
347 uint32_t pc;
348 int retval;
349 /* This code relies on the target specific resume() and poll()->debug_entry()
350 * sequence to write register values to the processor and the read them back */
351 if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
352 {
353 return retval;
354 }
355
356 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
357 /* If the target fails to halt due to the breakpoint, force a halt */
358 if (retval != ERROR_OK || target->state != TARGET_HALTED)
359 {
360 if ((retval = target_halt(target)) != ERROR_OK)
361 return retval;
362 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
363 {
364 return retval;
365 }
366 return ERROR_TARGET_TIMEOUT;
367 }
368
369 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
370 if (pc != exit_point)
371 {
372 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
373 return ERROR_TARGET_TIMEOUT;
374 }
375
376 return ERROR_OK;
377 }
378
379 /** Runs a Thumb algorithm in the target. */
380 int armv7m_run_algorithm(struct target *target,
381 int num_mem_params, struct mem_param *mem_params,
382 int num_reg_params, struct reg_param *reg_params,
383 uint32_t entry_point, uint32_t exit_point,
384 int timeout_ms, void *arch_info)
385 {
386 struct armv7m_common *armv7m = target_to_armv7m(target);
387 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
388 enum armv7m_mode core_mode = armv7m->core_mode;
389 int retval = ERROR_OK;
390 int i;
391 uint32_t context[ARMV7M_NUM_REGS];
392
393 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
394 {
395 LOG_ERROR("current target isn't an ARMV7M target");
396 return ERROR_TARGET_INVALID;
397 }
398
399 if (target->state != TARGET_HALTED)
400 {
401 LOG_WARNING("target not halted");
402 return ERROR_TARGET_NOT_HALTED;
403 }
404
405 /* refresh core register cache */
406 /* Not needed if core register cache is always consistent with target process state */
407 for (i = 0; i < ARMV7M_NUM_REGS; i++)
408 {
409 if (!armv7m->core_cache->reg_list[i].valid)
410 armv7m->read_core_reg(target, i);
411 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
412 }
413
414 for (i = 0; i < num_mem_params; i++)
415 {
416 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
417 return retval;
418 }
419
420 for (i = 0; i < num_reg_params; i++)
421 {
422 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
423 // uint32_t regvalue;
424
425 if (!reg)
426 {
427 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
428 exit(-1);
429 }
430
431 if (reg->size != reg_params[i].size)
432 {
433 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
434 exit(-1);
435 }
436
437 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
438 armv7m_set_core_reg(reg, reg_params[i].value);
439 }
440
441 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
442 {
443 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
444 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
445 0, 1, armv7m_algorithm_info->core_mode);
446 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
447 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
448 }
449
450 /* REVISIT speed things up (3% or so in one case) by requiring
451 * algorithms to include a BKPT instruction at each exit point.
452 * This eliminates overheads of adding/removing a breakpoint.
453 */
454
455 /* ARMV7M always runs in Thumb state */
456 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
457 {
458 LOG_ERROR("can't add breakpoint to finish algorithm execution");
459 return ERROR_TARGET_FAILURE;
460 }
461
462 retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
463
464 breakpoint_remove(target, exit_point);
465
466 if (retval != ERROR_OK)
467 {
468 return retval;
469 }
470
471 /* Read memory values to mem_params[] */
472 for (i = 0; i < num_mem_params; i++)
473 {
474 if (mem_params[i].direction != PARAM_OUT)
475 if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
476 {
477 return retval;
478 }
479 }
480
481 /* Copy core register values to reg_params[] */
482 for (i = 0; i < num_reg_params; i++)
483 {
484 if (reg_params[i].direction != PARAM_OUT)
485 {
486 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
487
488 if (!reg)
489 {
490 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
491 exit(-1);
492 }
493
494 if (reg->size != reg_params[i].size)
495 {
496 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
497 exit(-1);
498 }
499
500 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
501 }
502 }
503
504 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
505 {
506 uint32_t regvalue;
507 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
508 if (regvalue != context[i])
509 {
510 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
511 armv7m->core_cache->reg_list[i].name, context[i]);
512 buf_set_u32(armv7m->core_cache->reg_list[i].value,
513 0, 32, context[i]);
514 armv7m->core_cache->reg_list[i].valid = 1;
515 armv7m->core_cache->reg_list[i].dirty = 1;
516 }
517 }
518
519 armv7m->core_mode = core_mode;
520
521 return retval;
522 }
523
524 /** Logs summary of ARMv7-M state for a halted target. */
525 int armv7m_arch_state(struct target *target)
526 {
527 struct armv7m_common *armv7m = target_to_armv7m(target);
528 uint32_t ctrl, sp;
529
530 ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
531 sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
532
533 LOG_USER("target halted due to %s, current mode: %s %s\n"
534 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
535 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
536 target->debug_reason)->name,
537 armv7m_mode_strings[armv7m->core_mode],
538 armv7m_exception_string(armv7m->exception_number),
539 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
540 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
541 (ctrl & 0x02) ? 'p' : 'm',
542 sp);
543
544 return ERROR_OK;
545 }
546
547 /** Builds cache of architecturally defined registers. */
548 struct reg_cache *armv7m_build_reg_cache(struct target *target)
549 {
550 struct armv7m_common *armv7m = target_to_armv7m(target);
551 int num_regs = ARMV7M_NUM_REGS;
552 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
553 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
554 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
555 struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
556 int i;
557
558 if (armv7m_core_reg_arch_type == -1)
559 {
560 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
561 }
562
563 register_init_dummy(&armv7m_gdb_dummy_fps_reg);
564 #ifdef ARMV7_GDB_HACKS
565 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
566 #endif
567 register_init_dummy(&armv7m_gdb_dummy_fp_reg);
568
569 /* Build the process context cache */
570 cache->name = "arm v7m registers";
571 cache->next = NULL;
572 cache->reg_list = reg_list;
573 cache->num_regs = num_regs;
574 (*cache_p) = cache;
575 armv7m->core_cache = cache;
576
577 for (i = 0; i < num_regs; i++)
578 {
579 arch_info[i].num = armv7m_regs[i].id;
580 arch_info[i].target = target;
581 arch_info[i].armv7m_common = armv7m;
582 reg_list[i].name = armv7m_regs[i].name;
583 reg_list[i].size = armv7m_regs[i].bits;
584 reg_list[i].value = calloc(1, 4);
585 reg_list[i].dirty = 0;
586 reg_list[i].valid = 0;
587 reg_list[i].arch_type = armv7m_core_reg_arch_type;
588 reg_list[i].arch_info = &arch_info[i];
589 }
590
591 return cache;
592 }
593
594 /** Sets up target as a generic ARMv7-M core */
595 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
596 {
597 /* register arch-specific functions */
598
599 target->arch_info = armv7m;
600 armv7m->read_core_reg = armv7m_read_core_reg;
601 armv7m->write_core_reg = armv7m_write_core_reg;
602
603 return ERROR_OK;
604 }
605
606 /** Generates a CRC32 checksum of a memory region. */
607 int armv7m_checksum_memory(struct target *target,
608 uint32_t address, uint32_t count, uint32_t* checksum)
609 {
610 struct working_area *crc_algorithm;
611 struct armv7m_algorithm armv7m_info;
612 struct reg_param reg_params[2];
613 int retval;
614
615 static const uint16_t cortex_m3_crc_code[] = {
616 0x4602, /* mov r2, r0 */
617 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
618 0x460B, /* mov r3, r1 */
619 0xF04F, 0x0400, /* mov r4, #0 */
620 0xE013, /* b ncomp */
621 /* nbyte: */
622 0x5D11, /* ldrb r1, [r2, r4] */
623 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
624 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
625
626 0xF04F, 0x0500, /* mov r5, #0 */
627 /* loop: */
628 0x2800, /* cmp r0, #0 */
629 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
630 0xF105, 0x0501, /* add r5, r5, #1 */
631 0x4630, /* mov r0, r6 */
632 0xBFB8, /* it lt */
633 0xEA86, 0x0007, /* eor r0, r6, r7 */
634 0x2D08, /* cmp r5, #8 */
635 0xD1F4, /* bne loop */
636
637 0xF104, 0x0401, /* add r4, r4, #1 */
638 /* ncomp: */
639 0x429C, /* cmp r4, r3 */
640 0xD1E9, /* bne nbyte */
641 /* end: */
642 0xE7FE, /* b end */
643 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
644 };
645
646 uint32_t i;
647
648 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
649 {
650 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
651 }
652
653 /* convert flash writing code into a buffer in target endianness */
654 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
655 if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
656 {
657 return retval;
658 }
659
660 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
661 armv7m_info.core_mode = ARMV7M_MODE_ANY;
662
663 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
664 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
665
666 buf_set_u32(reg_params[0].value, 0, 32, address);
667 buf_set_u32(reg_params[1].value, 0, 32, count);
668
669 if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
670 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
671 {
672 LOG_ERROR("error executing cortex_m3 crc algorithm");
673 destroy_reg_param(&reg_params[0]);
674 destroy_reg_param(&reg_params[1]);
675 target_free_working_area(target, crc_algorithm);
676 return retval;
677 }
678
679 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
680
681 destroy_reg_param(&reg_params[0]);
682 destroy_reg_param(&reg_params[1]);
683
684 target_free_working_area(target, crc_algorithm);
685
686 return ERROR_OK;
687 }
688
689 /** Checks whether a memory region is zeroed. */
690 int armv7m_blank_check_memory(struct target *target,
691 uint32_t address, uint32_t count, uint32_t* blank)
692 {
693 struct working_area *erase_check_algorithm;
694 struct reg_param reg_params[3];
695 struct armv7m_algorithm armv7m_info;
696 int retval;
697 uint32_t i;
698
699 static const uint16_t erase_check_code[] =
700 {
701 /* loop: */
702 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
703 0xEA02, 0x0203, /* and r2, r2, r3 */
704 0x3901, /* subs r1, r1, #1 */
705 0xD1F9, /* bne loop */
706 /* end: */
707 0xE7FE, /* b end */
708 };
709
710 /* make sure we have a working area */
711 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
712 {
713 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
714 }
715
716 /* convert flash writing code into a buffer in target endianness */
717 for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
718 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
719
720 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
721 armv7m_info.core_mode = ARMV7M_MODE_ANY;
722
723 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
724 buf_set_u32(reg_params[0].value, 0, 32, address);
725
726 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
727 buf_set_u32(reg_params[1].value, 0, 32, count);
728
729 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
730 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
731
732 if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
733 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
734 {
735 destroy_reg_param(&reg_params[0]);
736 destroy_reg_param(&reg_params[1]);
737 destroy_reg_param(&reg_params[2]);
738 target_free_working_area(target, erase_check_algorithm);
739 return 0;
740 }
741
742 *blank = buf_get_u32(reg_params[2].value, 0, 32);
743
744 destroy_reg_param(&reg_params[0]);
745 destroy_reg_param(&reg_params[1]);
746 destroy_reg_param(&reg_params[2]);
747
748 target_free_working_area(target, erase_check_algorithm);
749
750 return ERROR_OK;
751 }
752
753 /*--------------------------------------------------------------------------*/
754
755 /*
756 * Only stuff below this line should need to verify that its target
757 * is an ARMv7-M node.
758 *
759 * FIXME yet none of it _does_ verify target types yet!
760 */
761
762
763 /*
764 * Return the debug ap baseaddress in hexadecimal;
765 * no extra output to simplify script processing
766 */
767 COMMAND_HANDLER(handle_dap_baseaddr_command)
768 {
769 struct target *target = get_current_target(cmd_ctx);
770 struct armv7m_common *armv7m = target_to_armv7m(target);
771 struct swjdp_common *swjdp = &armv7m->swjdp_info;
772 uint32_t apsel, apselsave, baseaddr;
773 int retval;
774
775 apselsave = swjdp->apsel;
776 switch (argc) {
777 case 0:
778 apsel = swjdp->apsel;
779 break;
780 case 1:
781 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
782 break;
783 default:
784 return ERROR_COMMAND_SYNTAX_ERROR;
785 }
786
787 if (apselsave != apsel)
788 dap_ap_select(swjdp, apsel);
789
790 dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
791 retval = swjdp_transaction_endcheck(swjdp);
792 command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
793
794 if (apselsave != apsel)
795 dap_ap_select(swjdp, apselsave);
796
797 return retval;
798 }
799
800 /*
801 * Return the debug ap id in hexadecimal;
802 * no extra output to simplify script processing
803 */
804 COMMAND_HANDLER(handle_dap_apid_command)
805 {
806 struct target *target = get_current_target(cmd_ctx);
807 struct armv7m_common *armv7m = target_to_armv7m(target);
808 struct swjdp_common *swjdp = &armv7m->swjdp_info;
809
810 return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
811 }
812
813 COMMAND_HANDLER(handle_dap_apsel_command)
814 {
815 struct target *target = get_current_target(cmd_ctx);
816 struct armv7m_common *armv7m = target_to_armv7m(target);
817 struct swjdp_common *swjdp = &armv7m->swjdp_info;
818
819 return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
820 }
821
822 COMMAND_HANDLER(handle_dap_memaccess_command)
823 {
824 struct target *target = get_current_target(cmd_ctx);
825 struct armv7m_common *armv7m = target_to_armv7m(target);
826 struct swjdp_common *swjdp = &armv7m->swjdp_info;
827
828 return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
829 }
830
831
832 COMMAND_HANDLER(handle_dap_info_command)
833 {
834 struct target *target = get_current_target(cmd_ctx);
835 struct armv7m_common *armv7m = target_to_armv7m(target);
836 struct swjdp_common *swjdp = &armv7m->swjdp_info;
837 uint32_t apsel;
838
839 switch (argc) {
840 case 0:
841 apsel = swjdp->apsel;
842 break;
843 case 1:
844 COMMAND_PARSE_NUMBER(u32, args[0], apsel);
845 break;
846 default:
847 return ERROR_COMMAND_SYNTAX_ERROR;
848 }
849
850 return dap_info_command(cmd_ctx, swjdp, apsel);
851 }
852
853 /** Registers commands used to access DAP resources. */
854 int armv7m_register_commands(struct command_context *cmd_ctx)
855 {
856 struct command *arm_adi_v5_dap_cmd;
857
858 arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
859 NULL, COMMAND_ANY,
860 "cortex dap specific commands");
861
862 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
863 handle_dap_info_command, COMMAND_EXEC,
864 "Displays dap info for ap [num],"
865 "default currently selected AP");
866 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
867 handle_dap_apsel_command, COMMAND_EXEC,
868 "Select a different AP [num] (default 0)");
869 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
870 handle_dap_apid_command, COMMAND_EXEC,
871 "Displays id reg from AP [num], "
872 "default currently selected AP");
873 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
874 handle_dap_baseaddr_command, COMMAND_EXEC,
875 "Displays debug base address from AP [num],"
876 "default currently selected AP");
877 register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
878 handle_dap_memaccess_command, COMMAND_EXEC,
879 "set/get number of extra tck for mem-ap "
880 "memory bus access [0-255]");
881
882 return ERROR_OK;
883 }
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