1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 char* armv7m_mode_strings
[] =
48 char* armv7m_state_strings
[] =
53 char* armv7m_exception_strings
[] =
55 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
56 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
59 char* armv7m_core_reg_list
[] =
61 /* Registers accessed through core debug */
62 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
65 /* Registers accessed through MSR instructions */
66 /* "apsr", "iapsr", "ipsr", "epsr", */
67 "primask", "basepri", "faultmask", "control"
70 char* armv7m_core_dbgreg_list
[] =
72 /* Registers accessed through core debug */
73 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
76 /* Registers accessed through MSR instructions */
77 /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
78 "primask", "basepri", "faultmask", "dbg_control"
81 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
83 reg_t armv7m_gdb_dummy_fp_reg
=
85 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
88 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
90 /* CORE_GP are accesible using the core debug registers */
91 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
106 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
108 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
109 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
110 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
112 /* CORE_SP are accesible using MSR and MRS instructions */
114 // {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
115 // {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
116 // {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
117 // {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
120 {0x10, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
121 {0x11, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
122 {0x13, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
123 {0x14, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
126 int armv7m_core_reg_arch_type
= -1;
128 /* Keep different contexts for the process being debugged and debug algorithms */
129 enum armv7m_runcontext
armv7m_get_context(target_t
*target
)
131 /* get pointers to arch-specific information */
132 armv7m_common_t
*armv7m
= target
->arch_info
;
134 if (armv7m
->process_context
== armv7m
->core_cache
)
135 return ARMV7M_PROCESS_CONTEXT
;
136 if (armv7m
->debug_context
== armv7m
->core_cache
)
137 return ARMV7M_DEBUG_CONTEXT
;
139 ERROR("Invalid runcontext");
143 int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
)
146 /* get pointers to arch-specific information */
147 armv7m_common_t
*armv7m
= target
->arch_info
;
149 if ((target
->state
!= TARGET_HALTED
) && (target
->state
!= TARGET_RESET
))
151 WARNING("target not halted, switch context ");
152 return ERROR_TARGET_NOT_HALTED
;
155 if (new_ctx
== armv7m_get_context(target
))
160 case ARMV7M_PROCESS_CONTEXT
:
161 armv7m
->core_cache
= armv7m
->process_context
;
163 case ARMV7M_DEBUG_CONTEXT
:
164 armv7m
->core_cache
= armv7m
->debug_context
;
167 ERROR("Invalid runcontext");
170 /* Mark registers in new context as dirty to force reload when run */
172 for (i
= 0; i
< armv7m
->core_cache
->num_regs
-1; i
++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
174 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
180 int armv7m_restore_context(target_t
*target
)
184 /* get pointers to arch-specific information */
185 armv7m_common_t
*armv7m
= target
->arch_info
;
189 if (armv7m
->pre_restore_context
)
190 armv7m
->pre_restore_context(target
);
192 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
194 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
196 armv7m
->write_core_reg(target
, i
);
200 if (armv7m
->post_restore_context
)
201 armv7m
->post_restore_context(target
);
207 /* Core state functions */
209 char *armv7m_exception_string(int number
)
211 if ((number
< 0) | (number
> 511))
212 return "Invalid exception";
214 return armv7m_exception_strings
[number
];
215 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
219 int armv7m_get_core_reg(reg_t
*reg
)
222 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
223 target_t
*target
= armv7m_reg
->target
;
224 armv7m_common_t
*armv7m_target
= target
->arch_info
;
226 if (target
->state
!= TARGET_HALTED
)
228 return ERROR_TARGET_NOT_HALTED
;
231 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
236 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
238 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
239 target_t
*target
= armv7m_reg
->target
;
240 u32 value
= buf_get_u32(buf
, 0, 32);
242 if (target
->state
!= TARGET_HALTED
)
244 return ERROR_TARGET_NOT_HALTED
;
247 buf_set_u32(reg
->value
, 0, 32, value
);
254 int armv7m_read_core_reg(struct target_s
*target
, int num
)
258 armv7m_core_reg_t
* armv7m_core_reg
;
260 /* get pointers to arch-specific information */
261 armv7m_common_t
*armv7m
= target
->arch_info
;
263 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
264 return ERROR_INVALID_ARGUMENTS
;
266 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
267 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
268 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
269 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
270 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
275 int armv7m_write_core_reg(struct target_s
*target
, int num
)
279 armv7m_core_reg_t
*armv7m_core_reg
;
281 /* get pointers to arch-specific information */
282 armv7m_common_t
*armv7m
= target
->arch_info
;
284 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
285 return ERROR_INVALID_ARGUMENTS
;
287 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
288 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
289 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
290 if (retval
!= ERROR_OK
)
292 ERROR("JTAG failure");
293 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
294 return ERROR_JTAG_DEVICE_ERROR
;
296 DEBUG("write core reg %i value 0x%x", num
, reg_value
);
297 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
298 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
303 int armv7m_invalidate_core_regs(target_t
*target
)
305 /* get pointers to arch-specific information */
306 armv7m_common_t
*armv7m
= target
->arch_info
;
309 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
311 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
312 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
318 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
320 /* get pointers to arch-specific information */
321 armv7m_common_t
*armv7m
= target
->arch_info
;
324 if (target
->state
!= TARGET_HALTED
)
326 ERROR("Target not halted");
327 return ERROR_TARGET_NOT_HALTED
;
331 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
333 /* TODOLATER correct list of registers, names ? */
334 for (i
= 0; i
< *reg_list_size
; i
++)
336 if (i
< ARMV7NUMCOREREGS
)
337 (*reg_list
)[i
] = &armv7m
->process_context
->reg_list
[i
];
338 /* (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; */
340 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
342 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
343 armv7m
->process_context
->reg_list
[15].value
[0] |= 1;
344 (*reg_list
)[25] = &armv7m
->process_context
->reg_list
[ARMV7M_xPSR
];
348 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
350 /* get pointers to arch-specific information */
351 armv7m_common_t
*armv7m
= target
->arch_info
;
352 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
353 enum armv7m_state core_state
= armv7m
->core_state
;
354 enum armv7m_mode core_mode
= armv7m
->core_mode
;
355 int retval
= ERROR_OK
;
357 int exit_breakpoint_size
= 0;
360 armv7m
->core_state
= core_state
;
361 armv7m
->core_mode
= core_mode
;
363 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
365 ERROR("current target isn't an ARMV7M target");
366 return ERROR_TARGET_INVALID
;
369 if (target
->state
!= TARGET_HALTED
)
371 WARNING("target not halted");
372 return ERROR_TARGET_NOT_HALTED
;
375 /* refresh core register cache */
376 /* Not needed if core register cache is always consistent with target process state */
377 armv7m_use_context(target
, ARMV7M_DEBUG_CONTEXT
);
379 for (i
= 0; i
< num_mem_params
; i
++)
381 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
384 for (i
= 0; i
< num_reg_params
; i
++)
386 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
391 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
395 if (reg
->size
!= reg_params
[i
].size
)
397 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
401 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
402 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
405 /* ARMV7M always runs in Thumb state */
406 exit_breakpoint_size
= 2;
407 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_SOFT
)) != ERROR_OK
)
409 ERROR("can't add breakpoint to finish algorithm execution");
410 return ERROR_TARGET_FAILURE
;
413 /* This code relies on the target specific resume() and poll()->debug_entry()
414 sequence to write register values to the processor and the read them back */
415 target
->type
->resume(target
, 0, entry_point
, 1, 1);
416 target
->type
->poll(target
);
418 while (target
->state
!= TARGET_HALTED
)
421 target
->type
->poll(target
);
422 if ((timeout_ms
-= 5) <= 0)
424 ERROR("timeout waiting for algorithm to complete, trying to halt target");
425 target
->type
->halt(target
);
427 while (target
->state
!= TARGET_HALTED
)
430 target
->type
->poll(target
);
431 if ((timeout_ms
-= 10) <= 0)
433 ERROR("target didn't reenter debug state, exiting");
437 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
438 DEBUG("failed algoritm halted at 0x%x ", pc
);
439 retval
= ERROR_TARGET_TIMEOUT
;
443 breakpoint_remove(target
, exit_point
);
445 /* Read memory values to mem_params[] */
446 for (i
= 0; i
< num_mem_params
; i
++)
448 if (mem_params
[i
].direction
!= PARAM_OUT
)
449 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
452 /* Copy core register values to reg_params[] */
453 for (i
= 0; i
< num_reg_params
; i
++)
455 if (reg_params
[i
].direction
!= PARAM_OUT
)
457 reg_t
*reg
= register_get_by_name(armv7m
->debug_context
, reg_params
[i
].reg_name
, 0);
461 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
465 if (reg
->size
!= reg_params
[i
].size
)
467 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
471 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
478 int armv7m_arch_state(struct target_s
*target
)
480 /* get pointers to arch-specific information */
481 armv7m_common_t
*armv7m
= target
->arch_info
;
483 USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
484 armv7m_state_strings
[armv7m
->core_state
],
485 target_debug_reason_strings
[target
->debug_reason
],
486 armv7m_mode_strings
[armv7m
->core_mode
],
487 armv7m_exception_string(armv7m
->exception_number
),
488 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
489 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
494 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
496 /* get pointers to arch-specific information */
497 armv7m_common_t
*armv7m
= target
->arch_info
;
499 int num_regs
= ARMV7NUMCOREREGS
;
500 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
501 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
502 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
503 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
506 if (armv7m_core_reg_arch_type
== -1)
507 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
509 /* Build the process context cache */
510 cache
->name
= "arm v7m registers";
512 cache
->reg_list
= reg_list
;
513 cache
->num_regs
= num_regs
;
515 armv7m
->core_cache
= cache
;
516 armv7m
->process_context
= cache
;
518 for (i
= 0; i
< num_regs
; i
++)
520 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
521 arch_info
[i
].target
= target
;
522 arch_info
[i
].armv7m_common
= armv7m
;
523 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
524 reg_list
[i
].size
= 32;
525 reg_list
[i
].value
= calloc(1, 4);
526 reg_list
[i
].dirty
= 0;
527 reg_list
[i
].valid
= 0;
528 reg_list
[i
].bitfield_desc
= NULL
;
529 reg_list
[i
].num_bitfields
= 0;
530 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
531 reg_list
[i
].arch_info
= &arch_info
[i
];
534 /* Build the debug context cache*/
535 cache
= malloc(sizeof(reg_cache_t
));
536 reg_list
= malloc(sizeof(reg_t
) * num_regs
);
538 cache
->name
= "arm v7m debug registers";
540 cache
->reg_list
= reg_list
;
541 cache
->num_regs
= num_regs
;
542 armv7m
->debug_context
= cache
;
543 armv7m
->process_context
->next
= cache
;
545 for (i
= 0; i
< num_regs
; i
++)
547 reg_list
[i
].name
= armv7m_core_dbgreg_list
[i
];
548 reg_list
[i
].size
= 32;
549 reg_list
[i
].value
= calloc(1, 4);
550 reg_list
[i
].dirty
= 0;
551 reg_list
[i
].valid
= 0;
552 reg_list
[i
].bitfield_desc
= NULL
;
553 reg_list
[i
].num_bitfields
= 0;
554 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
555 reg_list
[i
].arch_info
= &arch_info
[i
];
561 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
563 armv7m_build_reg_cache(target
);
568 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
570 /* register arch-specific functions */
572 target
->arch_info
= armv7m
;
573 armv7m
->core_state
= ARMV7M_STATE_THUMB
;
574 armv7m
->read_core_reg
= armv7m_read_core_reg
;
575 armv7m
->write_core_reg
= armv7m_write_core_reg
;
580 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
585 int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
587 working_area_t
*crc_algorithm
;
588 armv7m_algorithm_t armv7m_info
;
589 reg_param_t reg_params
[2];
592 u16 cortex_m3_crc_code
[] = {
593 0x4602, /* mov r2, r0 */
594 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
595 0x460B, /* mov r3, r1 */
596 0xF04F, 0x0400, /* mov r4, #0 */
597 0xE013, /* b ncomp */
599 0x5D11, /* ldrb r1, [r2, r4] */
600 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
601 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
603 0xF04F, 0x0500, /* mov r5, #0 */
605 0x2800, /* cmp r0, #0 */
606 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
607 0xF105, 0x0501, /* add r5, r5, #1 */
608 0x4630, /* mov r0, r6 */
610 0xEA86, 0x0007, /* eor r0, r6, r7 */
611 0x2D08, /* cmp r5, #8 */
612 0xD1F4, /* bne loop */
614 0xF104, 0x0401, /* add r4, r4, #1 */
616 0x429C, /* cmp r4, r3 */
617 0xD1E9, /* bne nbyte */
620 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
625 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
627 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
630 /* convert flash writing code into a buffer in target endianness */
631 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(u16
)); i
++)
632 target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(u16
), cortex_m3_crc_code
[i
]);
634 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
635 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
636 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
638 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
639 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
641 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
642 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
644 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
645 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
647 ERROR("error executing cortex_m3 crc algorithm");
648 destroy_reg_param(®_params
[0]);
649 destroy_reg_param(®_params
[1]);
650 target_free_working_area(target
, crc_algorithm
);
654 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
656 destroy_reg_param(®_params
[0]);
657 destroy_reg_param(®_params
[1]);
659 target_free_working_area(target
, crc_algorithm
);
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