1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 char* armv7m_mode_strings
[] =
45 "Thread", "Thread (User)", "Handler",
48 char* armv7m_exception_strings
[] =
50 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
51 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
54 char* armv7m_core_reg_list
[] =
56 /* Registers accessed through core debug */
57 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
60 /* Registers accessed through special reg 20 */
61 "primask", "basepri", "faultmask", "control"
64 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
66 reg_t armv7m_gdb_dummy_fp_reg
=
68 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
71 u8 armv7m_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
73 reg_t armv7m_gdb_dummy_fps_reg
=
75 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
78 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
80 /* CORE_GP are accesible using the core debug registers */
81 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
82 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
83 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
84 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
85 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
86 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
87 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
88 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
89 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
90 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
91 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
99 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
100 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
102 /* CORE_SP are accesible using coreregister 20 */
103 {19, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
104 {20, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
105 {21, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
106 {22, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
109 int armv7m_core_reg_arch_type
= -1;
111 int armv7m_restore_context(target_t
*target
)
115 /* get pointers to arch-specific information */
116 armv7m_common_t
*armv7m
= target
->arch_info
;
120 if (armv7m
->pre_restore_context
)
121 armv7m
->pre_restore_context(target
);
123 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
125 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
127 armv7m
->write_core_reg(target
, i
);
131 if (armv7m
->post_restore_context
)
132 armv7m
->post_restore_context(target
);
137 /* Core state functions */
138 char *armv7m_exception_string(int number
)
140 static char enamebuf
[32];
142 if ((number
< 0) | (number
> 511))
143 return "Invalid exception";
145 return armv7m_exception_strings
[number
];
146 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
150 int armv7m_get_core_reg(reg_t
*reg
)
153 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
154 target_t
*target
= armv7m_reg
->target
;
155 armv7m_common_t
*armv7m_target
= target
->arch_info
;
157 if (target
->state
!= TARGET_HALTED
)
159 return ERROR_TARGET_NOT_HALTED
;
162 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
167 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
169 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
170 target_t
*target
= armv7m_reg
->target
;
171 u32 value
= buf_get_u32(buf
, 0, 32);
173 if (target
->state
!= TARGET_HALTED
)
175 return ERROR_TARGET_NOT_HALTED
;
178 buf_set_u32(reg
->value
, 0, 32, value
);
185 int armv7m_read_core_reg(struct target_s
*target
, int num
)
189 armv7m_core_reg_t
* armv7m_core_reg
;
191 /* get pointers to arch-specific information */
192 armv7m_common_t
*armv7m
= target
->arch_info
;
194 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
195 return ERROR_INVALID_ARGUMENTS
;
197 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
198 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
199 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
200 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
201 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
206 int armv7m_write_core_reg(struct target_s
*target
, int num
)
210 armv7m_core_reg_t
*armv7m_core_reg
;
212 /* get pointers to arch-specific information */
213 armv7m_common_t
*armv7m
= target
->arch_info
;
215 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
216 return ERROR_INVALID_ARGUMENTS
;
218 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
219 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
220 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
221 if (retval
!= ERROR_OK
)
223 LOG_ERROR("JTAG failure");
224 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
225 return ERROR_JTAG_DEVICE_ERROR
;
227 LOG_DEBUG("write core reg %i value 0x%x", num
, reg_value
);
228 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
229 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
234 int armv7m_invalidate_core_regs(target_t
*target
)
236 /* get pointers to arch-specific information */
237 armv7m_common_t
*armv7m
= target
->arch_info
;
240 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
242 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
243 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
249 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
251 /* get pointers to arch-specific information */
252 armv7m_common_t
*armv7m
= target
->arch_info
;
256 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
258 for (i
= 0; i
< 16; i
++)
260 (*reg_list
)[i
] = &armv7m
->core_cache
->reg_list
[i
];
263 for (i
= 16; i
< 24; i
++)
265 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
268 (*reg_list
)[24] = &armv7m_gdb_dummy_fps_reg
;
270 /* ARMV7M is always in thumb mode, try to make GDB understand this
271 * if it does not support this arch */
272 armv7m
->core_cache
->reg_list
[15].value
[0] |= 1;
273 (*reg_list
)[25] = &armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
];
277 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
279 /* get pointers to arch-specific information */
280 armv7m_common_t
*armv7m
= target
->arch_info
;
281 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
282 enum armv7m_mode core_mode
= armv7m
->core_mode
;
283 int retval
= ERROR_OK
;
286 u32 context
[ARMV7NUMCOREREGS
];
288 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
290 LOG_ERROR("current target isn't an ARMV7M target");
291 return ERROR_TARGET_INVALID
;
294 if (target
->state
!= TARGET_HALTED
)
296 LOG_WARNING("target not halted");
297 return ERROR_TARGET_NOT_HALTED
;
300 /* refresh core register cache */
301 /* Not needed if core register cache is always consistent with target process state */
302 for (i
= 0; i
< ARMV7NUMCOREREGS
; i
++)
304 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
305 armv7m
->read_core_reg(target
, i
);
306 context
[i
] = buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
309 for (i
= 0; i
< num_mem_params
; i
++)
311 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
314 for (i
= 0; i
< num_reg_params
; i
++)
316 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
321 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
325 if (reg
->size
!= reg_params
[i
].size
)
327 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
331 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
332 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
335 if (armv7m_algorithm_info
->core_mode
!= ARMV7M_MODE_ANY
)
337 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
338 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 1, armv7m_algorithm_info
->core_mode
);
339 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
340 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
343 /* ARMV7M always runs in Thumb state */
344 if ((retval
= breakpoint_add(target
, exit_point
, 2, BKPT_SOFT
)) != ERROR_OK
)
346 LOG_ERROR("can't add breakpoint to finish algorithm execution");
347 return ERROR_TARGET_FAILURE
;
350 /* This code relies on the target specific resume() and poll()->debug_entry()
351 sequence to write register values to the processor and the read them back */
352 target
->type
->resume(target
, 0, entry_point
, 1, 1);
353 target
->type
->poll(target
);
355 while (target
->state
!= TARGET_HALTED
)
358 target
->type
->poll(target
);
359 if ((timeout_ms
-= 5) <= 0)
361 LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
362 target
->type
->halt(target
);
364 while (target
->state
!= TARGET_HALTED
)
367 target
->type
->poll(target
);
368 if ((timeout_ms
-= 10) <= 0)
370 LOG_ERROR("target didn't reenter debug state, exiting");
374 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
375 LOG_DEBUG("failed algoritm halted at 0x%x ", pc
);
376 retval
= ERROR_TARGET_TIMEOUT
;
380 breakpoint_remove(target
, exit_point
);
382 /* Read memory values to mem_params[] */
383 for (i
= 0; i
< num_mem_params
; i
++)
385 if (mem_params
[i
].direction
!= PARAM_OUT
)
386 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
389 /* Copy core register values to reg_params[] */
390 for (i
= 0; i
< num_reg_params
; i
++)
392 if (reg_params
[i
].direction
!= PARAM_OUT
)
394 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
398 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
402 if (reg
->size
!= reg_params
[i
].size
)
404 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
408 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
412 for (i
= ARMV7NUMCOREREGS
-1; i
>= 0; i
--)
414 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m
->core_cache
->reg_list
[i
].name
, context
[i
]);
415 buf_set_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32, context
[i
]);
416 armv7m
->core_cache
->reg_list
[i
].valid
= 1;
417 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
420 armv7m
->core_mode
= core_mode
;
425 int armv7m_arch_state(struct target_s
*target
)
427 /* get pointers to arch-specific information */
428 armv7m_common_t
*armv7m
= target
->arch_info
;
430 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
431 target_debug_reason_strings
[target
->debug_reason
],
432 armv7m_mode_strings
[armv7m
->core_mode
],
433 armv7m_exception_string(armv7m
->exception_number
),
434 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
435 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
440 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
442 /* get pointers to arch-specific information */
443 armv7m_common_t
*armv7m
= target
->arch_info
;
445 int num_regs
= ARMV7NUMCOREREGS
;
446 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
447 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
448 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
449 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
452 if (armv7m_core_reg_arch_type
== -1)
453 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
455 /* Build the process context cache */
456 cache
->name
= "arm v7m registers";
458 cache
->reg_list
= reg_list
;
459 cache
->num_regs
= num_regs
;
461 armv7m
->core_cache
= cache
;
463 for (i
= 0; i
< num_regs
; i
++)
465 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
466 arch_info
[i
].target
= target
;
467 arch_info
[i
].armv7m_common
= armv7m
;
468 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
469 reg_list
[i
].size
= 32;
470 reg_list
[i
].value
= calloc(1, 4);
471 reg_list
[i
].dirty
= 0;
472 reg_list
[i
].valid
= 0;
473 reg_list
[i
].bitfield_desc
= NULL
;
474 reg_list
[i
].num_bitfields
= 0;
475 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
476 reg_list
[i
].arch_info
= &arch_info
[i
];
482 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
484 armv7m_build_reg_cache(target
);
489 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
491 /* register arch-specific functions */
493 target
->arch_info
= armv7m
;
494 armv7m
->read_core_reg
= armv7m_read_core_reg
;
495 armv7m
->write_core_reg
= armv7m_write_core_reg
;
500 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
505 int armv7m_checksum_memory(struct target_s
*target
, u32 address
, u32 count
, u32
* checksum
)
507 working_area_t
*crc_algorithm
;
508 armv7m_algorithm_t armv7m_info
;
509 reg_param_t reg_params
[2];
512 u16 cortex_m3_crc_code
[] = {
513 0x4602, /* mov r2, r0 */
514 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
515 0x460B, /* mov r3, r1 */
516 0xF04F, 0x0400, /* mov r4, #0 */
517 0xE013, /* b ncomp */
519 0x5D11, /* ldrb r1, [r2, r4] */
520 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
521 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
523 0xF04F, 0x0500, /* mov r5, #0 */
525 0x2800, /* cmp r0, #0 */
526 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
527 0xF105, 0x0501, /* add r5, r5, #1 */
528 0x4630, /* mov r0, r6 */
530 0xEA86, 0x0007, /* eor r0, r6, r7 */
531 0x2D08, /* cmp r5, #8 */
532 0xD1F4, /* bne loop */
534 0xF104, 0x0401, /* add r4, r4, #1 */
536 0x429C, /* cmp r4, r3 */
537 0xD1E9, /* bne nbyte */
540 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
545 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
547 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
550 /* convert flash writing code into a buffer in target endianness */
551 for (i
= 0; i
< (sizeof(cortex_m3_crc_code
)/sizeof(u16
)); i
++)
552 target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(u16
), cortex_m3_crc_code
[i
]);
554 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
555 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
557 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
558 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
560 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
561 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
563 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 2, reg_params
,
564 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
566 LOG_ERROR("error executing cortex_m3 crc algorithm");
567 destroy_reg_param(®_params
[0]);
568 destroy_reg_param(®_params
[1]);
569 target_free_working_area(target
, crc_algorithm
);
573 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
575 destroy_reg_param(®_params
[0]);
576 destroy_reg_param(®_params
[1]);
578 target_free_working_area(target
, crc_algorithm
);
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