1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2006 by Magnus Lundin *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "replacements.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 char* armv7m_mode_strings
[] =
47 char* armv7m_state_strings
[] =
52 char* armv7m_exception_strings
[] =
54 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
55 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 char* armv7m_core_reg_list
[] =
60 /* Registers accessed through core debug */
61 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 /* Registers accessed through MSR instructions */
65 // "apsr", "iapsr", "ipsr", "epsr",
66 "primask", "basepri", "faultmask", "control"
69 char* armv7m_core_dbgreg_list
[] =
71 /* Registers accessed through core debug */
72 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
75 /* Registers accessed through MSR instructions */
76 // "dbg_apsr", "iapsr", "ipsr", "epsr",
77 "primask", "basepri", "faultmask", "dbg_control"
80 u8 armv7m_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
82 reg_t armv7m_gdb_dummy_fp_reg
=
84 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
87 armv7m_core_reg_t armv7m_core_reg_list_arch_info
[] =
89 /* CORE_GP are accesible using the core debug registers */
90 {0, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
91 {1, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
92 {2, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
93 {3, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
94 {4, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
95 {5, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
96 {6, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
97 {7, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
98 {8, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
99 {9, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
100 {10, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
101 {11, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
102 {12, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
103 {13, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
104 {14, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
105 {15, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
},
107 {16, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* xPSR */
108 {17, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* MSP */
109 {18, ARMV7M_REGISTER_CORE_GP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PSP */
111 /* CORE_SP are accesible using MSR and MRS instructions */
112 // {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
113 // {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
114 // {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
115 // {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
117 {0x10, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* PRIMASK */
118 {0x11, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* BASEPRI */
119 {0x13, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
}, /* FAULTMASK */
120 {0x14, ARMV7M_REGISTER_CORE_SP
, ARMV7M_MODE_ANY
, NULL
, NULL
} /* CONTROL */
123 int armv7m_core_reg_arch_type
= -1;
126 /* Keep different contexts for the process being debugged and debug algorithms */
127 enum armv7m_runcontext
armv7m_get_context(target_t
*target
)
129 /* get pointers to arch-specific information */
130 armv7m_common_t
*armv7m
= target
->arch_info
;
132 if (armv7m
->process_context
== armv7m
->core_cache
)
133 return ARMV7M_PROCESS_CONTEXT
;
134 if (armv7m
->debug_context
== armv7m
->core_cache
)
135 return ARMV7M_DEBUG_CONTEXT
;
137 ERROR("Invalid runcontext");
141 int armv7m_use_context(target_t
*target
, enum armv7m_runcontext new_ctx
)
144 /* get pointers to arch-specific information */
145 armv7m_common_t
*armv7m
= target
->arch_info
;
147 if ((target
->state
!= TARGET_HALTED
) && (target
->state
!= TARGET_RESET
))
149 WARNING("target not halted, switch context ");
150 return ERROR_TARGET_NOT_HALTED
;
153 if (new_ctx
== armv7m_get_context(target
))
158 case ARMV7M_PROCESS_CONTEXT
:
159 armv7m
->core_cache
= armv7m
->process_context
;
161 case ARMV7M_DEBUG_CONTEXT
:
162 armv7m
->core_cache
= armv7m
->debug_context
;
165 ERROR("Invalid runcontext");
168 /* Mark registers in new context as dirty to force reload when run */
170 for (i
= 0; i
< armv7m
->core_cache
->num_regs
-1; i
++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
172 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
178 /* Core state functions */
180 char *armv7m_exception_string(int number
)
182 if ((number
< 0) | (number
> 511))
183 return "Invalid exception";
185 return armv7m_exception_strings
[number
];
186 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
190 int armv7m_get_core_reg(reg_t
*reg
)
193 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
194 target_t
*target
= armv7m_reg
->target
;
195 armv7m_common_t
*armv7m_target
= target
->arch_info
;
197 if (target
->state
!= TARGET_HALTED
)
199 return ERROR_TARGET_NOT_HALTED
;
202 retval
= armv7m_target
->read_core_reg(target
, armv7m_reg
->num
);
207 int armv7m_set_core_reg(reg_t
*reg
, u8
*buf
)
209 armv7m_core_reg_t
*armv7m_reg
= reg
->arch_info
;
210 target_t
*target
= armv7m_reg
->target
;
211 armv7m_common_t
*armv7m_target
= target
->arch_info
;
212 u32 value
= buf_get_u32(buf
, 0, 32);
214 if (target
->state
!= TARGET_HALTED
)
216 return ERROR_TARGET_NOT_HALTED
;
219 buf_set_u32(reg
->value
, 0, 32, value
);
226 int armv7m_read_core_reg(struct target_s
*target
, int num
)
230 armv7m_core_reg_t
* armv7m_core_reg
;
232 /* get pointers to arch-specific information */
233 armv7m_common_t
*armv7m
= target
->arch_info
;
235 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
236 return ERROR_INVALID_ARGUMENTS
;
238 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
239 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
240 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
241 armv7m
->core_cache
->reg_list
[num
].valid
=1;
242 armv7m
->core_cache
->reg_list
[num
].dirty
=0;
247 int armv7m_write_core_reg(struct target_s
*target
, int num
)
251 armv7m_core_reg_t
* armv7m_core_reg
;
253 /* get pointers to arch-specific information */
254 armv7m_common_t
*armv7m
= target
->arch_info
;
256 if ((num
< 0) || (num
>= ARMV7NUMCOREREGS
))
257 return ERROR_INVALID_ARGUMENTS
;
259 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
260 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
261 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
262 if (retval
!= ERROR_OK
)
264 ERROR("JTAG failure");
265 armv7m
->core_cache
->reg_list
[num
].dirty
=1;
266 return ERROR_JTAG_DEVICE_ERROR
;
268 DEBUG("write core reg %i value 0x%x",num
,reg_value
);
269 armv7m
->core_cache
->reg_list
[num
].valid
=1;
270 armv7m
->core_cache
->reg_list
[num
].dirty
=0;
275 int armv7m_invalidate_core_regs(target_t
*target
)
277 /* get pointers to arch-specific information */
278 armv7m_common_t
*armv7m
= target
->arch_info
;
281 for (i
= 0; i
< armv7m
->core_cache
->num_regs
; i
++)
283 armv7m
->core_cache
->reg_list
[i
].valid
= 0;
284 armv7m
->core_cache
->reg_list
[i
].dirty
= 0;
290 int armv7m_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
292 /* get pointers to arch-specific information */
293 armv7m_common_t
*armv7m
= target
->arch_info
;
296 if (target
->state
!= TARGET_HALTED
)
298 return ERROR_TARGET_NOT_HALTED
;
302 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
304 /* TODOLATER correct list of registers, names ? */
305 for (i
= 0; i
< *reg_list_size
; i
++)
307 if (i
< ARMV7NUMCOREREGS
)
308 (*reg_list
)[i
] = &armv7m
->process_context
->reg_list
[i
];
309 //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
311 (*reg_list
)[i
] = &armv7m_gdb_dummy_fp_reg
;
313 /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
314 //armv7m->core_cache->reg_list[15].value[0] |= 1;
315 armv7m
->process_context
->reg_list
[15].value
[0] |= 1;
316 //armv7m->core_cache->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
317 //armv7m->process_context->reg_list[ARMV7M_xPSR].value[0] = (1<<5);
318 (*reg_list
)[25] = &armv7m
->process_context
->reg_list
[ARMV7M_xPSR
];
319 //(*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
323 int armv7m_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
325 // get pointers to arch-specific information
326 armv7m_common_t
*armv7m
= target
->arch_info
;
327 armv7m_algorithm_t
*armv7m_algorithm_info
= arch_info
;
328 enum armv7m_state core_state
= armv7m
->core_state
;
329 enum armv7m_mode core_mode
= armv7m
->core_mode
;
330 int retval
= ERROR_OK
;
332 int exit_breakpoint_size
= 0;
335 armv7m
->core_state
= core_state
;
336 armv7m
->core_mode
= core_mode
;
338 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
340 ERROR("current target isn't an ARMV7M target");
341 return ERROR_TARGET_INVALID
;
344 if (target
->state
!= TARGET_HALTED
)
346 WARNING("target not halted");
347 return ERROR_TARGET_NOT_HALTED
;
350 /* refresh core register cache */
351 /* Not needed if core register cache is always consistent with target process state */
352 armv7m_use_context(target
, ARMV7M_DEBUG_CONTEXT
);
354 for (i
= 0; i
< num_mem_params
; i
++)
356 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
359 for (i
= 0; i
< num_reg_params
; i
++)
361 reg_t
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
362 //reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
363 //armv7m_core_reg_t * armv7m_core_reg = reg->arch_info;
368 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
372 if (reg
->size
!= reg_params
[i
].size
)
374 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
378 regvalue
= buf_get_u32(reg_params
[i
].value
, 0, 32);
379 //armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, regvalue);
380 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
383 /* ARMV7M always runs in Thumb state */
384 exit_breakpoint_size
= 2;
385 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_SOFT
)) != ERROR_OK
)
387 ERROR("can't add breakpoint to finish algorithm execution");
388 return ERROR_TARGET_FAILURE
;
391 /* This code relies on the target specific resume() and poll()->debug_entry()
392 sequence to write register values to the processor and the read them back */
393 target
->type
->resume(target
, 0, entry_point
, 1, 1);
394 target
->type
->poll(target
);
396 while (target
->state
!= TARGET_HALTED
)
399 target
->type
->poll(target
);
400 if ((timeout_ms
-= 5) <= 0)
402 ERROR("timeout waiting for algorithm to complete, trying to halt target");
403 target
->type
->halt(target
);
405 while (target
->state
!= TARGET_HALTED
)
408 target
->type
->poll(target
);
409 if ((timeout_ms
-= 10) <= 0)
411 ERROR("target didn't reenter debug state, exiting");
415 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
416 DEBUG("failed algoritm halted at 0x%x ", pc
);
417 retval
= ERROR_TARGET_TIMEOUT
;
421 breakpoint_remove(target
, exit_point
);
423 /* Read memory values to mem_params[] */
424 for (i
= 0; i
< num_mem_params
; i
++)
426 if (mem_params
[i
].direction
!= PARAM_OUT
)
427 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
430 /* Copy core register values to reg_params[] */
431 for (i
= 0; i
< num_reg_params
; i
++)
433 if (reg_params
[i
].direction
!= PARAM_OUT
)
435 //reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
436 reg_t
*reg
= register_get_by_name(armv7m
->debug_context
, reg_params
[i
].reg_name
, 0);
441 ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
445 if (reg
->size
!= reg_params
[i
].size
)
447 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
451 armv7m_core_reg_t
*armv7m_core_reg
= reg
->arch_info
;
452 //armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®value);
453 //buf_set_u32(reg_params[i].value, 0, 32, regvalue);
454 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
458 /* Mark all core registers !! except control !! as valid but dirty */
459 /* This will be done by armv7m_use_context in resume function */
460 //for (i = 0; i < armv7m->core_cache->num_regs-1; i++)
462 // armv7m->core_cache->reg_list[i].dirty = 1;
465 // ????armv7m->core_state = core_state;
466 // ????armv7m->core_mode = core_mode;
471 int armv7m_arch_state(struct target_s
*target
, char *buf
, int buf_size
)
473 /* get pointers to arch-specific information */
474 armv7m_common_t
*armv7m
= target
->arch_info
;
476 snprintf(buf
, buf_size
,
477 "target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
478 armv7m_state_strings
[armv7m
->core_state
],
479 target_debug_reason_strings
[target
->debug_reason
],
480 armv7m_mode_strings
[armv7m
->core_mode
],
481 armv7m_exception_string(armv7m
->exception_number
),
482 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32),
483 buf_get_u32(armv7m
->core_cache
->reg_list
[15].value
, 0, 32));
488 reg_cache_t
*armv7m_build_reg_cache(target_t
*target
)
490 /* get pointers to arch-specific information */
491 armv7m_common_t
*armv7m
= target
->arch_info
;
492 arm_jtag_t
*jtag_info
= &armv7m
->jtag_info
;
494 int num_regs
= ARMV7NUMCOREREGS
;
495 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
496 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
497 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
498 armv7m_core_reg_t
*arch_info
= malloc(sizeof(armv7m_core_reg_t
) * num_regs
);
501 if (armv7m_core_reg_arch_type
== -1)
502 armv7m_core_reg_arch_type
= register_reg_arch_type(armv7m_get_core_reg
, armv7m_set_core_reg
);
504 /* Build the process context cache */
505 cache
->name
= "arm v7m registers";
507 cache
->reg_list
= reg_list
;
508 cache
->num_regs
= num_regs
;
510 armv7m
->core_cache
= cache
;
511 armv7m
->process_context
= cache
;
513 for (i
= 0; i
< num_regs
; i
++)
515 arch_info
[i
] = armv7m_core_reg_list_arch_info
[i
];
516 arch_info
[i
].target
= target
;
517 arch_info
[i
].armv7m_common
= armv7m
;
518 reg_list
[i
].name
= armv7m_core_reg_list
[i
];
519 reg_list
[i
].size
= 32;
520 reg_list
[i
].value
= calloc(1, 4);
521 reg_list
[i
].dirty
= 0;
522 reg_list
[i
].valid
= 0;
523 reg_list
[i
].bitfield_desc
= NULL
;
524 reg_list
[i
].num_bitfields
= 0;
525 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
526 reg_list
[i
].arch_info
= &arch_info
[i
];
529 /* Build the debug context cache*/
530 cache
= malloc(sizeof(reg_cache_t
));
531 reg_list
= malloc(sizeof(reg_t
) * num_regs
);
533 cache
->name
= "arm v7m debug registers";
535 cache
->reg_list
= reg_list
;
536 cache
->num_regs
= num_regs
;
537 armv7m
->debug_context
= cache
;
538 armv7m
->process_context
->next
= cache
;
540 for (i
= 0; i
< num_regs
; i
++)
542 reg_list
[i
].name
= armv7m_core_dbgreg_list
[i
];
543 reg_list
[i
].size
= 32;
544 reg_list
[i
].value
= calloc(1, 4);
545 reg_list
[i
].dirty
= 0;
546 reg_list
[i
].valid
= 0;
547 reg_list
[i
].bitfield_desc
= NULL
;
548 reg_list
[i
].num_bitfields
= 0;
549 reg_list
[i
].arch_type
= armv7m_core_reg_arch_type
;
550 reg_list
[i
].arch_info
= &arch_info
[i
];
556 int armv7m_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
558 armv7m_build_reg_cache(target
);
563 int armv7m_init_arch_info(target_t
*target
, armv7m_common_t
*armv7m
)
565 /* register arch-specific functions */
567 target
->arch_info
= armv7m
;
568 armv7m
->core_state
= ARMV7M_STATE_THUMB
;
569 armv7m
->read_core_reg
= armv7m_read_core_reg
;
570 armv7m
->write_core_reg
= armv7m_write_core_reg
;
575 int armv7m_register_commands(struct command_context_s
*cmd_ctx
)
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