Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
Laurentiu Cocanu - more error handling fixes
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29 #ifdef HAVE_CONFIG_H
30 #include "config.h"
31 #endif
32
33 #include "replacements.h"
34
35 #include "armv7m.h"
36 #include "register.h"
37 #include "target.h"
38 #include "log.h"
39 #include "jtag.h"
40 #include "arm_jtag.h"
41
42 #include <stdlib.h>
43 #include <string.h>
44
45 #if 0
46 #define _DEBUG_INSTRUCTION_EXECUTION_
47 #endif
48
49 char* armv7m_mode_strings[] =
50 {
51 "Thread", "Thread (User)", "Handler",
52 };
53
54 char* armv7m_exception_strings[] =
55 {
56 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
57 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
58 };
59
60 char* armv7m_core_reg_list[] =
61 {
62 /* Registers accessed through core debug */
63 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
64 "sp", "lr", "pc",
65 "xPSR", "msp", "psp",
66 /* Registers accessed through special reg 20 */
67 "primask", "basepri", "faultmask", "control"
68 };
69
70 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
71
72 reg_t armv7m_gdb_dummy_fp_reg =
73 {
74 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
75 };
76
77 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
78
79 reg_t armv7m_gdb_dummy_fps_reg =
80 {
81 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
82 };
83
84 #ifdef ARMV7_GDB_HACKS
85 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
86
87 reg_t armv7m_gdb_dummy_cpsr_reg =
88 {
89 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
90 };
91 #endif
92
93 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
94 {
95 /* CORE_GP are accesible using the core debug registers */
96 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
107 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
108 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
109 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
110 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
111 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
112
113 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
114 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
115 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
116
117 /* CORE_SP are accesible using coreregister 20 */
118 {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
119 {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
120 {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
121 {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
122 };
123
124 int armv7m_core_reg_arch_type = -1;
125 int armv7m_dummy_core_reg_arch_type = -1;
126
127 int armv7m_restore_context(target_t *target)
128 {
129 int i;
130
131 /* get pointers to arch-specific information */
132 armv7m_common_t *armv7m = target->arch_info;
133
134 LOG_DEBUG(" ");
135
136 if (armv7m->pre_restore_context)
137 armv7m->pre_restore_context(target);
138
139 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
140 {
141 if (armv7m->core_cache->reg_list[i].dirty)
142 {
143 armv7m->write_core_reg(target, i);
144 }
145 }
146
147 if (armv7m->post_restore_context)
148 armv7m->post_restore_context(target);
149
150 return ERROR_OK;
151 }
152
153 /* Core state functions */
154 char *armv7m_exception_string(int number)
155 {
156 static char enamebuf[32];
157
158 if ((number < 0) | (number > 511))
159 return "Invalid exception";
160 if (number < 16)
161 return armv7m_exception_strings[number];
162 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
163 return enamebuf;
164 }
165
166 int armv7m_get_core_reg(reg_t *reg)
167 {
168 int retval;
169 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
170 target_t *target = armv7m_reg->target;
171 armv7m_common_t *armv7m_target = target->arch_info;
172
173 if (target->state != TARGET_HALTED)
174 {
175 return ERROR_TARGET_NOT_HALTED;
176 }
177
178 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
179
180 return retval;
181 }
182
183 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
184 {
185 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
186 target_t *target = armv7m_reg->target;
187 u32 value = buf_get_u32(buf, 0, 32);
188
189 if (target->state != TARGET_HALTED)
190 {
191 return ERROR_TARGET_NOT_HALTED;
192 }
193
194 buf_set_u32(reg->value, 0, 32, value);
195 reg->dirty = 1;
196 reg->valid = 1;
197
198 return ERROR_OK;
199 }
200
201 int armv7m_read_core_reg(struct target_s *target, int num)
202 {
203 u32 reg_value;
204 int retval;
205 armv7m_core_reg_t * armv7m_core_reg;
206
207 /* get pointers to arch-specific information */
208 armv7m_common_t *armv7m = target->arch_info;
209
210 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
211 return ERROR_INVALID_ARGUMENTS;
212
213 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
214 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
215 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
216 armv7m->core_cache->reg_list[num].valid = 1;
217 armv7m->core_cache->reg_list[num].dirty = 0;
218
219 return retval;
220 }
221
222 int armv7m_write_core_reg(struct target_s *target, int num)
223 {
224 int retval;
225 u32 reg_value;
226 armv7m_core_reg_t *armv7m_core_reg;
227
228 /* get pointers to arch-specific information */
229 armv7m_common_t *armv7m = target->arch_info;
230
231 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
232 return ERROR_INVALID_ARGUMENTS;
233
234 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
235 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
236 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
237 if (retval != ERROR_OK)
238 {
239 LOG_ERROR("JTAG failure");
240 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
241 return ERROR_JTAG_DEVICE_ERROR;
242 }
243 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
244 armv7m->core_cache->reg_list[num].valid = 1;
245 armv7m->core_cache->reg_list[num].dirty = 0;
246
247 return ERROR_OK;
248 }
249
250 int armv7m_invalidate_core_regs(target_t *target)
251 {
252 /* get pointers to arch-specific information */
253 armv7m_common_t *armv7m = target->arch_info;
254 int i;
255
256 for (i = 0; i < armv7m->core_cache->num_regs; i++)
257 {
258 armv7m->core_cache->reg_list[i].valid = 0;
259 armv7m->core_cache->reg_list[i].dirty = 0;
260 }
261
262 return ERROR_OK;
263 }
264
265 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
266 {
267 /* get pointers to arch-specific information */
268 armv7m_common_t *armv7m = target->arch_info;
269 int i;
270
271 *reg_list_size = 26;
272 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
273
274 for (i = 0; i < 16; i++)
275 {
276 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
277 }
278
279 for (i = 16; i < 24; i++)
280 {
281 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
282 }
283
284 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
285
286 #ifdef ARMV7_GDB_HACKS
287 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
288 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
289
290 /* ARMV7M is always in thumb mode, try to make GDB understand this
291 * if it does not support this arch */
292 armv7m->core_cache->reg_list[15].value[0] |= 1;
293 #else
294 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
295 #endif
296
297 return ERROR_OK;
298 }
299
300 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
301 {
302 /* get pointers to arch-specific information */
303 armv7m_common_t *armv7m = target->arch_info;
304 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
305 enum armv7m_mode core_mode = armv7m->core_mode;
306 int retval = ERROR_OK;
307 u32 pc;
308 int i;
309 u32 context[ARMV7NUMCOREREGS];
310
311 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
312 {
313 LOG_ERROR("current target isn't an ARMV7M target");
314 return ERROR_TARGET_INVALID;
315 }
316
317 if (target->state != TARGET_HALTED)
318 {
319 LOG_WARNING("target not halted");
320 return ERROR_TARGET_NOT_HALTED;
321 }
322
323 /* refresh core register cache */
324 /* Not needed if core register cache is always consistent with target process state */
325 for (i = 0; i < ARMV7NUMCOREREGS; i++)
326 {
327 if (!armv7m->core_cache->reg_list[i].valid)
328 armv7m->read_core_reg(target, i);
329 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
330 }
331
332 for (i = 0; i < num_mem_params; i++)
333 {
334 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
335 }
336
337 for (i = 0; i < num_reg_params; i++)
338 {
339 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
340 u32 regvalue;
341
342 if (!reg)
343 {
344 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
345 exit(-1);
346 }
347
348 if (reg->size != reg_params[i].size)
349 {
350 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
351 exit(-1);
352 }
353
354 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
355 armv7m_set_core_reg(reg, reg_params[i].value);
356 }
357
358 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
359 {
360 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
361 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
362 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
363 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
364 }
365
366 /* ARMV7M always runs in Thumb state */
367 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
368 {
369 LOG_ERROR("can't add breakpoint to finish algorithm execution");
370 return ERROR_TARGET_FAILURE;
371 }
372
373 /* This code relies on the target specific resume() and poll()->debug_entry()
374 sequence to write register values to the processor and the read them back */
375 if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
376 {
377 return retval;
378 }
379 if((retval = target_poll(target)) != ERROR_OK)
380 {
381 return retval;
382 }
383
384 if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
385 {
386 return retval;
387 }
388 if (target->state != TARGET_HALTED)
389 {
390 if ((retval=target_halt(target))!=ERROR_OK)
391 return retval;
392 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
393 {
394 return retval;
395 }
396 return ERROR_TARGET_TIMEOUT;
397 }
398
399
400 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
401 if (pc != exit_point)
402 {
403 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
404 return ERROR_TARGET_TIMEOUT;
405 }
406
407 breakpoint_remove(target, exit_point);
408
409 /* Read memory values to mem_params[] */
410 for (i = 0; i < num_mem_params; i++)
411 {
412 if (mem_params[i].direction != PARAM_OUT)
413 if((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
414 {
415 return retval;
416 }
417 }
418
419 /* Copy core register values to reg_params[] */
420 for (i = 0; i < num_reg_params; i++)
421 {
422 if (reg_params[i].direction != PARAM_OUT)
423 {
424 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
425
426 if (!reg)
427 {
428 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
429 exit(-1);
430 }
431
432 if (reg->size != reg_params[i].size)
433 {
434 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
435 exit(-1);
436 }
437
438 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
439 }
440 }
441
442 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
443 {
444 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
445 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
446 armv7m->core_cache->reg_list[i].valid = 1;
447 armv7m->core_cache->reg_list[i].dirty = 1;
448 }
449
450 armv7m->core_mode = core_mode;
451
452 return retval;
453 }
454
455 int armv7m_arch_state(struct target_s *target)
456 {
457 /* get pointers to arch-specific information */
458 armv7m_common_t *armv7m = target->arch_info;
459
460 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
461 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
462 armv7m_mode_strings[armv7m->core_mode],
463 armv7m_exception_string(armv7m->exception_number),
464 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
465 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
466
467 return ERROR_OK;
468 }
469
470 reg_cache_t *armv7m_build_reg_cache(target_t *target)
471 {
472 /* get pointers to arch-specific information */
473 armv7m_common_t *armv7m = target->arch_info;
474
475 int num_regs = ARMV7NUMCOREREGS;
476 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
477 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
478 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
479 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
480 int i;
481
482 if (armv7m_core_reg_arch_type == -1)
483 {
484 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
485 }
486
487 register_init_dummy(&armv7m_gdb_dummy_fps_reg);
488 #ifdef ARMV7_GDB_HACKS
489 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
490 #endif
491 register_init_dummy(&armv7m_gdb_dummy_fp_reg);
492
493 /* Build the process context cache */
494 cache->name = "arm v7m registers";
495 cache->next = NULL;
496 cache->reg_list = reg_list;
497 cache->num_regs = num_regs;
498 (*cache_p) = cache;
499 armv7m->core_cache = cache;
500
501 for (i = 0; i < num_regs; i++)
502 {
503 arch_info[i] = armv7m_core_reg_list_arch_info[i];
504 arch_info[i].target = target;
505 arch_info[i].armv7m_common = armv7m;
506 reg_list[i].name = armv7m_core_reg_list[i];
507 reg_list[i].size = 32;
508 reg_list[i].value = calloc(1, 4);
509 reg_list[i].dirty = 0;
510 reg_list[i].valid = 0;
511 reg_list[i].bitfield_desc = NULL;
512 reg_list[i].num_bitfields = 0;
513 reg_list[i].arch_type = armv7m_core_reg_arch_type;
514 reg_list[i].arch_info = &arch_info[i];
515 }
516
517 return cache;
518 }
519
520 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
521 {
522 armv7m_build_reg_cache(target);
523
524 return ERROR_OK;
525 }
526
527 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
528 {
529 /* register arch-specific functions */
530
531 target->arch_info = armv7m;
532 armv7m->read_core_reg = armv7m_read_core_reg;
533 armv7m->write_core_reg = armv7m_write_core_reg;
534
535 return ERROR_OK;
536 }
537
538 int armv7m_register_commands(struct command_context_s *cmd_ctx)
539 {
540 return ERROR_OK;
541 }
542
543 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
544 {
545 working_area_t *crc_algorithm;
546 armv7m_algorithm_t armv7m_info;
547 reg_param_t reg_params[2];
548 int retval;
549
550 u16 cortex_m3_crc_code[] = {
551 0x4602, /* mov r2, r0 */
552 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
553 0x460B, /* mov r3, r1 */
554 0xF04F, 0x0400, /* mov r4, #0 */
555 0xE013, /* b ncomp */
556 /* nbyte: */
557 0x5D11, /* ldrb r1, [r2, r4] */
558 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
559 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
560
561 0xF04F, 0x0500, /* mov r5, #0 */
562 /* loop: */
563 0x2800, /* cmp r0, #0 */
564 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
565 0xF105, 0x0501, /* add r5, r5, #1 */
566 0x4630, /* mov r0, r6 */
567 0xBFB8, /* it lt */
568 0xEA86, 0x0007, /* eor r0, r6, r7 */
569 0x2D08, /* cmp r5, #8 */
570 0xD1F4, /* bne loop */
571
572 0xF104, 0x0401, /* add r4, r4, #1 */
573 /* ncomp: */
574 0x429C, /* cmp r4, r3 */
575 0xD1E9, /* bne nbyte */
576 /* end: */
577 0xE7FE, /* b end */
578 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
579 };
580
581 int i;
582
583 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
584 {
585 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
586 }
587
588 /* convert flash writing code into a buffer in target endianness */
589 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
590 if((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i])) != ERROR_OK)
591 {
592 return retval;
593 }
594
595 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
596 armv7m_info.core_mode = ARMV7M_MODE_ANY;
597
598 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
599 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
600
601 buf_set_u32(reg_params[0].value, 0, 32, address);
602 buf_set_u32(reg_params[1].value, 0, 32, count);
603
604 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
605 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
606 {
607 LOG_ERROR("error executing cortex_m3 crc algorithm");
608 destroy_reg_param(&reg_params[0]);
609 destroy_reg_param(&reg_params[1]);
610 target_free_working_area(target, crc_algorithm);
611 return retval;
612 }
613
614 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
615
616 destroy_reg_param(&reg_params[0]);
617 destroy_reg_param(&reg_params[1]);
618
619 target_free_working_area(target, crc_algorithm);
620
621 return ERROR_OK;
622 }
623
624 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
625 {
626 working_area_t *erase_check_algorithm;
627 reg_param_t reg_params[3];
628 armv7m_algorithm_t armv7m_info;
629 int retval;
630 int i;
631
632 u16 erase_check_code[] =
633 {
634 /* loop: */
635 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
636 0xEA02, 0x0203, /* and r2, r2, r3 */
637 0x3901, /* subs r1, r1, #1 */
638 0xD1F9, /* bne loop */
639 /* end: */
640 0xE7FE, /* b end */
641 };
642
643 /* make sure we have a working area */
644 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
645 {
646 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
647 }
648
649 /* convert flash writing code into a buffer in target endianness */
650 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
651 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
652
653 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
654 armv7m_info.core_mode = ARMV7M_MODE_ANY;
655
656 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
657 buf_set_u32(reg_params[0].value, 0, 32, address);
658
659 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
660 buf_set_u32(reg_params[1].value, 0, 32, count);
661
662 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
663 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
664
665 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
666 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
667 {
668 destroy_reg_param(&reg_params[0]);
669 destroy_reg_param(&reg_params[1]);
670 destroy_reg_param(&reg_params[2]);
671 target_free_working_area(target, erase_check_algorithm);
672 return 0;
673 }
674
675 *blank = buf_get_u32(reg_params[2].value, 0, 32);
676
677 destroy_reg_param(&reg_params[0]);
678 destroy_reg_param(&reg_params[1]);
679 destroy_reg_param(&reg_params[2]);
680
681 target_free_working_area(target, erase_check_algorithm);
682
683 return ERROR_OK;
684 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)