armv7m: improve error handling
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 √ėyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
31 * *
32 ***************************************************************************/
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36
37 #include "breakpoints.h"
38 #include "armv7m.h"
39 #include "algorithm.h"
40 #include "register.h"
41
42
43 #if 0
44 #define _DEBUG_INSTRUCTION_EXECUTION_
45 #endif
46
47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
48 char *armv7m_mode_strings[] =
49 {
50 "Thread", "Thread (User)", "Handler",
51 };
52
53 static char *armv7m_exception_strings[] =
54 {
55 "", "Reset", "NMI", "HardFault",
56 "MemManage", "BusFault", "UsageFault", "RESERVED",
57 "RESERVED", "RESERVED", "RESERVED", "SVCall",
58 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
59 };
60
61 #ifdef ARMV7_GDB_HACKS
62 uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
63
64 struct reg armv7m_gdb_dummy_cpsr_reg =
65 {
66 .name = "GDB dummy cpsr register",
67 .value = armv7m_gdb_dummy_cpsr_value,
68 .dirty = 0,
69 .valid = 1,
70 .size = 32,
71 .arch_info = NULL,
72 };
73 #endif
74
75 /*
76 * These registers are not memory-mapped. The ARMv7-M profile includes
77 * memory mapped registers too, such as for the NVIC (interrupt controller)
78 * and SysTick (timer) modules; those can mostly be treated as peripherals.
79 *
80 * The ARMv6-M profile is almost identical in this respect, except that it
81 * doesn't include basepri or faultmask registers.
82 */
83 static const struct {
84 unsigned id;
85 const char *name;
86 unsigned bits;
87 } armv7m_regs[] = {
88 { ARMV7M_R0, "r0", 32 },
89 { ARMV7M_R1, "r1", 32 },
90 { ARMV7M_R2, "r2", 32 },
91 { ARMV7M_R3, "r3", 32 },
92
93 { ARMV7M_R4, "r4", 32 },
94 { ARMV7M_R5, "r5", 32 },
95 { ARMV7M_R6, "r6", 32 },
96 { ARMV7M_R7, "r7", 32 },
97
98 { ARMV7M_R8, "r8", 32 },
99 { ARMV7M_R9, "r9", 32 },
100 { ARMV7M_R10, "r10", 32 },
101 { ARMV7M_R11, "r11", 32 },
102
103 { ARMV7M_R12, "r12", 32 },
104 { ARMV7M_R13, "sp", 32 },
105 { ARMV7M_R14, "lr", 32 },
106 { ARMV7M_PC, "pc", 32 },
107
108 { ARMV7M_xPSR, "xPSR", 32 },
109 { ARMV7M_MSP, "msp", 32 },
110 { ARMV7M_PSP, "psp", 32 },
111
112 { ARMV7M_PRIMASK, "primask", 1 },
113 { ARMV7M_BASEPRI, "basepri", 8 },
114 { ARMV7M_FAULTMASK, "faultmask", 1 },
115 { ARMV7M_CONTROL, "control", 2 },
116 };
117
118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
119
120 /**
121 * Restores target context using the cache of core registers set up
122 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
123 */
124 int armv7m_restore_context(struct target *target)
125 {
126 int i;
127 struct armv7m_common *armv7m = target_to_armv7m(target);
128
129 LOG_DEBUG(" ");
130
131 if (armv7m->pre_restore_context)
132 armv7m->pre_restore_context(target);
133
134 for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
135 {
136 if (armv7m->core_cache->reg_list[i].dirty)
137 {
138 armv7m->write_core_reg(target, i);
139 }
140 }
141
142 return ERROR_OK;
143 }
144
145 /* Core state functions */
146
147 /**
148 * Maps ISR number (from xPSR) to name.
149 * Note that while names and meanings for the first sixteen are standardized
150 * (with zero not a true exception), external interrupts are only numbered.
151 * They are assigned by vendors, which generally assign different numbers to
152 * peripherals (such as UART0 or a USB peripheral controller).
153 */
154 char *armv7m_exception_string(int number)
155 {
156 static char enamebuf[32];
157
158 if ((number < 0) | (number > 511))
159 return "Invalid exception";
160 if (number < 16)
161 return armv7m_exception_strings[number];
162 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
163 return enamebuf;
164 }
165
166 static int armv7m_get_core_reg(struct reg *reg)
167 {
168 int retval;
169 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
170 struct target *target = armv7m_reg->target;
171 struct armv7m_common *armv7m = target_to_armv7m(target);
172
173 if (target->state != TARGET_HALTED)
174 {
175 return ERROR_TARGET_NOT_HALTED;
176 }
177
178 retval = armv7m->read_core_reg(target, armv7m_reg->num);
179
180 return retval;
181 }
182
183 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
184 {
185 struct armv7m_core_reg *armv7m_reg = reg->arch_info;
186 struct target *target = armv7m_reg->target;
187 uint32_t value = buf_get_u32(buf, 0, 32);
188
189 if (target->state != TARGET_HALTED)
190 {
191 return ERROR_TARGET_NOT_HALTED;
192 }
193
194 buf_set_u32(reg->value, 0, 32, value);
195 reg->dirty = 1;
196 reg->valid = 1;
197
198 return ERROR_OK;
199 }
200
201 static int armv7m_read_core_reg(struct target *target, unsigned num)
202 {
203 uint32_t reg_value;
204 int retval;
205 struct armv7m_core_reg * armv7m_core_reg;
206 struct armv7m_common *armv7m = target_to_armv7m(target);
207
208 if (num >= ARMV7M_NUM_REGS)
209 return ERROR_INVALID_ARGUMENTS;
210
211 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
212 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
213 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
214 armv7m->core_cache->reg_list[num].valid = 1;
215 armv7m->core_cache->reg_list[num].dirty = 0;
216
217 return retval;
218 }
219
220 static int armv7m_write_core_reg(struct target *target, unsigned num)
221 {
222 int retval;
223 uint32_t reg_value;
224 struct armv7m_core_reg *armv7m_core_reg;
225 struct armv7m_common *armv7m = target_to_armv7m(target);
226
227 if (num >= ARMV7M_NUM_REGS)
228 return ERROR_INVALID_ARGUMENTS;
229
230 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
231 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
232 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
233 if (retval != ERROR_OK)
234 {
235 LOG_ERROR("JTAG failure");
236 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
237 return ERROR_JTAG_DEVICE_ERROR;
238 }
239 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
240 armv7m->core_cache->reg_list[num].valid = 1;
241 armv7m->core_cache->reg_list[num].dirty = 0;
242
243 return ERROR_OK;
244 }
245
246 /**
247 * Returns generic ARM userspace registers to GDB.
248 * GDB doesn't quite understand that most ARMs don't have floating point
249 * hardware, so this also fakes a set of long-obsolete FPA registers that
250 * are not used in EABI based software stacks.
251 */
252 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
253 {
254 struct armv7m_common *armv7m = target_to_armv7m(target);
255 int i;
256
257 *reg_list_size = 26;
258 *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
259
260 /*
261 * GDB register packet format for ARM:
262 * - the first 16 registers are r0..r15
263 * - (obsolete) 8 FPA registers
264 * - (obsolete) FPA status
265 * - CPSR
266 */
267 for (i = 0; i < 16; i++)
268 {
269 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
270 }
271
272 for (i = 16; i < 24; i++)
273 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
274 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
275
276 #ifdef ARMV7_GDB_HACKS
277 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
278 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
279
280 /* ARMV7M is always in thumb mode, try to make GDB understand this
281 * if it does not support this arch */
282 *((char*)armv7m->arm.pc->value) |= 1;
283 #else
284 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
285 #endif
286
287 return ERROR_OK;
288 }
289
290 /** Runs a Thumb algorithm in the target. */
291 int armv7m_run_algorithm(struct target *target,
292 int num_mem_params, struct mem_param *mem_params,
293 int num_reg_params, struct reg_param *reg_params,
294 uint32_t entry_point, uint32_t exit_point,
295 int timeout_ms, void *arch_info)
296 {
297 int retval;
298
299 retval = armv7m_start_algorithm(target,
300 num_mem_params, mem_params,
301 num_reg_params, reg_params,
302 entry_point, exit_point,
303 arch_info);
304
305 if (retval == ERROR_OK)
306 retval = armv7m_wait_algorithm(target,
307 num_mem_params, mem_params,
308 num_reg_params, reg_params,
309 exit_point, timeout_ms,
310 arch_info);
311
312 return retval;
313 }
314
315 /** Starts a Thumb algorithm in the target. */
316 int armv7m_start_algorithm(struct target *target,
317 int num_mem_params, struct mem_param *mem_params,
318 int num_reg_params, struct reg_param *reg_params,
319 uint32_t entry_point, uint32_t exit_point,
320 void *arch_info)
321 {
322 struct armv7m_common *armv7m = target_to_armv7m(target);
323 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
324 enum armv7m_mode core_mode = armv7m->core_mode;
325 int retval = ERROR_OK;
326
327 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
328 * at the exit point */
329
330 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
331 {
332 LOG_ERROR("current target isn't an ARMV7M target");
333 return ERROR_TARGET_INVALID;
334 }
335
336 if (target->state != TARGET_HALTED)
337 {
338 LOG_WARNING("target not halted");
339 return ERROR_TARGET_NOT_HALTED;
340 }
341
342 /* refresh core register cache */
343 /* Not needed if core register cache is always consistent with target process state */
344 for (unsigned i = 0; i < ARMV7M_NUM_REGS; i++)
345 {
346 if (!armv7m->core_cache->reg_list[i].valid)
347 armv7m->read_core_reg(target, i);
348 armv7m_algorithm_info->context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
349 }
350
351 for (int i = 0; i < num_mem_params; i++)
352 {
353 // TODO: Write only out params
354 if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
355 return retval;
356 }
357
358 for (int i = 0; i < num_reg_params; i++)
359 {
360 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
361 // uint32_t regvalue;
362
363 if (!reg)
364 {
365 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
366 return ERROR_INVALID_ARGUMENTS;
367 }
368
369 if (reg->size != reg_params[i].size)
370 {
371 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
372 return ERROR_INVALID_ARGUMENTS;
373 }
374
375 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
376 armv7m_set_core_reg(reg, reg_params[i].value);
377 }
378
379 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
380 {
381 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
382 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value,
383 0, 1, armv7m_algorithm_info->core_mode);
384 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
385 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
386 }
387 armv7m_algorithm_info->core_mode = core_mode;
388
389 retval = target_resume(target, 0, entry_point, 1, 1);
390
391 return retval;
392 }
393
394 /** Waits for an algorithm in the target. */
395 int armv7m_wait_algorithm(struct target *target,
396 int num_mem_params, struct mem_param *mem_params,
397 int num_reg_params, struct reg_param *reg_params,
398 uint32_t exit_point, int timeout_ms,
399 void *arch_info)
400 {
401 struct armv7m_common *armv7m = target_to_armv7m(target);
402 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
403 int retval = ERROR_OK;
404 uint32_t pc;
405
406 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
407 * at the exit point */
408
409 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
410 {
411 LOG_ERROR("current target isn't an ARMV7M target");
412 return ERROR_TARGET_INVALID;
413 }
414
415 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
416 /* If the target fails to halt due to the breakpoint, force a halt */
417 if (retval != ERROR_OK || target->state != TARGET_HALTED)
418 {
419 if ((retval = target_halt(target)) != ERROR_OK)
420 return retval;
421 if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
422 {
423 return retval;
424 }
425 return ERROR_TARGET_TIMEOUT;
426 }
427
428 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
429 if (exit_point && (pc != exit_point))
430 {
431 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32 , pc, exit_point);
432 return ERROR_TARGET_TIMEOUT;
433 }
434
435 /* Read memory values to mem_params[] */
436 for (int i = 0; i < num_mem_params; i++)
437 {
438 if (mem_params[i].direction != PARAM_OUT)
439 if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
440 {
441 return retval;
442 }
443 }
444
445 /* Copy core register values to reg_params[] */
446 for (int i = 0; i < num_reg_params; i++)
447 {
448 if (reg_params[i].direction != PARAM_OUT)
449 {
450 struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
451
452 if (!reg)
453 {
454 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
455 return ERROR_INVALID_ARGUMENTS;
456 }
457
458 if (reg->size != reg_params[i].size)
459 {
460 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
461 return ERROR_INVALID_ARGUMENTS;
462 }
463
464 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
465 }
466 }
467
468 for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
469 {
470 uint32_t regvalue;
471 regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
472 if (regvalue != armv7m_algorithm_info->context[i])
473 {
474 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
475 armv7m->core_cache->reg_list[i].name, armv7m_algorithm_info->context[i]);
476 buf_set_u32(armv7m->core_cache->reg_list[i].value,
477 0, 32, armv7m_algorithm_info->context[i]);
478 armv7m->core_cache->reg_list[i].valid = 1;
479 armv7m->core_cache->reg_list[i].dirty = 1;
480 }
481 }
482
483 armv7m->core_mode = armv7m_algorithm_info->core_mode;
484
485 return retval;
486 }
487
488 /** Logs summary of ARMv7-M state for a halted target. */
489 int armv7m_arch_state(struct target *target)
490 {
491 struct armv7m_common *armv7m = target_to_armv7m(target);
492 struct arm *arm = &armv7m->arm;
493 uint32_t ctrl, sp;
494
495 ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
496 sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
497
498 LOG_USER("target halted due to %s, current mode: %s %s\n"
499 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s",
500 debug_reason_name(target),
501 armv7m_mode_strings[armv7m->core_mode],
502 armv7m_exception_string(armv7m->exception_number),
503 buf_get_u32(arm->cpsr->value, 0, 32),
504 buf_get_u32(arm->pc->value, 0, 32),
505 (ctrl & 0x02) ? 'p' : 'm',
506 sp,
507 arm->is_semihosting ? ", semihosting" : "");
508
509 return ERROR_OK;
510 }
511 static const struct reg_arch_type armv7m_reg_type = {
512 .get = armv7m_get_core_reg,
513 .set = armv7m_set_core_reg,
514 };
515
516 /** Builds cache of architecturally defined registers. */
517 struct reg_cache *armv7m_build_reg_cache(struct target *target)
518 {
519 struct armv7m_common *armv7m = target_to_armv7m(target);
520 struct arm *arm = &armv7m->arm;
521 int num_regs = ARMV7M_NUM_REGS;
522 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
523 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
524 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
525 struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
526 int i;
527
528 #ifdef ARMV7_GDB_HACKS
529 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
530 #endif
531
532 /* Build the process context cache */
533 cache->name = "arm v7m registers";
534 cache->next = NULL;
535 cache->reg_list = reg_list;
536 cache->num_regs = num_regs;
537 (*cache_p) = cache;
538 armv7m->core_cache = cache;
539
540 for (i = 0; i < num_regs; i++)
541 {
542 arch_info[i].num = armv7m_regs[i].id;
543 arch_info[i].target = target;
544 arch_info[i].armv7m_common = armv7m;
545 reg_list[i].name = armv7m_regs[i].name;
546 reg_list[i].size = armv7m_regs[i].bits;
547 reg_list[i].value = calloc(1, 4);
548 reg_list[i].dirty = 0;
549 reg_list[i].valid = 0;
550 reg_list[i].type = &armv7m_reg_type;
551 reg_list[i].arch_info = &arch_info[i];
552 }
553
554 arm->cpsr = reg_list + ARMV7M_xPSR;
555 arm->pc = reg_list + ARMV7M_PC;
556 arm->core_cache = cache;
557 return cache;
558 }
559
560 static int armv7m_setup_semihosting(struct target *target, int enable)
561 {
562 /* nothing todo for armv7m */
563 return ERROR_OK;
564 }
565
566 /** Sets up target as a generic ARMv7-M core */
567 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
568 {
569 struct arm *arm = &armv7m->arm;
570
571 armv7m->common_magic = ARMV7M_COMMON_MAGIC;
572
573 arm->core_type = ARM_MODE_THREAD;
574 arm->arch_info = armv7m;
575 arm->setup_semihosting = armv7m_setup_semihosting;
576
577 /* FIXME remove v7m-specific r/w core_reg functions;
578 * use the generic ARM core support..
579 */
580 armv7m->read_core_reg = armv7m_read_core_reg;
581 armv7m->write_core_reg = armv7m_write_core_reg;
582
583 return arm_init_arch_info(target, arm);
584 }
585
586 /** Generates a CRC32 checksum of a memory region. */
587 int armv7m_checksum_memory(struct target *target,
588 uint32_t address, uint32_t count, uint32_t* checksum)
589 {
590 struct working_area *crc_algorithm;
591 struct armv7m_algorithm armv7m_info;
592 struct reg_param reg_params[2];
593 int retval;
594
595 /* see contib/loaders/checksum/armv7m_crc.s for src */
596
597 static const uint16_t cortex_m3_crc_code[] = {
598 0x4602, /* mov r2, r0 */
599 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
600 0x460B, /* mov r3, r1 */
601 0xF04F, 0x0400, /* mov r4, #0 */
602 0xE013, /* b ncomp */
603 /* nbyte: */
604 0x5D11, /* ldrb r1, [r2, r4] */
605 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
606 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
607
608 0xF04F, 0x0500, /* mov r5, #0 */
609 /* loop: */
610 0x2800, /* cmp r0, #0 */
611 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
612 0xF105, 0x0501, /* add r5, r5, #1 */
613 0x4630, /* mov r0, r6 */
614 0xBFB8, /* it lt */
615 0xEA86, 0x0007, /* eor r0, r6, r7 */
616 0x2D08, /* cmp r5, #8 */
617 0xD1F4, /* bne loop */
618
619 0xF104, 0x0401, /* add r4, r4, #1 */
620 /* ncomp: */
621 0x429C, /* cmp r4, r3 */
622 0xD1E9, /* bne nbyte */
623 0xBE00, /* bkpt #0 */
624 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
625 };
626
627 uint32_t i;
628
629 retval = target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm);
630 if (retval != ERROR_OK)
631 return retval;
632
633 /* convert flash writing code into a buffer in target endianness */
634 for (i = 0; i < ARRAY_SIZE(cortex_m3_crc_code); i++) {
635 retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i]);
636 if (retval != ERROR_OK)
637 goto cleanup;
638 }
639
640 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
641 armv7m_info.core_mode = ARMV7M_MODE_ANY;
642
643 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
644 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
645
646 buf_set_u32(reg_params[0].value, 0, 32, address);
647 buf_set_u32(reg_params[1].value, 0, 32, count);
648
649 int timeout = 20000 * (1 + (count / (1024 * 1024)));
650
651 retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
652 crc_algorithm->address + (sizeof(cortex_m3_crc_code) - 6),
653 timeout, &armv7m_info);
654
655 if (retval == ERROR_OK)
656 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
657 else
658 LOG_ERROR("error executing cortex_m3 crc algorithm");
659
660 destroy_reg_param(&reg_params[0]);
661 destroy_reg_param(&reg_params[1]);
662
663 cleanup:
664 target_free_working_area(target, crc_algorithm);
665
666 return retval;
667 }
668
669 /** Checks whether a memory region is zeroed. */
670 int armv7m_blank_check_memory(struct target *target,
671 uint32_t address, uint32_t count, uint32_t* blank)
672 {
673 struct working_area *erase_check_algorithm;
674 struct reg_param reg_params[3];
675 struct armv7m_algorithm armv7m_info;
676 int retval;
677 uint32_t i;
678
679 static const uint16_t erase_check_code[] =
680 {
681 /* loop: */
682 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
683 0xEA02, 0x0203, /* and r2, r2, r3 */
684 0x3901, /* subs r1, r1, #1 */
685 0xD1F9, /* bne loop */
686 0xBE00, /* bkpt #0 */
687 };
688
689 /* make sure we have a working area */
690 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
691 {
692 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
693 }
694
695 /* convert flash writing code into a buffer in target endianness */
696 for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
697 target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
698
699 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
700 armv7m_info.core_mode = ARMV7M_MODE_ANY;
701
702 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
703 buf_set_u32(reg_params[0].value, 0, 32, address);
704
705 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
706 buf_set_u32(reg_params[1].value, 0, 32, count);
707
708 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
709 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
710
711 retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address,
712 erase_check_algorithm->address + (sizeof(erase_check_code) - 2),
713 10000, &armv7m_info);
714
715 if (retval == ERROR_OK)
716 *blank = buf_get_u32(reg_params[2].value, 0, 32);
717
718 destroy_reg_param(&reg_params[0]);
719 destroy_reg_param(&reg_params[1]);
720 destroy_reg_param(&reg_params[2]);
721
722 target_free_working_area(target, erase_check_algorithm);
723
724 return retval;
725 }
726
727 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
728 {
729 struct armv7m_common *armv7m = target_to_armv7m(target);
730 struct reg *r = armv7m->arm.pc;
731 bool result = false;
732
733
734 /* if we halted last time due to a bkpt instruction
735 * then we have to manually step over it, otherwise
736 * the core will break again */
737
738 if (target->debug_reason == DBG_REASON_BREAKPOINT)
739 {
740 uint16_t op;
741 uint32_t pc = buf_get_u32(r->value, 0, 32);
742
743 pc &= ~1;
744 if (target_read_u16(target, pc, &op) == ERROR_OK)
745 {
746 if ((op & 0xFF00) == 0xBE00)
747 {
748 pc = buf_get_u32(r->value, 0, 32) + 2;
749 buf_set_u32(r->value, 0, 32, pc);
750 r->dirty = true;
751 r->valid = true;
752 result = true;
753 LOG_DEBUG("Skipping over BKPT instruction");
754 }
755 }
756 }
757
758 if (inst_found) {
759 *inst_found = result;
760 }
761
762 return ERROR_OK;
763 }
764
765 const struct command_registration armv7m_command_handlers[] = {
766 {
767 .chain = arm_command_handlers,
768 },
769 {
770 .chain = dap_command_handlers,
771 },
772 COMMAND_REGISTRATION_DONE
773 };