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- moved flash erase_check target code to target.c
[openocd.git] / src / target / armv7m.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "armv7m.h"
30 #include "register.h"
31 #include "target.h"
32 #include "log.h"
33 #include "jtag.h"
34 #include "arm_jtag.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 char* armv7m_mode_strings[] =
44 {
45 "Thread", "Thread (User)", "Handler",
46 };
47
48 char* armv7m_exception_strings[] =
49 {
50 "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
51 "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
52 };
53
54 char* armv7m_core_reg_list[] =
55 {
56 /* Registers accessed through core debug */
57 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
58 "sp", "lr", "pc",
59 "xPSR", "msp", "psp",
60 /* Registers accessed through special reg 20 */
61 "primask", "basepri", "faultmask", "control"
62 };
63
64 u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
65
66 reg_t armv7m_gdb_dummy_fp_reg =
67 {
68 "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
69 };
70
71 u8 armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
72
73 reg_t armv7m_gdb_dummy_fps_reg =
74 {
75 "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
76 };
77
78 #ifdef ARMV7_GDB_HACKS
79 u8 armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
80
81 reg_t armv7m_gdb_dummy_cpsr_reg =
82 {
83 "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
84 };
85 #endif
86
87 armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
88 {
89 /* CORE_GP are accesible using the core debug registers */
90 {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
91 {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
92 {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
93 {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
94 {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
95 {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
96 {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
97 {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
98 {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
99 {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
100 {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
101 {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
102 {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
103 {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
104 {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
105 {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
106
107 {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
108 {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
109 {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
110
111 /* CORE_SP are accesible using coreregister 20 */
112 {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
113 {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
114 {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
115 {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
116 };
117
118 int armv7m_core_reg_arch_type = -1;
119
120 int armv7m_restore_context(target_t *target)
121 {
122 int i;
123
124 /* get pointers to arch-specific information */
125 armv7m_common_t *armv7m = target->arch_info;
126
127 LOG_DEBUG(" ");
128
129 if (armv7m->pre_restore_context)
130 armv7m->pre_restore_context(target);
131
132 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
133 {
134 if (armv7m->core_cache->reg_list[i].dirty)
135 {
136 armv7m->write_core_reg(target, i);
137 }
138 }
139
140 if (armv7m->post_restore_context)
141 armv7m->post_restore_context(target);
142
143 return ERROR_OK;
144 }
145
146 /* Core state functions */
147 char *armv7m_exception_string(int number)
148 {
149 static char enamebuf[32];
150
151 if ((number < 0) | (number > 511))
152 return "Invalid exception";
153 if (number < 16)
154 return armv7m_exception_strings[number];
155 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
156 return enamebuf;
157 }
158
159 int armv7m_get_core_reg(reg_t *reg)
160 {
161 int retval;
162 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
163 target_t *target = armv7m_reg->target;
164 armv7m_common_t *armv7m_target = target->arch_info;
165
166 if (target->state != TARGET_HALTED)
167 {
168 return ERROR_TARGET_NOT_HALTED;
169 }
170
171 retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
172
173 return retval;
174 }
175
176 int armv7m_set_core_reg(reg_t *reg, u8 *buf)
177 {
178 armv7m_core_reg_t *armv7m_reg = reg->arch_info;
179 target_t *target = armv7m_reg->target;
180 u32 value = buf_get_u32(buf, 0, 32);
181
182 if (target->state != TARGET_HALTED)
183 {
184 return ERROR_TARGET_NOT_HALTED;
185 }
186
187 buf_set_u32(reg->value, 0, 32, value);
188 reg->dirty = 1;
189 reg->valid = 1;
190
191 return ERROR_OK;
192 }
193
194 int armv7m_read_core_reg(struct target_s *target, int num)
195 {
196 u32 reg_value;
197 int retval;
198 armv7m_core_reg_t * armv7m_core_reg;
199
200 /* get pointers to arch-specific information */
201 armv7m_common_t *armv7m = target->arch_info;
202
203 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
204 return ERROR_INVALID_ARGUMENTS;
205
206 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
207 retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, &reg_value);
208 buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
209 armv7m->core_cache->reg_list[num].valid = 1;
210 armv7m->core_cache->reg_list[num].dirty = 0;
211
212 return ERROR_OK;
213 }
214
215 int armv7m_write_core_reg(struct target_s *target, int num)
216 {
217 int retval;
218 u32 reg_value;
219 armv7m_core_reg_t *armv7m_core_reg;
220
221 /* get pointers to arch-specific information */
222 armv7m_common_t *armv7m = target->arch_info;
223
224 if ((num < 0) || (num >= ARMV7NUMCOREREGS))
225 return ERROR_INVALID_ARGUMENTS;
226
227 reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
228 armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
229 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
230 if (retval != ERROR_OK)
231 {
232 LOG_ERROR("JTAG failure");
233 armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
234 return ERROR_JTAG_DEVICE_ERROR;
235 }
236 LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
237 armv7m->core_cache->reg_list[num].valid = 1;
238 armv7m->core_cache->reg_list[num].dirty = 0;
239
240 return ERROR_OK;
241 }
242
243 int armv7m_invalidate_core_regs(target_t *target)
244 {
245 /* get pointers to arch-specific information */
246 armv7m_common_t *armv7m = target->arch_info;
247 int i;
248
249 for (i = 0; i < armv7m->core_cache->num_regs; i++)
250 {
251 armv7m->core_cache->reg_list[i].valid = 0;
252 armv7m->core_cache->reg_list[i].dirty = 0;
253 }
254
255 return ERROR_OK;
256 }
257
258 int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
259 {
260 /* get pointers to arch-specific information */
261 armv7m_common_t *armv7m = target->arch_info;
262 int i;
263
264 *reg_list_size = 26;
265 *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
266
267 for (i = 0; i < 16; i++)
268 {
269 (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
270 }
271
272 for (i = 16; i < 24; i++)
273 {
274 (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
275 }
276
277 (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
278
279 #ifdef ARMV7_GDB_HACKS
280 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
281 (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
282
283 /* ARMV7M is always in thumb mode, try to make GDB understand this
284 * if it does not support this arch */
285 armv7m->core_cache->reg_list[15].value[0] |= 1;
286 #else
287 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
288 #endif
289
290 return ERROR_OK;
291 }
292
293 int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
294 {
295 /* get pointers to arch-specific information */
296 armv7m_common_t *armv7m = target->arch_info;
297 armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
298 enum armv7m_mode core_mode = armv7m->core_mode;
299 int retval = ERROR_OK;
300 u32 pc;
301 int i;
302 u32 context[ARMV7NUMCOREREGS];
303
304 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
305 {
306 LOG_ERROR("current target isn't an ARMV7M target");
307 return ERROR_TARGET_INVALID;
308 }
309
310 if (target->state != TARGET_HALTED)
311 {
312 LOG_WARNING("target not halted");
313 return ERROR_TARGET_NOT_HALTED;
314 }
315
316 /* refresh core register cache */
317 /* Not needed if core register cache is always consistent with target process state */
318 for (i = 0; i < ARMV7NUMCOREREGS; i++)
319 {
320 if (!armv7m->core_cache->reg_list[i].valid)
321 armv7m->read_core_reg(target, i);
322 context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
323 }
324
325 for (i = 0; i < num_mem_params; i++)
326 {
327 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
328 }
329
330 for (i = 0; i < num_reg_params; i++)
331 {
332 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
333 u32 regvalue;
334
335 if (!reg)
336 {
337 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
338 exit(-1);
339 }
340
341 if (reg->size != reg_params[i].size)
342 {
343 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
344 exit(-1);
345 }
346
347 regvalue = buf_get_u32(reg_params[i].value, 0, 32);
348 armv7m_set_core_reg(reg, reg_params[i].value);
349 }
350
351 if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
352 {
353 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
354 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
355 armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
356 armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
357 }
358
359 /* ARMV7M always runs in Thumb state */
360 if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
361 {
362 LOG_ERROR("can't add breakpoint to finish algorithm execution");
363 return ERROR_TARGET_FAILURE;
364 }
365
366 /* This code relies on the target specific resume() and poll()->debug_entry()
367 sequence to write register values to the processor and the read them back */
368 target_resume(target, 0, entry_point, 1, 1);
369 target_poll(target);
370
371 while (target->state != TARGET_HALTED)
372 {
373 usleep(5000);
374 target_poll(target);
375 if ((timeout_ms -= 5) <= 0)
376 {
377 LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
378 target_halt(target);
379 timeout_ms = 1000;
380 while (target->state != TARGET_HALTED)
381 {
382 usleep(10000);
383 target_poll(target);
384 if ((timeout_ms -= 10) <= 0)
385 {
386 LOG_ERROR("target didn't reenter debug state, exiting");
387 exit(-1);
388 }
389 }
390 armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
391 LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
392 retval = ERROR_TARGET_TIMEOUT;
393 }
394 }
395
396 breakpoint_remove(target, exit_point);
397
398 /* Read memory values to mem_params[] */
399 for (i = 0; i < num_mem_params; i++)
400 {
401 if (mem_params[i].direction != PARAM_OUT)
402 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
403 }
404
405 /* Copy core register values to reg_params[] */
406 for (i = 0; i < num_reg_params; i++)
407 {
408 if (reg_params[i].direction != PARAM_OUT)
409 {
410 reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
411
412 if (!reg)
413 {
414 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
415 exit(-1);
416 }
417
418 if (reg->size != reg_params[i].size)
419 {
420 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
421 exit(-1);
422 }
423
424 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
425 }
426 }
427
428 for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
429 {
430 LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
431 buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
432 armv7m->core_cache->reg_list[i].valid = 1;
433 armv7m->core_cache->reg_list[i].dirty = 1;
434 }
435
436 armv7m->core_mode = core_mode;
437
438 return retval;
439 }
440
441 int armv7m_arch_state(struct target_s *target)
442 {
443 /* get pointers to arch-specific information */
444 armv7m_common_t *armv7m = target->arch_info;
445
446 LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
447 target_debug_reason_strings[target->debug_reason],
448 armv7m_mode_strings[armv7m->core_mode],
449 armv7m_exception_string(armv7m->exception_number),
450 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
451 buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
452
453 return ERROR_OK;
454 }
455
456 reg_cache_t *armv7m_build_reg_cache(target_t *target)
457 {
458 /* get pointers to arch-specific information */
459 armv7m_common_t *armv7m = target->arch_info;
460
461 int num_regs = ARMV7NUMCOREREGS;
462 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
463 reg_cache_t *cache = malloc(sizeof(reg_cache_t));
464 reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
465 armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
466 int i;
467
468 if (armv7m_core_reg_arch_type == -1)
469 armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
470
471 /* Build the process context cache */
472 cache->name = "arm v7m registers";
473 cache->next = NULL;
474 cache->reg_list = reg_list;
475 cache->num_regs = num_regs;
476 (*cache_p) = cache;
477 armv7m->core_cache = cache;
478
479 for (i = 0; i < num_regs; i++)
480 {
481 arch_info[i] = armv7m_core_reg_list_arch_info[i];
482 arch_info[i].target = target;
483 arch_info[i].armv7m_common = armv7m;
484 reg_list[i].name = armv7m_core_reg_list[i];
485 reg_list[i].size = 32;
486 reg_list[i].value = calloc(1, 4);
487 reg_list[i].dirty = 0;
488 reg_list[i].valid = 0;
489 reg_list[i].bitfield_desc = NULL;
490 reg_list[i].num_bitfields = 0;
491 reg_list[i].arch_type = armv7m_core_reg_arch_type;
492 reg_list[i].arch_info = &arch_info[i];
493 }
494
495 return cache;
496 }
497
498 int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
499 {
500 armv7m_build_reg_cache(target);
501
502 return ERROR_OK;
503 }
504
505 int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
506 {
507 /* register arch-specific functions */
508
509 target->arch_info = armv7m;
510 armv7m->read_core_reg = armv7m_read_core_reg;
511 armv7m->write_core_reg = armv7m_write_core_reg;
512
513 return ERROR_OK;
514 }
515
516 int armv7m_register_commands(struct command_context_s *cmd_ctx)
517 {
518 return ERROR_OK;
519 }
520
521 int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
522 {
523 working_area_t *crc_algorithm;
524 armv7m_algorithm_t armv7m_info;
525 reg_param_t reg_params[2];
526 int retval;
527
528 u16 cortex_m3_crc_code[] = {
529 0x4602, /* mov r2, r0 */
530 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
531 0x460B, /* mov r3, r1 */
532 0xF04F, 0x0400, /* mov r4, #0 */
533 0xE013, /* b ncomp */
534 /* nbyte: */
535 0x5D11, /* ldrb r1, [r2, r4] */
536 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
537 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
538
539 0xF04F, 0x0500, /* mov r5, #0 */
540 /* loop: */
541 0x2800, /* cmp r0, #0 */
542 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
543 0xF105, 0x0501, /* add r5, r5, #1 */
544 0x4630, /* mov r0, r6 */
545 0xBFB8, /* it lt */
546 0xEA86, 0x0007, /* eor r0, r6, r7 */
547 0x2D08, /* cmp r5, #8 */
548 0xD1F4, /* bne loop */
549
550 0xF104, 0x0401, /* add r4, r4, #1 */
551 /* ncomp: */
552 0x429C, /* cmp r4, r3 */
553 0xD1E9, /* bne nbyte */
554 /* end: */
555 0xE7FE, /* b end */
556 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
557 };
558
559 int i;
560
561 if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
562 {
563 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
564 }
565
566 /* convert flash writing code into a buffer in target endianness */
567 for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
568 target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
569
570 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
571 armv7m_info.core_mode = ARMV7M_MODE_ANY;
572
573 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
574 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
575
576 buf_set_u32(reg_params[0].value, 0, 32, address);
577 buf_set_u32(reg_params[1].value, 0, 32, count);
578
579 if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
580 crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
581 {
582 LOG_ERROR("error executing cortex_m3 crc algorithm");
583 destroy_reg_param(&reg_params[0]);
584 destroy_reg_param(&reg_params[1]);
585 target_free_working_area(target, crc_algorithm);
586 return retval;
587 }
588
589 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
590
591 destroy_reg_param(&reg_params[0]);
592 destroy_reg_param(&reg_params[1]);
593
594 target_free_working_area(target, crc_algorithm);
595
596 return ERROR_OK;
597 }
598
599 int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank)
600 {
601 working_area_t *erase_check_algorithm;
602 reg_param_t reg_params[3];
603 armv7m_algorithm_t armv7m_info;
604 int retval;
605 int i;
606
607 u16 erase_check_code[] =
608 {
609 /* loop: */
610 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
611 0xEA02, 0x0203, /* and r2, r2, r3 */
612 0x3901, /* subs r1, r1, #1 */
613 0xD1F9, /* bne loop */
614 /* end: */
615 0xE7FE, /* b end */
616 };
617
618 /* make sure we have a working area */
619 if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
620 {
621 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
622 }
623
624 /* convert flash writing code into a buffer in target endianness */
625 for (i = 0; i < (sizeof(erase_check_code)/sizeof(u16)); i++)
626 target_write_u16(target, erase_check_algorithm->address + i*sizeof(u16), erase_check_code[i]);
627
628 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
629 armv7m_info.core_mode = ARMV7M_MODE_ANY;
630
631 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
632 buf_set_u32(reg_params[0].value, 0, 32, address);
633
634 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
635 buf_set_u32(reg_params[1].value, 0, 32, count);
636
637 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
638 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
639
640 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
641 erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
642 {
643 destroy_reg_param(&reg_params[0]);
644 destroy_reg_param(&reg_params[1]);
645 destroy_reg_param(&reg_params[2]);
646 target_free_working_area(target, erase_check_algorithm);
647 return 0;
648 }
649
650 *blank = buf_get_u32(reg_params[2].value, 0, 32);
651
652 destroy_reg_param(&reg_params[0]);
653 destroy_reg_param(&reg_params[1]);
654 destroy_reg_param(&reg_params[2]);
655
656 target_free_working_area(target, erase_check_algorithm);
657
658 return ERROR_OK;
659 }
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