1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
32 ***************************************************************************/
38 #include "breakpoints.h"
40 #include "algorithm.h"
44 #define _DEBUG_INSTRUCTION_EXECUTION_
47 static const char * const armv7m_exception_strings
[] = {
48 "", "Reset", "NMI", "HardFault",
49 "MemManage", "BusFault", "UsageFault", "RESERVED",
50 "RESERVED", "RESERVED", "RESERVED", "SVCall",
51 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
54 /* PSP is used in some thread modes */
55 const int armv7m_psp_reg_map
[ARMV7M_NUM_CORE_REGS
] = {
56 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
57 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
58 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
59 ARMV7M_R12
, ARMV7M_PSP
, ARMV7M_R14
, ARMV7M_PC
,
63 /* MSP is used in handler and some thread modes */
64 const int armv7m_msp_reg_map
[ARMV7M_NUM_CORE_REGS
] = {
65 ARMV7M_R0
, ARMV7M_R1
, ARMV7M_R2
, ARMV7M_R3
,
66 ARMV7M_R4
, ARMV7M_R5
, ARMV7M_R6
, ARMV7M_R7
,
67 ARMV7M_R8
, ARMV7M_R9
, ARMV7M_R10
, ARMV7M_R11
,
68 ARMV7M_R12
, ARMV7M_MSP
, ARMV7M_R14
, ARMV7M_PC
,
73 * These registers are not memory-mapped. The ARMv7-M profile includes
74 * memory mapped registers too, such as for the NVIC (interrupt controller)
75 * and SysTick (timer) modules; those can mostly be treated as peripherals.
77 * The ARMv6-M profile is almost identical in this respect, except that it
78 * doesn't include basepri or faultmask registers.
88 { ARMV7M_R0
, "r0", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
89 { ARMV7M_R1
, "r1", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
90 { ARMV7M_R2
, "r2", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
91 { ARMV7M_R3
, "r3", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
92 { ARMV7M_R4
, "r4", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
93 { ARMV7M_R5
, "r5", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
94 { ARMV7M_R6
, "r6", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
95 { ARMV7M_R7
, "r7", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
96 { ARMV7M_R8
, "r8", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
97 { ARMV7M_R9
, "r9", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
98 { ARMV7M_R10
, "r10", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
99 { ARMV7M_R11
, "r11", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
100 { ARMV7M_R12
, "r12", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
101 { ARMV7M_R13
, "sp", 32, REG_TYPE_DATA_PTR
, "general", "org.gnu.gdb.arm.m-profile" },
102 { ARMV7M_R14
, "lr", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
103 { ARMV7M_PC
, "pc", 32, REG_TYPE_CODE_PTR
, "general", "org.gnu.gdb.arm.m-profile" },
104 { ARMV7M_xPSR
, "xPSR", 32, REG_TYPE_INT
, "general", "org.gnu.gdb.arm.m-profile" },
106 { ARMV7M_MSP
, "msp", 32, REG_TYPE_DATA_PTR
, "system", "org.gnu.gdb.arm.m-system" },
107 { ARMV7M_PSP
, "psp", 32, REG_TYPE_DATA_PTR
, "system", "org.gnu.gdb.arm.m-system" },
109 { ARMV7M_PRIMASK
, "primask", 1, REG_TYPE_INT8
, "system", "org.gnu.gdb.arm.m-system" },
110 { ARMV7M_BASEPRI
, "basepri", 8, REG_TYPE_INT8
, "system", "org.gnu.gdb.arm.m-system" },
111 { ARMV7M_FAULTMASK
, "faultmask", 1, REG_TYPE_INT8
, "system", "org.gnu.gdb.arm.m-system" },
112 { ARMV7M_CONTROL
, "control", 2, REG_TYPE_INT8
, "system", "org.gnu.gdb.arm.m-system" },
114 { ARMV7M_D0
, "d0", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
115 { ARMV7M_D1
, "d1", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
116 { ARMV7M_D2
, "d2", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
117 { ARMV7M_D3
, "d3", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
118 { ARMV7M_D4
, "d4", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
119 { ARMV7M_D5
, "d5", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
120 { ARMV7M_D6
, "d6", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
121 { ARMV7M_D7
, "d7", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
122 { ARMV7M_D8
, "d8", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
123 { ARMV7M_D9
, "d9", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
124 { ARMV7M_D10
, "d10", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
125 { ARMV7M_D11
, "d11", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
126 { ARMV7M_D12
, "d12", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
127 { ARMV7M_D13
, "d13", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
128 { ARMV7M_D14
, "d14", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
129 { ARMV7M_D15
, "d15", 64, REG_TYPE_IEEE_DOUBLE
, "float", "org.gnu.gdb.arm.vfp" },
131 { ARMV7M_FPSCR
, "fpscr", 32, REG_TYPE_INT
, "float", "org.gnu.gdb.arm.vfp" },
134 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
137 * Restores target context using the cache of core registers set up
138 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
140 int armv7m_restore_context(struct target
*target
)
143 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
144 struct reg_cache
*cache
= armv7m
->arm
.core_cache
;
148 if (armv7m
->pre_restore_context
)
149 armv7m
->pre_restore_context(target
);
151 for (i
= cache
->num_regs
- 1; i
>= 0; i
--) {
152 if (cache
->reg_list
[i
].dirty
) {
153 armv7m
->arm
.write_core_reg(target
, &cache
->reg_list
[i
], i
,
154 ARM_MODE_ANY
, cache
->reg_list
[i
].value
);
161 /* Core state functions */
164 * Maps ISR number (from xPSR) to name.
165 * Note that while names and meanings for the first sixteen are standardized
166 * (with zero not a true exception), external interrupts are only numbered.
167 * They are assigned by vendors, which generally assign different numbers to
168 * peripherals (such as UART0 or a USB peripheral controller).
170 const char *armv7m_exception_string(int number
)
172 static char enamebuf
[32];
174 if ((number
< 0) | (number
> 511))
175 return "Invalid exception";
177 return armv7m_exception_strings
[number
];
178 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
182 static int armv7m_get_core_reg(struct reg
*reg
)
185 struct arm_reg
*armv7m_reg
= reg
->arch_info
;
186 struct target
*target
= armv7m_reg
->target
;
187 struct arm
*arm
= target_to_arm(target
);
189 if (target
->state
!= TARGET_HALTED
)
190 return ERROR_TARGET_NOT_HALTED
;
192 retval
= arm
->read_core_reg(target
, reg
, armv7m_reg
->num
, arm
->core_mode
);
197 static int armv7m_set_core_reg(struct reg
*reg
, uint8_t *buf
)
199 struct arm_reg
*armv7m_reg
= reg
->arch_info
;
200 struct target
*target
= armv7m_reg
->target
;
202 if (target
->state
!= TARGET_HALTED
)
203 return ERROR_TARGET_NOT_HALTED
;
205 buf_cpy(buf
, reg
->value
, reg
->size
);
212 static int armv7m_read_core_reg(struct target
*target
, struct reg
*r
,
213 int num
, enum arm_mode mode
)
217 struct arm_reg
*armv7m_core_reg
;
218 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
220 assert(num
< (int)armv7m
->arm
.core_cache
->num_regs
);
222 armv7m_core_reg
= armv7m
->arm
.core_cache
->reg_list
[num
].arch_info
;
224 if ((armv7m_core_reg
->num
>= ARMV7M_D0
) && (armv7m_core_reg
->num
<= ARMV7M_D15
)) {
225 /* map D0..D15 to S0..S31 */
226 size_t regidx
= ARMV7M_S0
+ 2 * (armv7m_core_reg
->num
- ARMV7M_D0
);
227 retval
= armv7m
->load_core_reg_u32(target
, regidx
, ®_value
);
228 if (retval
!= ERROR_OK
)
230 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[num
].value
,
232 retval
= armv7m
->load_core_reg_u32(target
, regidx
+ 1, ®_value
);
233 if (retval
!= ERROR_OK
)
235 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[num
].value
+ 4,
238 retval
= armv7m
->load_core_reg_u32(target
,
239 armv7m_core_reg
->num
, ®_value
);
240 if (retval
!= ERROR_OK
)
242 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
245 armv7m
->arm
.core_cache
->reg_list
[num
].valid
= 1;
246 armv7m
->arm
.core_cache
->reg_list
[num
].dirty
= 0;
251 static int armv7m_write_core_reg(struct target
*target
, struct reg
*r
,
252 int num
, enum arm_mode mode
, uint8_t *value
)
255 struct arm_reg
*armv7m_core_reg
;
256 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
258 assert(num
< (int)armv7m
->arm
.core_cache
->num_regs
);
260 armv7m_core_reg
= armv7m
->arm
.core_cache
->reg_list
[num
].arch_info
;
262 if ((armv7m_core_reg
->num
>= ARMV7M_D0
) && (armv7m_core_reg
->num
<= ARMV7M_D15
)) {
263 /* map D0..D15 to S0..S31 */
264 size_t regidx
= ARMV7M_S0
+ 2 * (armv7m_core_reg
->num
- ARMV7M_D0
);
266 uint32_t t
= buf_get_u32(value
, 0, 32);
267 retval
= armv7m
->store_core_reg_u32(target
, regidx
, t
);
268 if (retval
!= ERROR_OK
)
271 t
= buf_get_u32(value
+ 4, 0, 32);
272 retval
= armv7m
->store_core_reg_u32(target
, regidx
+ 1, t
);
273 if (retval
!= ERROR_OK
)
276 uint32_t t
= buf_get_u32(value
, 0, 32);
278 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, t
);
279 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->num
, t
);
280 if (retval
!= ERROR_OK
)
284 armv7m
->arm
.core_cache
->reg_list
[num
].valid
= 1;
285 armv7m
->arm
.core_cache
->reg_list
[num
].dirty
= 0;
290 LOG_ERROR("Error setting register");
291 armv7m
->arm
.core_cache
->reg_list
[num
].dirty
= armv7m
->arm
.core_cache
->reg_list
[num
].valid
;
292 return ERROR_JTAG_DEVICE_ERROR
;
296 * Returns generic ARM userspace registers to GDB.
298 int armv7m_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
299 int *reg_list_size
, enum target_register_class reg_class
)
301 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
304 if (reg_class
== REG_CLASS_ALL
)
305 *reg_list_size
= armv7m
->arm
.core_cache
->num_regs
;
307 *reg_list_size
= ARMV7M_NUM_CORE_REGS
;
309 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
310 if (*reg_list
== NULL
)
313 for (i
= 0; i
< *reg_list_size
; i
++)
314 (*reg_list
)[i
] = &armv7m
->arm
.core_cache
->reg_list
[i
];
319 /** Runs a Thumb algorithm in the target. */
320 int armv7m_run_algorithm(struct target
*target
,
321 int num_mem_params
, struct mem_param
*mem_params
,
322 int num_reg_params
, struct reg_param
*reg_params
,
323 uint32_t entry_point
, uint32_t exit_point
,
324 int timeout_ms
, void *arch_info
)
328 retval
= armv7m_start_algorithm(target
,
329 num_mem_params
, mem_params
,
330 num_reg_params
, reg_params
,
331 entry_point
, exit_point
,
334 if (retval
== ERROR_OK
)
335 retval
= armv7m_wait_algorithm(target
,
336 num_mem_params
, mem_params
,
337 num_reg_params
, reg_params
,
338 exit_point
, timeout_ms
,
344 /** Starts a Thumb algorithm in the target. */
345 int armv7m_start_algorithm(struct target
*target
,
346 int num_mem_params
, struct mem_param
*mem_params
,
347 int num_reg_params
, struct reg_param
*reg_params
,
348 uint32_t entry_point
, uint32_t exit_point
,
351 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
352 struct armv7m_algorithm
*armv7m_algorithm_info
= arch_info
;
353 enum arm_mode core_mode
= armv7m
->arm
.core_mode
;
354 int retval
= ERROR_OK
;
356 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
357 * at the exit point */
359 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
) {
360 LOG_ERROR("current target isn't an ARMV7M target");
361 return ERROR_TARGET_INVALID
;
364 if (target
->state
!= TARGET_HALTED
) {
365 LOG_WARNING("target not halted");
366 return ERROR_TARGET_NOT_HALTED
;
369 /* refresh core register cache
370 * Not needed if core register cache is always consistent with target process state */
371 for (unsigned i
= 0; i
< armv7m
->arm
.core_cache
->num_regs
; i
++) {
373 armv7m_algorithm_info
->context
[i
] = buf_get_u32(
374 armv7m
->arm
.core_cache
->reg_list
[i
].value
,
379 for (int i
= 0; i
< num_mem_params
; i
++) {
380 /* TODO: Write only out params */
381 retval
= target_write_buffer(target
, mem_params
[i
].address
,
383 mem_params
[i
].value
);
384 if (retval
!= ERROR_OK
)
388 for (int i
= 0; i
< num_reg_params
; i
++) {
390 register_get_by_name(armv7m
->arm
.core_cache
, reg_params
[i
].reg_name
, 0);
391 /* uint32_t regvalue; */
394 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
395 return ERROR_COMMAND_SYNTAX_ERROR
;
398 if (reg
->size
!= reg_params
[i
].size
) {
399 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
400 reg_params
[i
].reg_name
);
401 return ERROR_COMMAND_SYNTAX_ERROR
;
404 /* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
405 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
408 if (armv7m_algorithm_info
->core_mode
!= ARM_MODE_ANY
&&
409 armv7m_algorithm_info
->core_mode
!= core_mode
) {
411 /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
412 if (armv7m_algorithm_info
->core_mode
== ARM_MODE_HANDLER
) {
413 armv7m_algorithm_info
->core_mode
= ARM_MODE_THREAD
;
414 LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
417 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
418 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].value
,
419 0, 1, armv7m_algorithm_info
->core_mode
);
420 armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
421 armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
424 /* save previous core mode */
425 armv7m_algorithm_info
->core_mode
= core_mode
;
427 retval
= target_resume(target
, 0, entry_point
, 1, 1);
432 /** Waits for an algorithm in the target. */
433 int armv7m_wait_algorithm(struct target
*target
,
434 int num_mem_params
, struct mem_param
*mem_params
,
435 int num_reg_params
, struct reg_param
*reg_params
,
436 uint32_t exit_point
, int timeout_ms
,
439 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
440 struct armv7m_algorithm
*armv7m_algorithm_info
= arch_info
;
441 int retval
= ERROR_OK
;
444 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
445 * at the exit point */
447 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
) {
448 LOG_ERROR("current target isn't an ARMV7M target");
449 return ERROR_TARGET_INVALID
;
452 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
453 /* If the target fails to halt due to the breakpoint, force a halt */
454 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
) {
455 retval
= target_halt(target
);
456 if (retval
!= ERROR_OK
)
458 retval
= target_wait_state(target
, TARGET_HALTED
, 500);
459 if (retval
!= ERROR_OK
)
461 return ERROR_TARGET_TIMEOUT
;
464 armv7m
->load_core_reg_u32(target
, 15, &pc
);
465 if (exit_point
&& (pc
!= exit_point
)) {
466 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32
", expected 0x%" PRIx32
,
469 return ERROR_TARGET_TIMEOUT
;
472 /* Read memory values to mem_params[] */
473 for (int i
= 0; i
< num_mem_params
; i
++) {
474 if (mem_params
[i
].direction
!= PARAM_OUT
) {
475 retval
= target_read_buffer(target
, mem_params
[i
].address
,
477 mem_params
[i
].value
);
478 if (retval
!= ERROR_OK
)
483 /* Copy core register values to reg_params[] */
484 for (int i
= 0; i
< num_reg_params
; i
++) {
485 if (reg_params
[i
].direction
!= PARAM_OUT
) {
486 struct reg
*reg
= register_get_by_name(armv7m
->arm
.core_cache
,
487 reg_params
[i
].reg_name
,
491 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
492 return ERROR_COMMAND_SYNTAX_ERROR
;
495 if (reg
->size
!= reg_params
[i
].size
) {
497 "BUG: register '%s' size doesn't match reg_params[i].size",
498 reg_params
[i
].reg_name
);
499 return ERROR_COMMAND_SYNTAX_ERROR
;
502 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
506 for (int i
= armv7m
->arm
.core_cache
->num_regs
- 1; i
>= 0; i
--) {
508 regvalue
= buf_get_u32(armv7m
->arm
.core_cache
->reg_list
[i
].value
, 0, 32);
509 if (regvalue
!= armv7m_algorithm_info
->context
[i
]) {
510 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
511 armv7m
->arm
.core_cache
->reg_list
[i
].name
,
512 armv7m_algorithm_info
->context
[i
]);
513 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[i
].value
,
514 0, 32, armv7m_algorithm_info
->context
[i
]);
515 armv7m
->arm
.core_cache
->reg_list
[i
].valid
= 1;
516 armv7m
->arm
.core_cache
->reg_list
[i
].dirty
= 1;
520 /* restore previous core mode */
521 if (armv7m_algorithm_info
->core_mode
!= armv7m
->arm
.core_mode
) {
522 LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
523 buf_set_u32(armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].value
,
524 0, 1, armv7m_algorithm_info
->core_mode
);
525 armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
526 armv7m
->arm
.core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
529 armv7m
->arm
.core_mode
= armv7m_algorithm_info
->core_mode
;
534 /** Logs summary of ARMv7-M state for a halted target. */
535 int armv7m_arch_state(struct target
*target
)
537 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
538 struct arm
*arm
= &armv7m
->arm
;
541 ctrl
= buf_get_u32(arm
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 32);
542 sp
= buf_get_u32(arm
->core_cache
->reg_list
[ARMV7M_R13
].value
, 0, 32);
544 LOG_USER("target halted due to %s, current mode: %s %s\n"
545 "xPSR: %#8.8" PRIx32
" pc: %#8.8" PRIx32
" %csp: %#8.8" PRIx32
"%s",
546 debug_reason_name(target
),
547 arm_mode_name(arm
->core_mode
),
548 armv7m_exception_string(armv7m
->exception_number
),
549 buf_get_u32(arm
->cpsr
->value
, 0, 32),
550 buf_get_u32(arm
->pc
->value
, 0, 32),
551 (ctrl
& 0x02) ? 'p' : 'm',
553 arm
->is_semihosting
? ", semihosting" : "");
558 static const struct reg_arch_type armv7m_reg_type
= {
559 .get
= armv7m_get_core_reg
,
560 .set
= armv7m_set_core_reg
,
563 /** Builds cache of architecturally defined registers. */
564 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
)
566 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
567 struct arm
*arm
= &armv7m
->arm
;
568 int num_regs
= ARMV7M_NUM_REGS
;
569 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
570 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
571 struct reg
*reg_list
= calloc(num_regs
, sizeof(struct reg
));
572 struct arm_reg
*arch_info
= calloc(num_regs
, sizeof(struct arm_reg
));
573 struct reg_feature
*feature
;
576 /* Build the process context cache */
577 cache
->name
= "arm v7m registers";
579 cache
->reg_list
= reg_list
;
580 cache
->num_regs
= num_regs
;
583 for (i
= 0; i
< num_regs
; i
++) {
584 arch_info
[i
].num
= armv7m_regs
[i
].id
;
585 arch_info
[i
].target
= target
;
586 arch_info
[i
].arm
= arm
;
588 reg_list
[i
].name
= armv7m_regs
[i
].name
;
589 reg_list
[i
].size
= armv7m_regs
[i
].bits
;
590 size_t storage_size
= DIV_ROUND_UP(armv7m_regs
[i
].bits
, 8);
591 if (storage_size
< 4)
593 reg_list
[i
].value
= calloc(1, storage_size
);
594 reg_list
[i
].dirty
= 0;
595 reg_list
[i
].valid
= 0;
596 reg_list
[i
].type
= &armv7m_reg_type
;
597 reg_list
[i
].arch_info
= &arch_info
[i
];
599 reg_list
[i
].group
= armv7m_regs
[i
].group
;
600 reg_list
[i
].number
= i
;
601 reg_list
[i
].exist
= true;
602 reg_list
[i
].caller_save
= true; /* gdb defaults to true */
604 feature
= calloc(1, sizeof(struct reg_feature
));
606 feature
->name
= armv7m_regs
[i
].feature
;
607 reg_list
[i
].feature
= feature
;
609 LOG_ERROR("unable to allocate feature list");
611 reg_list
[i
].reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
612 if (reg_list
[i
].reg_data_type
)
613 reg_list
[i
].reg_data_type
->type
= armv7m_regs
[i
].type
;
615 LOG_ERROR("unable to allocate reg type list");
618 arm
->cpsr
= reg_list
+ ARMV7M_xPSR
;
619 arm
->pc
= reg_list
+ ARMV7M_PC
;
620 arm
->core_cache
= cache
;
625 void armv7m_free_reg_cache(struct target
*target
)
627 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
628 struct arm
*arm
= &armv7m
->arm
;
629 struct reg_cache
*cache
;
633 cache
= arm
->core_cache
;
638 for (i
= 0; i
< cache
->num_regs
; i
++) {
639 reg
= &cache
->reg_list
[i
];
642 free(reg
->reg_data_type
);
646 free(cache
->reg_list
[0].arch_info
);
647 free(cache
->reg_list
);
650 arm
->core_cache
= NULL
;
653 static int armv7m_setup_semihosting(struct target
*target
, int enable
)
655 /* nothing todo for armv7m */
659 /** Sets up target as a generic ARMv7-M core */
660 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
)
662 struct arm
*arm
= &armv7m
->arm
;
664 armv7m
->common_magic
= ARMV7M_COMMON_MAGIC
;
665 armv7m
->fp_feature
= FP_NONE
;
666 armv7m
->trace_config
.trace_bus_id
= 1;
667 /* Enable stimulus port #0 by default */
668 armv7m
->trace_config
.itm_ter
[0] = 1;
670 arm
->core_type
= ARM_MODE_THREAD
;
671 arm
->arch_info
= armv7m
;
672 arm
->setup_semihosting
= armv7m_setup_semihosting
;
674 arm
->read_core_reg
= armv7m_read_core_reg
;
675 arm
->write_core_reg
= armv7m_write_core_reg
;
677 return arm_init_arch_info(target
, arm
);
680 /** Generates a CRC32 checksum of a memory region. */
681 int armv7m_checksum_memory(struct target
*target
,
682 uint32_t address
, uint32_t count
, uint32_t *checksum
)
684 struct working_area
*crc_algorithm
;
685 struct armv7m_algorithm armv7m_info
;
686 struct reg_param reg_params
[2];
689 static const uint8_t cortex_m_crc_code
[] = {
690 #include "../../contrib/loaders/checksum/armv7m_crc.inc"
693 retval
= target_alloc_working_area(target
, sizeof(cortex_m_crc_code
), &crc_algorithm
);
694 if (retval
!= ERROR_OK
)
697 retval
= target_write_buffer(target
, crc_algorithm
->address
,
698 sizeof(cortex_m_crc_code
), (uint8_t *)cortex_m_crc_code
);
699 if (retval
!= ERROR_OK
)
702 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
703 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
705 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
706 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
708 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
709 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
711 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
713 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
, crc_algorithm
->address
,
714 crc_algorithm
->address
+ (sizeof(cortex_m_crc_code
) - 6),
715 timeout
, &armv7m_info
);
717 if (retval
== ERROR_OK
)
718 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
720 LOG_ERROR("error executing cortex_m crc algorithm");
722 destroy_reg_param(®_params
[0]);
723 destroy_reg_param(®_params
[1]);
726 target_free_working_area(target
, crc_algorithm
);
731 /** Checks whether a memory region is zeroed. */
732 int armv7m_blank_check_memory(struct target
*target
,
733 uint32_t address
, uint32_t count
, uint32_t *blank
)
735 struct working_area
*erase_check_algorithm
;
736 struct reg_param reg_params
[3];
737 struct armv7m_algorithm armv7m_info
;
740 static const uint8_t erase_check_code
[] = {
741 #include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
744 /* make sure we have a working area */
745 if (target_alloc_working_area(target
, sizeof(erase_check_code
),
746 &erase_check_algorithm
) != ERROR_OK
)
747 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
749 retval
= target_write_buffer(target
, erase_check_algorithm
->address
,
750 sizeof(erase_check_code
), (uint8_t *)erase_check_code
);
751 if (retval
!= ERROR_OK
)
754 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
755 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
757 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
758 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
760 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
761 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
763 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
764 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
766 retval
= target_run_algorithm(target
,
771 erase_check_algorithm
->address
,
772 erase_check_algorithm
->address
+ (sizeof(erase_check_code
) - 2),
776 if (retval
== ERROR_OK
)
777 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
779 destroy_reg_param(®_params
[0]);
780 destroy_reg_param(®_params
[1]);
781 destroy_reg_param(®_params
[2]);
784 target_free_working_area(target
, erase_check_algorithm
);
789 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
)
791 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
792 struct reg
*r
= armv7m
->arm
.pc
;
796 /* if we halted last time due to a bkpt instruction
797 * then we have to manually step over it, otherwise
798 * the core will break again */
800 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
) {
802 uint32_t pc
= buf_get_u32(r
->value
, 0, 32);
805 if (target_read_u16(target
, pc
, &op
) == ERROR_OK
) {
806 if ((op
& 0xFF00) == 0xBE00) {
807 pc
= buf_get_u32(r
->value
, 0, 32) + 2;
808 buf_set_u32(r
->value
, 0, 32, pc
);
812 LOG_DEBUG("Skipping over BKPT instruction");
818 *inst_found
= result
;
823 const struct command_registration armv7m_command_handlers
[] = {
825 .chain
= arm_command_handlers
,
828 .chain
= dap_command_handlers
,
830 COMMAND_REGISTRATION_DONE
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