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Fix usage of timeval_ms()
[openocd.git] / src / target / armv7a_cache_l2x.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include "jtag/interface.h"
24 #include "arm.h"
25 #include "armv7a.h"
26 #include "armv7a_cache.h"
27 #include <helper/time_support.h>
28 #include "target.h"
29 #include "target_type.h"
30
31 static int arm7a_l2x_sanity_check(struct target *target)
32 {
33 struct armv7a_common *armv7a = target_to_armv7a(target);
34 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
35 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
36
37 if (target->state != TARGET_HALTED) {
38 LOG_ERROR("%s: target not halted", __func__);
39 return ERROR_TARGET_NOT_HALTED;
40 }
41
42 if (!l2x_cache || !l2x_cache->base) {
43 LOG_DEBUG("l2x is not configured!");
44 return ERROR_FAIL;
45 }
46
47 return ERROR_OK;
48 }
49 /*
50 * clean and invalidate complete l2x cache
51 */
52 int arm7a_l2x_flush_all_data(struct target *target)
53 {
54 struct armv7a_common *armv7a = target_to_armv7a(target);
55 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
56 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
57 uint32_t l2_way_val;
58 int retval;
59
60 retval = arm7a_l2x_sanity_check(target);
61 if (retval)
62 return retval;
63
64 l2_way_val = (1 << l2x_cache->way) - 1;
65
66 return target_write_phys_memory(target,
67 l2x_cache->base + L2X0_CLEAN_INV_WAY,
68 4, 1, (uint8_t *)&l2_way_val);
69 }
70
71 int armv7a_l2x_cache_flush_virt(struct target *target, uint32_t virt,
72 uint32_t size)
73 {
74 struct armv7a_common *armv7a = target_to_armv7a(target);
75 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
76 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
77 /* FIXME: different controllers have different linelen? */
78 uint32_t i, linelen = 32;
79 int retval;
80
81 retval = arm7a_l2x_sanity_check(target);
82 if (retval)
83 return retval;
84
85 for (i = 0; i < size; i += linelen) {
86 uint32_t pa, offs = virt + i;
87
88 /* FIXME: use less verbose virt2phys? */
89 retval = target->type->virt2phys(target, offs, &pa);
90 if (retval != ERROR_OK)
91 goto done;
92
93 retval = target_write_phys_memory(target,
94 l2x_cache->base + L2X0_CLEAN_INV_LINE_PA,
95 4, 1, (uint8_t *)&pa);
96 if (retval != ERROR_OK)
97 goto done;
98 }
99 return retval;
100
101 done:
102 LOG_ERROR("d-cache invalidate failed");
103
104 return retval;
105 }
106
107 static int armv7a_l2x_cache_inval_virt(struct target *target, uint32_t virt,
108 uint32_t size)
109 {
110 struct armv7a_common *armv7a = target_to_armv7a(target);
111 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
112 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
113 /* FIXME: different controllers have different linelen */
114 uint32_t i, linelen = 32;
115 int retval;
116
117 retval = arm7a_l2x_sanity_check(target);
118 if (retval)
119 return retval;
120
121 for (i = 0; i < size; i += linelen) {
122 uint32_t pa, offs = virt + i;
123
124 /* FIXME: use less verbose virt2phys? */
125 retval = target->type->virt2phys(target, offs, &pa);
126 if (retval != ERROR_OK)
127 goto done;
128
129 retval = target_write_phys_memory(target,
130 l2x_cache->base + L2X0_INV_LINE_PA,
131 4, 1, (uint8_t *)&pa);
132 if (retval != ERROR_OK)
133 goto done;
134 }
135 return retval;
136
137 done:
138 LOG_ERROR("d-cache invalidate failed");
139
140 return retval;
141 }
142
143 static int armv7a_l2x_cache_clean_virt(struct target *target, uint32_t virt,
144 unsigned int size)
145 {
146 struct armv7a_common *armv7a = target_to_armv7a(target);
147 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
148 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
149 /* FIXME: different controllers have different linelen */
150 uint32_t i, linelen = 32;
151 int retval;
152
153 retval = arm7a_l2x_sanity_check(target);
154 if (retval)
155 return retval;
156
157 for (i = 0; i < size; i += linelen) {
158 uint32_t pa, offs = virt + i;
159
160 /* FIXME: use less verbose virt2phys? */
161 retval = target->type->virt2phys(target, offs, &pa);
162 if (retval != ERROR_OK)
163 goto done;
164
165 retval = target_write_phys_memory(target,
166 l2x_cache->base + L2X0_CLEAN_LINE_PA,
167 4, 1, (uint8_t *)&pa);
168 if (retval != ERROR_OK)
169 goto done;
170 }
171 return retval;
172
173 done:
174 LOG_ERROR("d-cache invalidate failed");
175
176 return retval;
177 }
178
179 static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
180 struct armv7a_cache_common *armv7a_cache)
181 {
182 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
183 (armv7a_cache->outer_cache);
184
185 if (armv7a_cache->info == -1) {
186 command_print(cmd_ctx, "cache not yet identified");
187 return ERROR_OK;
188 }
189
190 command_print(cmd_ctx,
191 "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
192 l2x_cache->base, l2x_cache->way);
193
194 return ERROR_OK;
195 }
196
197 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
198 {
199 struct armv7a_l2x_cache *l2x_cache;
200 struct target_list *head = target->head;
201 struct target *curr;
202
203 struct armv7a_common *armv7a = target_to_armv7a(target);
204 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
205 LOG_ERROR("L2 cache was already initialised\n");
206 return ERROR_FAIL;
207 }
208
209 l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
210 l2x_cache->base = base;
211 l2x_cache->way = way;
212 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
213
214 /* initialize all targets in this cluster (smp target)
215 * l2 cache must be configured after smp declaration */
216 while (head != (struct target_list *)NULL) {
217 curr = head->target;
218 if (curr != target) {
219 armv7a = target_to_armv7a(curr);
220 if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
221 LOG_ERROR("smp target : cache l2 already initialized\n");
222 return ERROR_FAIL;
223 }
224 armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
225 }
226 head = head->next;
227 }
228 return ERROR_OK;
229 }
230
231 COMMAND_HANDLER(arm7a_l2x_cache_info_command)
232 {
233 struct target *target = get_current_target(CMD_CTX);
234 struct armv7a_common *armv7a = target_to_armv7a(target);
235 int retval;
236
237 retval = arm7a_l2x_sanity_check(target);
238 if (retval)
239 return retval;
240
241 return arm7a_handle_l2x_cache_info_command(CMD_CTX,
242 &armv7a->armv7a_mmu.armv7a_cache);
243 }
244
245 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
246 {
247 struct target *target = get_current_target(CMD_CTX);
248
249 return arm7a_l2x_flush_all_data(target);
250 }
251
252 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
253 {
254 struct target *target = get_current_target(CMD_CTX);
255 uint32_t virt, size;
256
257 if (CMD_ARGC == 0 || CMD_ARGC > 2)
258 return ERROR_COMMAND_SYNTAX_ERROR;
259
260 if (CMD_ARGC == 2)
261 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
262 else
263 size = 1;
264
265 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
266
267 return armv7a_l2x_cache_flush_virt(target, virt, size);
268 }
269
270 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
271 {
272 struct target *target = get_current_target(CMD_CTX);
273 uint32_t virt, size;
274
275 if (CMD_ARGC == 0 || CMD_ARGC > 2)
276 return ERROR_COMMAND_SYNTAX_ERROR;
277
278 if (CMD_ARGC == 2)
279 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
280 else
281 size = 1;
282
283 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
284
285 return armv7a_l2x_cache_inval_virt(target, virt, size);
286 }
287
288 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
289 {
290 struct target *target = get_current_target(CMD_CTX);
291 uint32_t virt, size;
292
293 if (CMD_ARGC == 0 || CMD_ARGC > 2)
294 return ERROR_COMMAND_SYNTAX_ERROR;
295
296 if (CMD_ARGC == 2)
297 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
298 else
299 size = 1;
300
301 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], virt);
302
303 return armv7a_l2x_cache_clean_virt(target, virt, size);
304 }
305
306 /* FIXME: should we configure way size? or controller type? */
307 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
308 {
309 struct target *target = get_current_target(CMD_CTX);
310 uint32_t base, way;
311
312 if (CMD_ARGC != 2)
313 return ERROR_COMMAND_SYNTAX_ERROR;
314
315 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
316 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
317 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
318
319 /* AP address is in bits 31:24 of DP_SELECT */
320 return armv7a_l2x_cache_init(target, base, way);
321 }
322
323 static const struct command_registration arm7a_l2x_cache_commands[] = {
324 {
325 .name = "conf",
326 .handler = armv7a_l2x_cache_conf_cmd,
327 .mode = COMMAND_ANY,
328 .help = "configure l2x cache ",
329 .usage = "<base_addr> <number_of_way>",
330 },
331 {
332 .name = "info",
333 .handler = arm7a_l2x_cache_info_command,
334 .mode = COMMAND_ANY,
335 .help = "print cache realted information",
336 .usage = "",
337 },
338 {
339 .name = "flush_all",
340 .handler = arm7a_l2x_cache_flush_all_command,
341 .mode = COMMAND_ANY,
342 .help = "flush complete l2x cache",
343 .usage = "",
344 },
345 {
346 .name = "flush",
347 .handler = arm7a_l2x_cache_flush_virt_cmd,
348 .mode = COMMAND_ANY,
349 .help = "flush (clean and invalidate) l2x cache by virtual address offset and range size",
350 .usage = "<virt_addr> [size]",
351 },
352 {
353 .name = "inval",
354 .handler = arm7a_l2x_cache_inval_virt_cmd,
355 .mode = COMMAND_ANY,
356 .help = "invalidate l2x cache by virtual address offset and range size",
357 .usage = "<virt_addr> [size]",
358 },
359 {
360 .name = "clean",
361 .handler = arm7a_l2x_cache_clean_virt_cmd,
362 .mode = COMMAND_ANY,
363 .help = "clean l2x cache by virtual address address offset and range size",
364 .usage = "<virt_addr> [size]",
365 },
366 COMMAND_REGISTRATION_DONE
367 };
368
369 const struct command_registration arm7a_l2x_cache_command_handler[] = {
370 {
371 .name = "l2x",
372 .mode = COMMAND_ANY,
373 .help = "l2x cache command group",
374 .usage = "",
375 .chain = arm7a_l2x_cache_commands,
376 },
377 COMMAND_REGISTRATION_DONE
378 };
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