ARM: simplify ARMv7-A register handling
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "arm_adi_v5.h"
23 #include "armv4_5.h"
24 #include "armv4_5_mmu.h"
25 #include "armv4_5_cache.h"
26
27 typedef enum armv7a_mode
28 {
29 ARMV7A_MODE_USR = 16,
30 ARMV7A_MODE_FIQ = 17,
31 ARMV7A_MODE_IRQ = 18,
32 ARMV7A_MODE_SVC = 19,
33 ARMV7A_MODE_ABT = 23,
34 ARMV7A_MODE_UND = 27,
35 ARMV7A_MODE_SYS = 31,
36 ARMV7A_MODE_MON = 22,
37 ARMV7A_MODE_ANY = -1
38 } armv7a_t;
39
40 typedef enum armv7a_state
41 {
42 ARMV7A_STATE_ARM,
43 ARMV7A_STATE_THUMB,
44 ARMV7A_STATE_JAZELLE,
45 ARMV7A_STATE_THUMBEE,
46 } armv7a_state_t;
47
48 enum
49 {
50 ARM_PC = 15,
51 ARM_CPSR = 16
52 }
53 ;
54 /* offsets into armv4_5 core register cache */
55 enum
56 {
57 ARMV7A_CPSR = 31,
58 ARMV7A_SPSR_FIQ = 32,
59 ARMV7A_SPSR_IRQ = 33,
60 ARMV7A_SPSR_SVC = 34,
61 ARMV7A_SPSR_ABT = 35,
62 ARMV7A_SPSR_UND = 36
63 };
64
65 #define ARMV7_COMMON_MAGIC 0x0A450999
66
67 /* VA to PA translation operations opc2 values*/
68 #define V2PCWPR 0
69 #define V2PCWPW 1
70 #define V2PCWUR 2
71 #define V2PCWUW 3
72 #define V2POWPR 4
73 #define V2POWPW 5
74 #define V2POWUR 6
75 #define V2POWUW 7
76
77 struct armv7a_common
78 {
79 int common_magic;
80 struct reg_cache *core_cache;
81 enum armv7a_mode core_mode;
82 enum armv7a_state core_state;
83
84 /* arm adp debug port */
85 struct swjdp_common swjdp_info;
86
87 /* Core Debug Unit */
88 uint32_t debug_base;
89 uint8_t debug_ap;
90 uint8_t memory_ap;
91
92 /* Cache and Memory Management Unit */
93 struct armv4_5_mmu_common armv4_5_mmu;
94 struct arm armv4_5_common;
95
96 int (*read_cp15)(struct target *target,
97 uint32_t op1, uint32_t op2,
98 uint32_t CRn, uint32_t CRm, uint32_t *value);
99 int (*write_cp15)(struct target *target,
100 uint32_t op1, uint32_t op2,
101 uint32_t CRn, uint32_t CRm, uint32_t value);
102
103 int (*examine_debug_reason)(struct target *target);
104 void (*post_debug_entry)(struct target *target);
105
106 void (*pre_restore_context)(struct target *target);
107 void (*post_restore_context)(struct target *target);
108
109 };
110
111 static inline struct armv7a_common *
112 target_to_armv7a(struct target *target)
113 {
114 return container_of(target->arch_info, struct armv7a_common,
115 armv4_5_common);
116 }
117
118 struct armv7a_algorithm
119 {
120 int common_magic;
121
122 enum armv7a_mode core_mode;
123 enum armv7a_state core_state;
124 };
125
126 struct armv7a_core_reg
127 {
128 int num;
129 enum armv7a_mode mode;
130 struct target *target;
131 struct armv7a_common *armv7a_common;
132 };
133
134 int armv7a_arch_state(struct target *target);
135 struct reg_cache *armv7a_build_reg_cache(struct target *target,
136 struct armv7a_common *armv7a_common);
137 int armv7a_register_commands(struct command_context *cmd_ctx);
138 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
139
140 #endif /* ARMV4_5_H */

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