target: no implicit #includes of "register.h"
[openocd.git] / src / target / armv7a.h
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19 #ifndef ARMV7A_H
20 #define ARMV7A_H
21
22 #include "target.h"
23 #include "arm_adi_v5.h"
24 #include "armv4_5.h"
25 #include "armv4_5_mmu.h"
26 #include "armv4_5_cache.h"
27
28 typedef enum armv7a_mode
29 {
30 ARMV7A_MODE_USR = 16,
31 ARMV7A_MODE_FIQ = 17,
32 ARMV7A_MODE_IRQ = 18,
33 ARMV7A_MODE_SVC = 19,
34 ARMV7A_MODE_ABT = 23,
35 ARMV7A_MODE_UND = 27,
36 ARMV7A_MODE_SYS = 31,
37 ARMV7A_MODE_MON = 22,
38 ARMV7A_MODE_ANY = -1
39 } armv7a_t;
40
41 extern char **armv7a_mode_strings;
42
43 typedef enum armv7a_state
44 {
45 ARMV7A_STATE_ARM,
46 ARMV7A_STATE_THUMB,
47 ARMV7A_STATE_JAZELLE,
48 ARMV7A_STATE_THUMBEE,
49 } armv7a_state_t;
50
51 extern char *armv7a_state_strings[];
52
53 extern int armv7a_core_reg_map[8][17];
54
55 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
56 cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
57 #define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
58 cache->reg_list[armv7a_core_reg_map[mode][num]]
59
60 enum
61 {
62 ARM_PC = 15,
63 ARM_CPSR = 16
64 }
65 ;
66 /* offsets into armv4_5 core register cache */
67 enum
68 {
69 ARMV7A_CPSR = 31,
70 ARMV7A_SPSR_FIQ = 32,
71 ARMV7A_SPSR_IRQ = 33,
72 ARMV7A_SPSR_SVC = 34,
73 ARMV7A_SPSR_ABT = 35,
74 ARMV7A_SPSR_UND = 36
75 };
76
77 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
78 #define ARMV7_COMMON_MAGIC 0x0A450999
79
80 /* VA to PA translation operations opc2 values*/
81 #define V2PCWPR 0
82 #define V2PCWPW 1
83 #define V2PCWUR 2
84 #define V2PCWUW 3
85 #define V2POWPR 4
86 #define V2POWPW 5
87 #define V2POWUR 6
88 #define V2POWUW 7
89
90 struct armv7a_common
91 {
92 int common_magic;
93 struct reg_cache *core_cache;
94 enum armv7a_mode core_mode;
95 enum armv7a_state core_state;
96
97 /* arm adp debug port */
98 struct swjdp_common swjdp_info;
99
100 /* Core Debug Unit */
101 uint32_t debug_base;
102 uint8_t debug_ap;
103 uint8_t memory_ap;
104
105 /* Cache and Memory Management Unit */
106 struct armv4_5_mmu_common armv4_5_mmu;
107 struct arm armv4_5_common;
108
109 // int (*full_context)(struct target *target);
110 // int (*read_core_reg)(struct target *target, int num, enum armv7a_mode mode);
111 // int (*write_core_reg)(struct target *target, int num, enum armv7a_mode mode, u32 value);
112 int (*read_cp15)(struct target *target,
113 uint32_t op1, uint32_t op2,
114 uint32_t CRn, uint32_t CRm, uint32_t *value);
115 int (*write_cp15)(struct target *target,
116 uint32_t op1, uint32_t op2,
117 uint32_t CRn, uint32_t CRm, uint32_t value);
118
119 int (*examine_debug_reason)(struct target *target);
120 void (*post_debug_entry)(struct target *target);
121
122 void (*pre_restore_context)(struct target *target);
123 void (*post_restore_context)(struct target *target);
124
125 };
126
127 static inline struct armv7a_common *
128 target_to_armv7a(struct target *target)
129 {
130 return container_of(target->arch_info, struct armv7a_common,
131 armv4_5_common);
132 }
133
134 struct armv7a_algorithm
135 {
136 int common_magic;
137
138 enum armv7a_mode core_mode;
139 enum armv7a_state core_state;
140 };
141
142 struct armv7a_core_reg
143 {
144 int num;
145 enum armv7a_mode mode;
146 struct target *target;
147 struct armv7a_common *armv7a_common;
148 };
149
150 int armv7a_arch_state(struct target *target);
151 struct reg_cache *armv7a_build_reg_cache(struct target *target,
152 struct armv7a_common *armv7a_common);
153 int armv7a_register_commands(struct command_context *cmd_ctx);
154 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
155
156 /* map psr mode bits to linear number */
157 static inline int armv7a_mode_to_number(enum armv7a_mode mode)
158 {
159 switch (mode)
160 {
161 case ARMV7A_MODE_USR: return 0; break;
162 case ARMV7A_MODE_FIQ: return 1; break;
163 case ARMV7A_MODE_IRQ: return 2; break;
164 case ARMV7A_MODE_SVC: return 3; break;
165 case ARMV7A_MODE_ABT: return 4; break;
166 case ARMV7A_MODE_UND: return 5; break;
167 case ARMV7A_MODE_SYS: return 6; break;
168 case ARMV7A_MODE_MON: return 7; break;
169 case ARMV7A_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
170 default:
171 LOG_ERROR("invalid mode value encountered, val %d", mode);
172 return -1;
173 }
174 }
175
176 /* map linear number to mode bits */
177 static inline enum armv7a_mode armv7a_number_to_mode(int number)
178 {
179 switch(number)
180 {
181 case 0: return ARMV7A_MODE_USR; break;
182 case 1: return ARMV7A_MODE_FIQ; break;
183 case 2: return ARMV7A_MODE_IRQ; break;
184 case 3: return ARMV7A_MODE_SVC; break;
185 case 4: return ARMV7A_MODE_ABT; break;
186 case 5: return ARMV7A_MODE_UND; break;
187 case 6: return ARMV7A_MODE_SYS; break;
188 case 7: return ARMV7A_MODE_MON; break;
189 default:
190 LOG_ERROR("mode index out of bounds");
191 return ARMV7A_MODE_ANY;
192 }
193 };
194
195
196 #endif /* ARMV4_5_H */

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