src/target/armv7a.h

   1 /***************************************************************************
   2  *    Copyright (C) 2009 by David Brownell                                 *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  16  ***************************************************************************/
  17
  18 #ifndef OPENOCD_TARGET_ARMV7A_H
  19 #define OPENOCD_TARGET_ARMV7A_H
  20
  21 #include "arm_adi_v5.h"
  22 #include "armv7a_cache.h"
  23 #include "arm.h"
  24 #include "armv4_5_mmu.h"
  25 #include "armv4_5_cache.h"
  26 #include "arm_dpm.h"
  27
  28 enum {
  29         ARM_PC  = 15,
  30         ARM_CPSR = 16
  31 };
  32
  33 #define ARMV7_COMMON_MAGIC 0x0A450999
  34
  35 /* VA to PA translation operations opc2 values*/
  36 #define V2PCWPR  0
  37 #define V2PCWPW  1
  38 #define V2PCWUR  2
  39 #define V2PCWUW  3
  40 #define V2POWPR  4
  41 #define V2POWPW  5
  42 #define V2POWUR  6
  43 #define V2POWUW  7
  44 /*   L210/L220 cache controller support */
  45 struct armv7a_l2x_cache {
  46         uint32_t base;
  47         uint32_t way;
  48 };
  49
  50 struct armv7a_cachesize {
  51         /*  cache dimensioning */
  52         uint32_t linelen;
  53         uint32_t associativity;
  54         uint32_t nsets;
  55         uint32_t cachesize;
  56         /* info for set way operation on cache */
  57         uint32_t index;
  58         uint32_t index_shift;
  59         uint32_t way;
  60         uint32_t way_shift;
  61 };
  62
  63 /* information about one architecture cache at any level */
  64 struct armv7a_arch_cache {
  65         int ctype;                              /* cache type, CLIDR encoding */
  66         struct armv7a_cachesize d_u_size;       /* data cache */
  67         struct armv7a_cachesize i_size;         /* instruction cache */
  68 };
  69
  70 /* common cache information */
  71 struct armv7a_cache_common {
  72         int info;                               /* -1 invalid, else valid */
  73         int loc;                                /* level of coherency */
  74         uint32_t dminline;                      /* minimum d-cache linelen */
  75         uint32_t iminline;                      /* minimum i-cache linelen */
  76         struct armv7a_arch_cache arch[6];       /* cache info, L1 - L7 */
  77         int i_cache_enabled;
  78         int d_u_cache_enabled;
  79         int auto_cache_enabled;                 /* openocd automatic
  80                                                  * cache handling */
  81         /* outer unified cache if some */
  82         void *outer_cache;
  83         int (*flush_all_data_cache)(struct target *target);
  84 };
  85
  86 struct armv7a_mmu_common {
  87         /* following field mmu working way */
  88         int32_t cached;     /* 0: not initialized, 1: initialized */
  89         uint32_t ttbcr;     /* cache for ttbcr register */
  90         uint32_t ttbr[2];
  91         uint32_t ttbr_mask[2];
  92         uint32_t ttbr_range[2];
  93
  94         int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
  95                         uint32_t count, uint8_t *buffer);
  96         struct armv7a_cache_common armv7a_cache;
  97         uint32_t mmu_enabled;
  98 };
  99
 100 struct armv7a_common {
 101         struct arm arm;
 102         int common_magic;
 103         struct reg_cache *core_cache;
 104
 105         /* Core Debug Unit */
 106         struct arm_dpm dpm;
 107         uint32_t debug_base;
 108         struct adiv5_ap *debug_ap;
 109         /* mdir */
 110         uint8_t multi_processor_system;
 111         uint8_t multi_threading_processor;
 112         uint8_t level2_id;
 113         uint8_t cluster_id;
 114         uint8_t cpu_id;
 115         bool is_armv7r;
 116         uint32_t rev;
 117         uint32_t partnum;
 118         uint32_t arch;
 119         uint32_t variant;
 120         uint32_t implementor;
 121
 122         /* cache specific to V7 Memory Management Unit compatible with v4_5*/
 123         struct armv7a_mmu_common armv7a_mmu;
 124
 125         int (*examine_debug_reason)(struct target *target);
 126         int (*post_debug_entry)(struct target *target);
 127
 128         void (*pre_restore_context)(struct target *target);
 129 };
 130
 131 static inline struct armv7a_common *
 132 target_to_armv7a(struct target *target)
 133 {
 134         return container_of(target->arch_info, struct armv7a_common, arm);
 135 }
 136
 137 static inline bool is_armv7a(struct armv7a_common *armv7a)
 138 {
 139         return armv7a->common_magic == ARMV7_COMMON_MAGIC;
 140 }
 141
 142
 143 /* register offsets from armv7a.debug_base */
 144
 145 /* See ARMv7a arch spec section C10.2 */
 146 #define CPUDBG_DIDR             0x000
 147
 148 /* See ARMv7a arch spec section C10.3 */
 149 #define CPUDBG_WFAR             0x018
 150 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
 151 #define CPUDBG_DSCR             0x088
 152 #define CPUDBG_DRCR             0x090
 153 #define CPUDBG_PRCR             0x310
 154 #define CPUDBG_PRSR             0x314
 155
 156 /* See ARMv7a arch spec section C10.4 */
 157 #define CPUDBG_DTRRX            0x080
 158 #define CPUDBG_ITR              0x084
 159 #define CPUDBG_DTRTX            0x08c
 160
 161 /* See ARMv7a arch spec section C10.5 */
 162 #define CPUDBG_BVR_BASE         0x100
 163 #define CPUDBG_BCR_BASE         0x140
 164 #define CPUDBG_WVR_BASE         0x180
 165 #define CPUDBG_WCR_BASE         0x1C0
 166 #define CPUDBG_VCR              0x01C
 167
 168 /* See ARMv7a arch spec section C10.6 */
 169 #define CPUDBG_OSLAR            0x300
 170 #define CPUDBG_OSLSR            0x304
 171 #define CPUDBG_OSSRR            0x308
 172 #define CPUDBG_ECR              0x024
 173
 174 /* See ARMv7a arch spec section C10.7 */
 175 #define CPUDBG_DSCCR            0x028
 176 #define CPUDBG_DSMCR            0x02C
 177
 178 /* See ARMv7a arch spec section C10.8 */
 179 #define CPUDBG_AUTHSTATUS       0xFB8
 180
 181 /* See ARMv7a arch spec DDI 0406C C11.10 */
 182 #define CPUDBG_ID_PFR1          0xD24
 183
 184 /* Masks for Vector Catch register */
 185 #define DBG_VCR_FIQ_MASK        ((1 << 31) | (1 << 7))
 186 #define DBG_VCR_IRQ_MASK        ((1 << 30) | (1 << 6))
 187 #define DBG_VCR_DATA_ABORT_MASK ((1 << 28) | (1 << 4))
 188 #define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
 189 #define DBG_VCR_SVC_MASK        ((1 << 26) | (1 << 2))
 190
 191 /* Masks for Multiprocessor Affinity Register */
 192 #define MPIDR_MP_EXT            (1UL << 31)
 193
 194 int armv7a_arch_state(struct target *target);
 195 int armv7a_identify_cache(struct target *target);
 196 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 197
 198 int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 199                 struct armv7a_cache_common *armv7a_cache);
 200 int armv7a_read_ttbcr(struct target *target);
 201
 202 extern const struct command_registration armv7a_command_handlers[];
 203
 204 #endif /* OPENOCD_TARGET_ARMV7A_H */