src/target/armv7a.h

   1 /***************************************************************************
   2  *    Copyright (C) 2009 by David Brownell                                 *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef ARMV7A_H
  21 #define ARMV7A_H
  22
  23 #include "arm_adi_v5.h"
  24 #include "arm.h"
  25 #include "armv4_5_mmu.h"
  26 #include "armv4_5_cache.h"
  27 #include "arm_dpm.h"
  28
  29 enum {
  30         ARM_PC  = 15,
  31         ARM_CPSR = 16
  32 };
  33
  34 #define ARMV7_COMMON_MAGIC 0x0A450999
  35
  36 /* VA to PA translation operations opc2 values*/
  37 #define V2PCWPR  0
  38 #define V2PCWPW  1
  39 #define V2PCWUR  2
  40 #define V2PCWUW  3
  41 #define V2POWPR  4
  42 #define V2POWPW  5
  43 #define V2POWUR  6
  44 #define V2POWUW  7
  45 /*   L210/L220 cache controller support */
  46 struct armv7a_l2x_cache {
  47         uint32_t base;
  48         uint32_t way;
  49 };
  50
  51 struct armv7a_cachesize {
  52         uint32_t level_num;
  53         /*  cache dimensionning */
  54         uint32_t linelen;
  55         uint32_t associativity;
  56         uint32_t nsets;
  57         uint32_t cachesize;
  58         /* info for set way operation on cache */
  59         uint32_t index;
  60         uint32_t index_shift;
  61         uint32_t way;
  62         uint32_t way_shift;
  63 };
  64
  65 struct armv7a_cache_common {
  66         int ctype;
  67         struct armv7a_cachesize d_u_size;       /* data cache */
  68         struct armv7a_cachesize i_size;         /* instruction cache */
  69         int i_cache_enabled;
  70         int d_u_cache_enabled;
  71         /* l2 external unified cache if some */
  72         void *l2_cache;
  73         int (*flush_all_data_cache)(struct target *target);
  74         int (*display_cache_info)(struct command_context *cmd_ctx,
  75                         struct armv7a_cache_common *armv7a_cache);
  76 };
  77
  78 struct armv7a_mmu_common {
  79         /* following field mmu working way */
  80         int32_t cached;     /* 0: not initialized, 1: initialized */
  81         uint32_t ttbcr;     /* cache for ttbcr register */
  82         uint32_t ttbr_mask[2];
  83         uint32_t ttbr_range[2];
  84         uint32_t os_border;
  85
  86         int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
  87                         uint32_t count, uint8_t *buffer);
  88         struct armv7a_cache_common armv7a_cache;
  89         uint32_t mmu_enabled;
  90 };
  91
  92 struct armv7a_common {
  93         struct arm arm;
  94         int common_magic;
  95         struct reg_cache *core_cache;
  96
  97         struct adiv5_dap dap;
  98
  99         /* Core Debug Unit */
 100         struct arm_dpm dpm;
 101         uint32_t debug_base;
 102         uint8_t debug_ap;
 103         uint8_t memory_ap;
 104         bool memory_ap_available;
 105         /* mdir */
 106         uint8_t multi_processor_system;
 107         uint8_t cluster_id;
 108         uint8_t cpu_id;
 109         bool is_armv7r;
 110         uint32_t rev;
 111         uint32_t partnum;
 112         uint32_t arch;
 113         uint32_t variant;
 114         uint32_t implementor;
 115
 116         /* cache specific to V7 Memory Management Unit compatible with v4_5*/
 117         struct armv7a_mmu_common armv7a_mmu;
 118
 119         int (*examine_debug_reason)(struct target *target);
 120         int (*post_debug_entry)(struct target *target);
 121
 122         void (*pre_restore_context)(struct target *target);
 123 };
 124
 125 static inline struct armv7a_common *
 126 target_to_armv7a(struct target *target)
 127 {
 128         return container_of(target->arch_info, struct armv7a_common, arm);
 129 }
 130
 131 /* register offsets from armv7a.debug_base */
 132
 133 /* See ARMv7a arch spec section C10.2 */
 134 #define CPUDBG_DIDR             0x000
 135
 136 /* See ARMv7a arch spec section C10.3 */
 137 #define CPUDBG_WFAR             0x018
 138 /* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
 139 #define CPUDBG_DSCR             0x088
 140 #define CPUDBG_DRCR             0x090
 141 #define CPUDBG_PRCR             0x310
 142 #define CPUDBG_PRSR             0x314
 143
 144 /* See ARMv7a arch spec section C10.4 */
 145 #define CPUDBG_DTRRX            0x080
 146 #define CPUDBG_ITR              0x084
 147 #define CPUDBG_DTRTX            0x08c
 148
 149 /* See ARMv7a arch spec section C10.5 */
 150 #define CPUDBG_BVR_BASE         0x100
 151 #define CPUDBG_BCR_BASE         0x140
 152 #define CPUDBG_WVR_BASE         0x180
 153 #define CPUDBG_WCR_BASE         0x1C0
 154 #define CPUDBG_VCR              0x01C
 155
 156 /* See ARMv7a arch spec section C10.6 */
 157 #define CPUDBG_OSLAR            0x300
 158 #define CPUDBG_OSLSR            0x304
 159 #define CPUDBG_OSSRR            0x308
 160 #define CPUDBG_ECR              0x024
 161
 162 /* See ARMv7a arch spec section C10.7 */
 163 #define CPUDBG_DSCCR            0x028
 164
 165 /* See ARMv7a arch spec section C10.8 */
 166 #define CPUDBG_AUTHSTATUS       0xFB8
 167
 168 int armv7a_arch_state(struct target *target);
 169 int armv7a_identify_cache(struct target *target);
 170 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 171 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
 172                 uint32_t *val, int meminfo);
 173 int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
 174
 175 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 176                 struct armv7a_cache_common *armv7a_cache);
 177
 178 extern const struct command_registration armv7a_command_handlers[];
 179
 180 #endif /* ARMV4_5_H */