1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm7_9_common.h"
27 #include "armv4_5_mmu.h"
31 u32
armv4mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 va
, int *type
, u32
*cb
, int *domain
, u32
*ap
);
32 int armv4_5_mmu_read_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
33 int armv4_5_mmu_write_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
35 char* armv4_5_mmu_page_type_names
[] =
37 "section", "large page", "small page", "tiny page"
40 u32
armv4_5_mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 va
, int *type
, u32
*cb
, int *domain
, u32
*ap
)
42 u32 first_lvl_descriptor
= 0x0;
43 u32 second_lvl_descriptor
= 0x0;
44 u32 ttb
= armv4_5_mmu
->get_ttb(target
);
46 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
47 (ttb
& 0xffffc000) | ((va
& 0xfff00000) >> 18),
48 4, 1, (u8
*)&first_lvl_descriptor
);
50 DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor
);
52 if ((first_lvl_descriptor
& 0x3) == 0)
55 return ERROR_TARGET_TRANSLATION_FAULT
;
58 if (!armv4_5_mmu
->has_tiny_pages
&& ((first_lvl_descriptor
& 0x3) == 3))
61 return ERROR_TARGET_TRANSLATION_FAULT
;
64 /* domain is always specified in bits 8-5 */
65 *domain
= (first_lvl_descriptor
& 0x1e0) >> 5;
67 if ((first_lvl_descriptor
& 0x3) == 2)
69 /* section descriptor */
70 *type
= ARMV4_5_SECTION
;
71 *cb
= (first_lvl_descriptor
& 0xc) >> 2;
72 *ap
= (first_lvl_descriptor
& 0xc00) >> 10;
73 return (first_lvl_descriptor
& 0xfff00000) | (va
& 0x000fffff);
76 if ((first_lvl_descriptor
& 0x3) == 1)
78 /* coarse page table */
79 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
80 (first_lvl_descriptor
& 0xfffffc00) | ((va
& 0x000ff000) >> 10),
81 4, 1, (u8
*)&second_lvl_descriptor
);
84 if ((first_lvl_descriptor
& 0x3) == 3)
87 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
88 (first_lvl_descriptor
& 0xfffff000) | ((va
& 0x000ffc00) >> 8),
89 4, 1, (u8
*)&second_lvl_descriptor
);
92 DEBUG("2nd lvl desc: %8.8x", first_lvl_descriptor
);
94 if ((second_lvl_descriptor
& 0x3) == 0)
97 return ERROR_TARGET_TRANSLATION_FAULT
;
100 /* cacheable/bufferable is always specified in bits 3-2 */
101 *cb
= (second_lvl_descriptor
& 0xc) >> 2;
103 if ((second_lvl_descriptor
& 0x3) == 1)
105 /* large page descriptor */
106 *type
= ARMV4_5_LARGE_PAGE
;
107 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
108 return (second_lvl_descriptor
& 0xffff0000) | (va
& 0x0000ffff);
111 if ((second_lvl_descriptor
& 0x3) == 2)
113 /* small page descriptor */
114 *type
= ARMV4_5_SMALL_PAGE
;
115 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
116 return (second_lvl_descriptor
& 0xfffff000) | (va
& 0x00000fff);
119 if ((second_lvl_descriptor
& 0x3) == 3)
121 /* tiny page descriptor */
122 *type
= ARMV4_5_TINY_PAGE
;
123 *ap
= (second_lvl_descriptor
& 0x30) >> 4;
124 return (second_lvl_descriptor
& 0xfffffc00) | (va
& 0x000003ff);
127 /* should not happen */
129 return ERROR_TARGET_TRANSLATION_FAULT
;
132 int armv4_5_mmu_read_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
136 if (target
->state
!= TARGET_HALTED
)
137 return ERROR_TARGET_NOT_HALTED
;
139 /* disable MMU and data (or unified) cache */
140 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
142 retval
= armv4_5_mmu
->read_memory(target
, address
, size
, count
, buffer
);
144 /* reenable MMU / cache */
145 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
146 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
147 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
152 int armv4_5_mmu_write_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
156 if (target
->state
!= TARGET_HALTED
)
157 return ERROR_TARGET_NOT_HALTED
;
159 /* disable MMU and data (or unified) cache */
160 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
162 retval
= armv4_5_mmu
->write_memory(target
, address
, size
, count
, buffer
);
164 /* reenable MMU / cache */
165 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
166 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
167 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
172 int armv4_5_mmu_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
181 if (target
->state
!= TARGET_HALTED
)
183 command_print(cmd_ctx
, "target must be stopped for \"virt2phys\" command");
189 command_print(cmd_ctx
, "usage: virt2phys <virtual address>");
195 va
= strtoul(args
[0], NULL
, 0);
196 pa
= armv4_5_mmu_translate_va(target
, armv4_5_mmu
, va
, &type
, &cb
, &domain
, &ap
);
201 case ERROR_TARGET_TRANSLATION_FAULT
:
202 command_print(cmd_ctx
, "no valid translation for 0x%8.8x", va
);
205 command_print(cmd_ctx
, "unknown translation error");
210 command_print(cmd_ctx
, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
211 va
, pa
, armv4_5_mmu_page_type_names
[type
], cb
, domain
, ap
);
217 int armv4_5_mmu_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
231 if (target
->state
!= TARGET_HALTED
)
233 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
241 count
= strtoul(args
[1], NULL
, 0);
243 address
= strtoul(args
[0], NULL
, 0);
260 buffer
= calloc(count
, size
);
261 if ((retval
= armv4_5_mmu_read_physical(target
, armv4_5_mmu
, address
, size
, count
, buffer
)) != ERROR_OK
)
265 case ERROR_TARGET_UNALIGNED_ACCESS
:
266 command_print(cmd_ctx
, "error: address not aligned");
268 case ERROR_TARGET_NOT_HALTED
:
269 command_print(cmd_ctx
, "error: target must be halted for memory accesses");
271 case ERROR_TARGET_DATA_ABORT
:
272 command_print(cmd_ctx
, "error: access caused data abort, system possibly corrupted");
275 command_print(cmd_ctx
, "error: unknown error");
281 for (i
= 0; i
< count
; i
++)
284 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "0x%8.8x: ", address
+ (i
*size
));
289 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%8.8x ", ((u32
*)buffer
)[i
]);
292 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%4.4x ", ((u16
*)buffer
)[i
]);
295 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%2.2x ", ((u8
*)buffer
)[i
]);
299 if ((i
%8 == 7) || (i
== count
- 1))
301 command_print(cmd_ctx
, output
);
311 int armv4_5_mmu_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
317 if (target
->state
!= TARGET_HALTED
)
319 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
326 address
= strtoul(args
[0], NULL
, 0);
327 value
= strtoul(args
[1], NULL
, 0);
332 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 4, 1, (u8
*)&value
);
335 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 2, 1, (u8
*)&value
);
338 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 1, 1, (u8
*)&value
);
346 case ERROR_TARGET_UNALIGNED_ACCESS
:
347 command_print(cmd_ctx
, "error: address not aligned");
349 case ERROR_TARGET_DATA_ABORT
:
350 command_print(cmd_ctx
, "error: access caused data abort, system possibly corrupted");
352 case ERROR_TARGET_NOT_HALTED
:
353 command_print(cmd_ctx
, "error: target must be halted for memory accesses");
358 command_print(cmd_ctx
, "error: unknown error");
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