build: add helper/types.h to config.h
[openocd.git] / src / target / armv4_5_cache.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #ifndef ARMV4_5_CACHE_H
22 #define ARMV4_5_CACHE_H
23
24 struct command_context;
25
26 struct armv4_5_cachesize {
27 int linelen;
28 int associativity;
29 int nsets;
30 int cachesize;
31 };
32
33 struct armv4_5_cache_common {
34 int ctype; /* specify supported cache operations */
35 int separate; /* separate caches or unified cache */
36 struct armv4_5_cachesize d_u_size; /* data cache */
37 struct armv4_5_cachesize i_size; /* instruction cache */
38 int i_cache_enabled;
39 int d_u_cache_enabled;
40 };
41
42 int armv4_5_identify_cache(uint32_t cache_type_reg,
43 struct armv4_5_cache_common *cache);
44 int armv4_5_cache_state(uint32_t cp15_control_reg,
45 struct armv4_5_cache_common *cache);
46
47 int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
48 struct armv4_5_cache_common *armv4_5_cache);
49
50 enum {
51 ARMV4_5_D_U_CACHE_ENABLED = 0x4,
52 ARMV4_5_I_CACHE_ENABLED = 0x1000,
53 ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
54 ARMV4_5_CACHE_RR_BIT = 0x5000,
55 };
56
57 #endif /* ARMV4_5_CACHE_H */