src/target/armv4_5_cache.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #include "armv4_5_cache.h"
  21
  22 #include "log.h"
  23 #include "command.h"
  24
  25 int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
  26 {
  27         int size, assoc, M, len, multiplier;
  28
  29         cache->ctype = (cache_type_reg & 0x1e000000U) >> 25;
  30         cache->separate = (cache_type_reg & 0x01000000U) >> 24;
  31
  32         size = (cache_type_reg & 0x1c0000) >> 18;
  33         assoc = (cache_type_reg & 0x38000) >> 15;
  34         M = (cache_type_reg & 0x4000) >> 14;
  35         len = (cache_type_reg & 0x3000) >> 12;
  36         multiplier = 2 + M;
  37
  38         if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
  39         {
  40                 /* cache is present */
  41                 cache->d_u_size.linelen = 1 << (len + 3);
  42                 cache->d_u_size.associativity = multiplier << (assoc - 1);
  43                 cache->d_u_size.nsets = 1 << (size + 6 - assoc - len);
  44                 cache->d_u_size.cachesize = multiplier << (size + 8);
  45         }
  46         else
  47         {
  48                 /* cache is absent */
  49                 cache->d_u_size.linelen = -1;
  50                 cache->d_u_size.associativity = -1;
  51                 cache->d_u_size.nsets = -1;
  52                 cache->d_u_size.cachesize = -1;
  53         }
  54
  55         if (cache->separate)
  56         {
  57                 size = (cache_type_reg & 0x1c0) >> 6;
  58                 assoc = (cache_type_reg & 0x38) >> 3;
  59                 M = (cache_type_reg & 0x4) >> 2;
  60                 len = (cache_type_reg & 0x3);
  61                 multiplier = 2 + M;
  62
  63                 if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
  64                 {
  65                         /* cache is present */
  66                         cache->i_size.linelen = 1 << (len + 3);
  67                         cache->i_size.associativity = multiplier << (assoc - 1);
  68                         cache->i_size.nsets = 1 << (size + 6 - assoc - len);
  69                         cache->i_size.cachesize = multiplier << (size + 8);
  70                 }
  71                 else
  72                 {
  73                         /* cache is absent */
  74                         cache->i_size.linelen = -1;
  75                         cache->i_size.associativity = -1;
  76                         cache->i_size.nsets = -1;
  77                         cache->i_size.cachesize = -1;
  78                 }
  79         }
  80         else
  81         {
  82                 cache->i_size = cache->d_u_size;
  83         }
  84
  85         return ERROR_OK;
  86 }
  87
  88 int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache)
  89 {
  90         if (armv4_5_cache->ctype == -1)
  91         {
  92                 command_print(cmd_ctx, "cache not yet identified");
  93                 return ERROR_OK;
  94         }
  95
  96         command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
  97                 (armv4_5_cache->separate) ? "separate caches" : "unified cache");
  98
  99         command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 100                 armv4_5_cache->d_u_size.linelen,
 101                 armv4_5_cache->d_u_size.associativity,
 102                 armv4_5_cache->d_u_size.nsets,
 103                 armv4_5_cache->d_u_size.cachesize);
 104
 105         command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 106                 armv4_5_cache->i_size.linelen,
 107                 armv4_5_cache->i_size.associativity,
 108                 armv4_5_cache->i_size.nsets,
 109                 armv4_5_cache->i_size.cachesize);
 110
 111         return ERROR_OK;
 112 }