1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
29 #include <target/target.h>
30 #include <helper/command.h>
46 const char *arm_mode_name(unsigned psr_mode
);
47 bool is_arm_mode(unsigned psr_mode
);
49 int arm_mode_to_number(enum arm_mode mode
);
50 enum arm_mode
armv4_5_number_to_mode(int number
);
52 typedef enum armv4_5_state
60 extern char* armv4_5_state_strings
[];
62 extern const int armv4_5_core_reg_map
[8][17];
64 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
65 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
67 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
68 enum { ARMV4_5_CPSR
= 31, };
70 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
73 * Represents a generic ARM core, with standard application registers.
75 * There are sixteen application registers (including PC, SP, LR) and a PSR.
76 * Cortex-M series cores do not support as many core states or shadowed
77 * registers as traditional ARM cores, and only support Thumb2 instructions.
82 struct reg_cache
*core_cache
;
84 /** Handle to the CPSR; valid in all core modes. */
87 /** Handle to the SPSR; valid only in core modes with an SPSR. */
93 * Indicates what registers are in the ARM state core register set.
94 * ARM_MODE_ANY indicates the standard set of 37 registers,
95 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
96 * more registers are shadowed, for "Secure Monitor" mode.
98 enum arm_mode core_type
;
100 enum arm_mode core_mode
;
101 enum armv4_5_state core_state
;
103 /** Flag reporting unavailability of the BKPT instruction. */
106 /** Flag reporting whether semihosting is active. */
109 /** Value to be returned by semihosting SYS_ERRNO request. */
110 int semihosting_errno
;
112 /** Backpointer to the target. */
113 struct target
*target
;
115 /** Handle for the debug module, if one is present. */
118 /** Handle for the Embedded Trace Module, if one is present. */
119 struct etm_context
*etm
;
121 /* FIXME all these methods should take "struct arm *" not target */
123 int (*full_context
)(struct target
*target
);
124 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
125 int num
, enum arm_mode mode
);
126 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
127 int num
, enum arm_mode mode
, uint32_t value
);
129 /** Read coprocessor register. */
130 int (*mrc
)(struct target
*target
, int cpnum
,
131 uint32_t op1
, uint32_t op2
,
132 uint32_t CRn
, uint32_t CRm
,
135 /* Write coprocessor register. */
136 int (*mcr
)(struct target
*target
, int cpnum
,
137 uint32_t op1
, uint32_t op2
,
138 uint32_t CRn
, uint32_t CRm
,
144 #define target_to_armv4_5 target_to_arm
146 /** Convert target handle to generic ARM target state handle. */
147 static inline struct arm
*target_to_arm(struct target
*target
)
149 return target
->arch_info
;
152 static inline bool is_arm(struct arm
*arm
)
154 return arm
&& arm
->common_magic
== ARMV4_5_COMMON_MAGIC
;
157 struct armv4_5_algorithm
161 enum arm_mode core_mode
;
162 enum armv4_5_state core_state
;
169 struct target
*target
;
170 struct arm
*armv4_5_common
;
174 struct reg_cache
* armv4_5_build_reg_cache(struct target
*target
,
175 struct arm
*armv4_5_common
);
177 int armv4_5_arch_state(struct target
*target
);
178 int armv4_5_get_gdb_reg_list(struct target
*target
,
179 struct reg
**reg_list
[], int *reg_list_size
);
181 extern const struct command_registration arm_command_handlers
[];
183 int armv4_5_init_arch_info(struct target
*target
, struct arm
*armv4_5
);
185 int armv4_5_run_algorithm(struct target
*target
,
186 int num_mem_params
, struct mem_param
*mem_params
,
187 int num_reg_params
, struct reg_param
*reg_params
,
188 uint32_t entry_point
, uint32_t exit_point
,
189 int timeout_ms
, void *arch_info
);
191 int arm_checksum_memory(struct target
*target
,
192 uint32_t address
, uint32_t count
, uint32_t *checksum
);
193 int arm_blank_check_memory(struct target
*target
,
194 uint32_t address
, uint32_t count
, uint32_t *blank
);
196 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
197 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
199 extern struct reg arm_gdb_dummy_fp_reg
;
200 extern struct reg arm_gdb_dummy_fps_reg
;
202 /* ARM mode instructions
205 /* Store multiple increment after
207 * List: for each bit in list: store register
208 * S: in priviledged mode: store user-mode registers
209 * W = 1: update the base register. W = 0: leave the base register untouched
211 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
213 /* Load multiple increment after
215 * List: for each bit in list: store register
216 * S: in priviledged mode: store user-mode registers
217 * W = 1: update the base register. W = 0: leave the base register untouched
219 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
222 #define ARMV4_5_NOP (0xe1a08008)
224 /* Move PSR to general purpose register
225 * R = 1: SPSR R = 0: CPSR
226 * Rn: target register
228 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
231 * Rd: register to store
234 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
237 * Rd: register to load
240 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
242 /* Move general purpose register to PSR
243 * R = 1: SPSR R = 0: CPSR
245 * 1: control field 2: extension field 4: status field 8: flags field
246 * Rm: source register
248 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
249 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
251 /* Load Register Halfword Immediate Post-Index
252 * Rd: register to load
255 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
257 /* Load Register Byte Immediate Post-Index
258 * Rd: register to load
261 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
263 /* Store register Halfword Immediate Post-Index
264 * Rd: register to store
267 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
269 /* Store register Byte Immediate Post-Index
270 * Rd: register to store
273 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
276 * Im: Branch target (left-shifted by 2 bits, added to PC)
277 * L: 1: branch and link 0: branch only
279 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
281 /* Branch and exchange (ARM state)
282 * Rm: register holding branch target address
284 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
286 /* Move to ARM register from coprocessor
287 * CP: Coprocessor number
288 * op1: Coprocessor opcode
289 * Rd: destination register
290 * CRn: first coprocessor operand
291 * CRm: second coprocessor operand
292 * op2: Second coprocessor opcode
294 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
296 /* Move to coprocessor from ARM register
297 * CP: Coprocessor number
298 * op1: Coprocessor opcode
299 * Rd: destination register
300 * CRn: first coprocessor operand
301 * CRm: second coprocessor operand
302 * op2: Second coprocessor opcode
304 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
306 /* Breakpoint instruction (ARMv5)
307 * Im: 16-bit immediate
309 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
312 /* Thumb mode instructions
315 /* Store register (Thumb mode)
316 * Rd: source register
319 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
321 /* Load register (Thumb state)
322 * Rd: destination register
325 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
327 /* Load multiple (Thumb state)
329 * List: for each bit in list: store register
331 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
333 /* Load register with PC relative addressing
334 * Rd: register to load
336 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
338 /* Move hi register (Thumb mode)
339 * Rd: destination register
340 * Rm: source register
342 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
344 /* No operation (Thumb mode)
346 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
348 /* Move immediate to register (Thumb state)
349 * Rd: destination register
350 * Im: 8-bit immediate value
352 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
354 /* Branch and Exchange
355 * Rm: register containing branch target
357 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
359 /* Branch (Thumb state)
362 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
364 /* Breakpoint instruction (ARMv5) (Thumb state)
365 * Im: 8-bit immediate
367 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
369 /* build basic mrc/mcr opcode */
371 static inline uint32_t mrc_opcode(int cpnum
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
)
381 #endif /* ARMV4_5_H */
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