src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include <target/target.h>
  30 #include <helper/command.h>
  31
  32
  33 /**
  34  * These numbers match the five low bits of the *PSR registers on
  35  * "classic ARM" processors, which build on the ARMv4 processor
  36  * modes and register set.
  37  */
  38 enum arm_mode {
  39         ARM_MODE_USR = 16,
  40         ARM_MODE_FIQ = 17,
  41         ARM_MODE_IRQ = 18,
  42         ARM_MODE_SVC = 19,
  43         ARM_MODE_ABT = 23,
  44         ARM_MODE_MON = 26,
  45         ARM_MODE_UND = 27,
  46         ARM_MODE_SYS = 31,
  47         ARM_MODE_ANY = -1
  48 };
  49
  50 const char *arm_mode_name(unsigned psr_mode);
  51 bool is_arm_mode(unsigned psr_mode);
  52
  53 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  54 enum arm_state {
  55         ARM_STATE_ARM,
  56         ARM_STATE_THUMB,
  57         ARM_STATE_JAZELLE,
  58         ARM_STATE_THUMB_EE,
  59 };
  60
  61 extern const char *arm_state_strings[];
  62
  63 /* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
  64  * index into the armv4_5_core_reg_map array.  Its remaining users are
  65  * remnants which could as easily walk * the register cache directly as
  66  * use the expensive ARMV4_5_CORE_REG_MODE() macro.
  67  */
  68 int arm_mode_to_number(enum arm_mode mode);
  69 enum arm_mode armv4_5_number_to_mode(int number);
  70
  71 extern const int armv4_5_core_reg_map[8][17];
  72
  73 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  74                 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
  75
  76 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
  77 enum { ARMV4_5_CPSR = 31, };
  78
  79 #define ARM_COMMON_MAGIC 0x0A450A45
  80
  81 /**
  82  * Represents a generic ARM core, with standard application registers.
  83  *
  84  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  85  * Cortex-M series cores do not support as many core states or shadowed
  86  * registers as traditional ARM cores, and only support Thumb2 instructions.
  87  */
  88 struct arm
  89 {
  90         int common_magic;
  91         struct reg_cache *core_cache;
  92
  93         /** Handle to the CPSR; valid in all core modes. */
  94         struct reg *cpsr;
  95
  96         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  97         struct reg *spsr;
  98
  99         /** Support for arm_reg_current() */
 100         const int *map;
 101
 102         /**
 103          * Indicates what registers are in the ARM state core register set.
 104          * ARM_MODE_ANY indicates the standard set of 37 registers,
 105          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 106          * more registers are shadowed, for "Secure Monitor" mode.
 107          */
 108         enum arm_mode core_type;
 109
 110         /** Record the current core mode: SVC, USR, or some other mode. */
 111         enum arm_mode core_mode;
 112
 113         /** Record the current core state: ARM, Thumb, or otherwise. */
 114         enum arm_state core_state;
 115
 116         /** Flag reporting unavailability of the BKPT instruction. */
 117         bool is_armv4;
 118
 119         /** Flag reporting whether semihosting is active. */
 120         bool is_semihosting;
 121
 122         /** Value to be returned by semihosting SYS_ERRNO request. */
 123         int semihosting_errno;
 124
 125         /** Backpointer to the target. */
 126         struct target *target;
 127
 128         /** Handle for the debug module, if one is present. */
 129         struct arm_dpm *dpm;
 130
 131         /** Handle for the Embedded Trace Module, if one is present. */
 132         struct etm_context *etm;
 133
 134         /* FIXME all these methods should take "struct arm *" not target */
 135
 136         /** Retrieve all core registers, for display. */
 137         int (*full_context)(struct target *target);
 138
 139         /** Retrieve a single core register. */
 140         int (*read_core_reg)(struct target *target, struct reg *reg,
 141                         int num, enum arm_mode mode);
 142         int (*write_core_reg)(struct target *target, struct reg *reg,
 143                         int num, enum arm_mode mode, uint32_t value);
 144
 145         /** Read coprocessor register.  */
 146         int (*mrc)(struct target *target, int cpnum,
 147                         uint32_t op1, uint32_t op2,
 148                         uint32_t CRn, uint32_t CRm,
 149                         uint32_t *value);
 150
 151         /** Write coprocessor register.  */
 152         int (*mcr)(struct target *target, int cpnum,
 153                         uint32_t op1, uint32_t op2,
 154                         uint32_t CRn, uint32_t CRm,
 155                         uint32_t value);
 156
 157         void *arch_info;
 158 };
 159
 160 /** Convert target handle to generic ARM target state handle. */
 161 static inline struct arm *target_to_arm(struct target *target)
 162 {
 163         return target->arch_info;
 164 }
 165
 166 static inline bool is_arm(struct arm *arm)
 167 {
 168         return arm && arm->common_magic == ARM_COMMON_MAGIC;
 169 }
 170
 171 struct arm_algorithm
 172 {
 173         int common_magic;
 174
 175         enum arm_mode core_mode;
 176         enum arm_state core_state;
 177 };
 178
 179 struct arm_reg
 180 {
 181         int num;
 182         enum arm_mode mode;
 183         struct target *target;
 184         struct arm *armv4_5_common;
 185         uint32_t value;
 186 };
 187
 188 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 189
 190 int armv4_5_arch_state(struct target *target);
 191 int armv4_5_get_gdb_reg_list(struct target *target,
 192                 struct reg **reg_list[], int *reg_list_size);
 193
 194 extern const struct command_registration arm_command_handlers[];
 195
 196 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 197
 198 int armv4_5_run_algorithm(struct target *target,
 199                 int num_mem_params, struct mem_param *mem_params,
 200                 int num_reg_params, struct reg_param *reg_params,
 201                 uint32_t entry_point, uint32_t exit_point,
 202                 int timeout_ms, void *arch_info);
 203
 204 int arm_checksum_memory(struct target *target,
 205                 uint32_t address, uint32_t count, uint32_t *checksum);
 206 int arm_blank_check_memory(struct target *target,
 207                 uint32_t address, uint32_t count, uint32_t *blank);
 208
 209 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 210 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 211
 212 extern struct reg arm_gdb_dummy_fp_reg;
 213 extern struct reg arm_gdb_dummy_fps_reg;
 214
 215 /* ARM mode instructions
 216  */
 217
 218 /* Store multiple increment after
 219  * Rn: base register
 220  * List: for each bit in list: store register
 221  * S: in priviledged mode: store user-mode registers
 222  * W = 1: update the base register. W = 0: leave the base register untouched
 223  */
 224 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 225
 226 /* Load multiple increment after
 227  * Rn: base register
 228  * List: for each bit in list: store register
 229  * S: in priviledged mode: store user-mode registers
 230  * W = 1: update the base register. W = 0: leave the base register untouched
 231  */
 232 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 233
 234 /* MOV r8, r8 */
 235 #define ARMV4_5_NOP                                     (0xe1a08008)
 236
 237 /* Move PSR to general purpose register
 238  * R = 1: SPSR R = 0: CPSR
 239  * Rn: target register
 240  */
 241 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 242
 243 /* Store register
 244  * Rd: register to store
 245  * Rn: base register
 246  */
 247 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 248
 249 /* Load register
 250  * Rd: register to load
 251  * Rn: base register
 252  */
 253 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 254
 255 /* Move general purpose register to PSR
 256  * R = 1: SPSR R = 0: CPSR
 257  * Field: Field mask
 258  * 1: control field 2: extension field 4: status field 8: flags field
 259  * Rm: source register
 260  */
 261 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 262 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 263
 264 /* Load Register Halfword Immediate Post-Index
 265  * Rd: register to load
 266  * Rn: base register
 267  */
 268 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 269
 270 /* Load Register Byte Immediate Post-Index
 271  * Rd: register to load
 272  * Rn: base register
 273  */
 274 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 275
 276 /* Store register Halfword Immediate Post-Index
 277  * Rd: register to store
 278  * Rn: base register
 279  */
 280 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 281
 282 /* Store register Byte Immediate Post-Index
 283  * Rd: register to store
 284  * Rn: base register
 285  */
 286 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 287
 288 /* Branch (and Link)
 289  * Im: Branch target (left-shifted by 2 bits, added to PC)
 290  * L: 1: branch and link 0: branch only
 291  */
 292 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 293
 294 /* Branch and exchange (ARM state)
 295  * Rm: register holding branch target address
 296  */
 297 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 298
 299 /* Move to ARM register from coprocessor
 300  * CP: Coprocessor number
 301  * op1: Coprocessor opcode
 302  * Rd: destination register
 303  * CRn: first coprocessor operand
 304  * CRm: second coprocessor operand
 305  * op2: Second coprocessor opcode
 306  */
 307 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 308
 309 /* Move to coprocessor from ARM register
 310  * CP: Coprocessor number
 311  * op1: Coprocessor opcode
 312  * Rd: destination register
 313  * CRn: first coprocessor operand
 314  * CRm: second coprocessor operand
 315  * op2: Second coprocessor opcode
 316  */
 317 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 318
 319 /* Breakpoint instruction (ARMv5)
 320  * Im: 16-bit immediate
 321  */
 322 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 323
 324
 325 /* Thumb mode instructions
 326  */
 327
 328 /* Store register (Thumb mode)
 329  * Rd: source register
 330  * Rn: base register
 331  */
 332 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 333
 334 /* Load register (Thumb state)
 335  * Rd: destination register
 336  * Rn: base register
 337  */
 338 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 339
 340 /* Load multiple (Thumb state)
 341  * Rn: base register
 342  * List: for each bit in list: store register
 343  */
 344 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 345
 346 /* Load register with PC relative addressing
 347  * Rd: register to load
 348  */
 349 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 350
 351 /* Move hi register (Thumb mode)
 352  * Rd: destination register
 353  * Rm: source register
 354  */
 355 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 356
 357 /* No operation (Thumb mode)
 358  */
 359 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 360
 361 /* Move immediate to register (Thumb state)
 362  * Rd: destination register
 363  * Im: 8-bit immediate value
 364  */
 365 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 366
 367 /* Branch and Exchange
 368  * Rm: register containing branch target
 369  */
 370 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 371
 372 /* Branch (Thumb state)
 373  * Imm: Branch target
 374  */
 375 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 376
 377 /* Breakpoint instruction (ARMv5) (Thumb state)
 378  * Im: 8-bit immediate
 379  */
 380 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 381
 382 /* build basic mrc/mcr opcode */
 383
 384 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 385 {
 386         uint32_t t = 0;
 387         t|=op1<<21;
 388         t|=op2<<5;
 389         t|=CRn<<16;
 390         t|=CRm<<0;
 391         return t;
 392 }
 393
 394 #endif /* ARMV4_5_H */