1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 typedef enum armv4_5_mode
33 ARMV4_5_MODE_USR
= 16,
34 ARMV4_5_MODE_FIQ
= 17,
35 ARMV4_5_MODE_IRQ
= 18,
36 ARMV4_5_MODE_SVC
= 19,
37 ARMV4_5_MODE_ABT
= 23,
39 ARMV4_5_MODE_UND
= 27,
40 ARMV4_5_MODE_SYS
= 31,
44 const char *arm_mode_name(unsigned psr_mode
);
45 bool is_arm_mode(unsigned psr_mode
);
47 int armv4_5_mode_to_number(enum armv4_5_mode mode
);
48 enum armv4_5_mode
armv4_5_number_to_mode(int number
);
50 typedef enum armv4_5_state
54 ARMV4_5_STATE_JAZELLE
,
58 extern char* armv4_5_state_strings
[];
60 extern const int armv4_5_core_reg_map
[8][17];
62 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
63 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
65 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
66 enum { ARMV4_5_CPSR
= 31, };
68 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
71 * Represents a generic ARM core, with standard application registers.
73 * There are sixteen application registers (including PC, SP, LR) and a PSR.
74 * Cortex-M series cores do not support as many core states or shadowed
75 * registers as traditional ARM cores, and only support Thumb2 instructions.
80 struct reg_cache
*core_cache
;
82 /** Handle to the CPSR; valid in all core modes. */
85 /** Handle to the SPSR; valid only in core modes with an SPSR. */
91 * Indicates what registers are in the ARM state core register set.
92 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
93 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
94 * more registers are shadowed, for "Secure Monitor" mode.
96 enum armv4_5_mode core_type
;
98 enum armv4_5_mode core_mode
;
99 enum armv4_5_state core_state
;
101 /** Flag reporting unavailability of the BKPT instruction. */
104 /** Handle for the Embedded Trace Module, if one is present. */
105 struct etm_context
*etm
;
107 int (*full_context
)(struct target
*target
);
108 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
109 int num
, enum armv4_5_mode mode
);
110 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
111 int num
, enum armv4_5_mode mode
, uint32_t value
);
115 #define target_to_armv4_5 target_to_arm
117 /** Convert target handle to generic ARM target state handle. */
118 static inline struct arm
*target_to_arm(struct target
*target
)
120 return target
->arch_info
;
123 static inline bool is_arm(struct arm
*arm
)
125 return arm
&& arm
->common_magic
== ARMV4_5_COMMON_MAGIC
;
128 struct armv4_5_algorithm
132 enum armv4_5_mode core_mode
;
133 enum armv4_5_state core_state
;
139 enum armv4_5_mode mode
;
140 struct target
*target
;
141 struct arm
*armv4_5_common
;
145 struct reg_cache
* armv4_5_build_reg_cache(struct target
*target
,
146 struct arm
*armv4_5_common
);
148 int armv4_5_arch_state(struct target
*target
);
149 int armv4_5_get_gdb_reg_list(struct target
*target
,
150 struct reg
**reg_list
[], int *reg_list_size
);
152 int armv4_5_register_commands(struct command_context
*cmd_ctx
);
153 int armv4_5_init_arch_info(struct target
*target
, struct arm
*armv4_5
);
155 int armv4_5_run_algorithm(struct target
*target
,
156 int num_mem_params
, struct mem_param
*mem_params
,
157 int num_reg_params
, struct reg_param
*reg_params
,
158 uint32_t entry_point
, uint32_t exit_point
,
159 int timeout_ms
, void *arch_info
);
161 int arm_checksum_memory(struct target
*target
,
162 uint32_t address
, uint32_t count
, uint32_t *checksum
);
163 int arm_blank_check_memory(struct target
*target
,
164 uint32_t address
, uint32_t count
, uint32_t *blank
);
166 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
167 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
169 extern struct reg arm_gdb_dummy_fp_reg
;
170 extern struct reg arm_gdb_dummy_fps_reg
;
172 /* ARM mode instructions
175 /* Store multiple increment after
177 * List: for each bit in list: store register
178 * S: in priviledged mode: store user-mode registers
179 * W = 1: update the base register. W = 0: leave the base register untouched
181 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
183 /* Load multiple increment after
185 * List: for each bit in list: store register
186 * S: in priviledged mode: store user-mode registers
187 * W = 1: update the base register. W = 0: leave the base register untouched
189 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
192 #define ARMV4_5_NOP (0xe1a08008)
194 /* Move PSR to general purpose register
195 * R = 1: SPSR R = 0: CPSR
196 * Rn: target register
198 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
201 * Rd: register to store
204 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
207 * Rd: register to load
210 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
212 /* Move general purpose register to PSR
213 * R = 1: SPSR R = 0: CPSR
215 * 1: control field 2: extension field 4: status field 8: flags field
216 * Rm: source register
218 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
219 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
221 /* Load Register Halfword Immediate Post-Index
222 * Rd: register to load
225 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
227 /* Load Register Byte Immediate Post-Index
228 * Rd: register to load
231 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
233 /* Store register Halfword Immediate Post-Index
234 * Rd: register to store
237 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
239 /* Store register Byte Immediate Post-Index
240 * Rd: register to store
243 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
246 * Im: Branch target (left-shifted by 2 bits, added to PC)
247 * L: 1: branch and link 0: branch only
249 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
251 /* Branch and exchange (ARM state)
252 * Rm: register holding branch target address
254 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
256 /* Move to ARM register from coprocessor
257 * CP: Coprocessor number
258 * op1: Coprocessor opcode
259 * Rd: destination register
260 * CRn: first coprocessor operand
261 * CRm: second coprocessor operand
262 * op2: Second coprocessor opcode
264 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
266 /* Move to coprocessor from ARM register
267 * CP: Coprocessor number
268 * op1: Coprocessor opcode
269 * Rd: destination register
270 * CRn: first coprocessor operand
271 * CRm: second coprocessor operand
272 * op2: Second coprocessor opcode
274 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
276 /* Breakpoint instruction (ARMv5)
277 * Im: 16-bit immediate
279 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
282 /* Thumb mode instructions
285 /* Store register (Thumb mode)
286 * Rd: source register
289 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
291 /* Load register (Thumb state)
292 * Rd: destination register
295 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
297 /* Load multiple (Thumb state)
299 * List: for each bit in list: store register
301 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
303 /* Load register with PC relative addressing
304 * Rd: register to load
306 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
308 /* Move hi register (Thumb mode)
309 * Rd: destination register
310 * Rm: source register
312 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
314 /* No operation (Thumb mode)
316 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
318 /* Move immediate to register (Thumb state)
319 * Rd: destination register
320 * Im: 8-bit immediate value
322 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
324 /* Branch and Exchange
325 * Rm: register containing branch target
327 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
329 /* Branch (Thumb state)
332 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
334 /* Breakpoint instruction (ARMv5) (Thumb state)
335 * Im: 8-bit immediate
337 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
339 /* build basic mrc/mcr opcode */
341 static inline uint32_t mrc_opcode(int cpnum
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
)
351 #endif /* ARMV4_5_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)