src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "target.h"
  30 #include "log.h"
  31
  32 typedef enum armv4_5_mode
  33 {
  34         ARMV4_5_MODE_USR = 16,
  35         ARMV4_5_MODE_FIQ = 17,
  36         ARMV4_5_MODE_IRQ = 18,
  37         ARMV4_5_MODE_SVC = 19,
  38         ARMV4_5_MODE_ABT = 23,
  39         ARMV4_5_MODE_UND = 27,
  40         ARMV4_5_MODE_SYS = 31,
  41         ARMV4_5_MODE_ANY = -1
  42 } armv4_5_mode_t;
  43
  44 extern char** armv4_5_mode_strings;
  45
  46 typedef enum armv4_5_state
  47 {
  48         ARMV4_5_STATE_ARM,
  49         ARMV4_5_STATE_THUMB,
  50         ARMV4_5_STATE_JAZELLE,
  51 } armv4_5_state_t;
  52
  53 extern char* armv4_5_state_strings[];
  54
  55 extern int armv4_5_core_reg_map[7][17];
  56
  57 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  58                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  59 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  60                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  61
  62 /* offsets into armv4_5 core register cache */
  63 enum
  64 {
  65         ARMV4_5_CPSR = 31,
  66         ARMV4_5_SPSR_FIQ = 32,
  67         ARMV4_5_SPSR_IRQ = 33,
  68         ARMV4_5_SPSR_SVC = 34,
  69         ARMV4_5_SPSR_ABT = 35,
  70         ARMV4_5_SPSR_UND = 36
  71 };
  72
  73 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  74
  75 /* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
  76 #define armv4_5_common_s arm
  77
  78 /**
  79  * Represents a generic ARM core, with standard application registers.
  80  *
  81  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  82  * Cortex-M series cores do not support as many core states or shadowed
  83  * registers as traditional ARM cores, and only support Thumb2 instructions.
  84  */
  85 struct arm
  86 {
  87         int common_magic;
  88         struct reg_cache *core_cache;
  89
  90         int /* armv4_5_mode */ core_mode;
  91         enum armv4_5_state core_state;
  92
  93         /** Flag reporting unavailability of the BKPT instruction. */
  94         bool is_armv4;
  95
  96         /** Handle for the Embedded Trace Module, if one is present. */
  97         struct etm_context *etm;
  98
  99         int (*full_context)(struct target *target);
 100         int (*read_core_reg)(struct target *target,
 101                         int num, enum armv4_5_mode mode);
 102         int (*write_core_reg)(struct target *target,
 103                         int num, enum armv4_5_mode mode, uint32_t value);
 104         void *arch_info;
 105 };
 106
 107 #define target_to_armv4_5 target_to_arm
 108
 109 /** Convert target handle to generic ARM target state handle. */
 110 static inline struct arm *target_to_arm(struct target *target)
 111 {
 112         return target->arch_info;
 113 }
 114
 115 static inline bool is_arm(struct arm *arm)
 116 {
 117         return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
 118 }
 119
 120 struct armv4_5_algorithm
 121 {
 122         int common_magic;
 123
 124         enum armv4_5_mode core_mode;
 125         enum armv4_5_state core_state;
 126 };
 127
 128 struct armv4_5_core_reg
 129 {
 130         int num;
 131         enum armv4_5_mode mode;
 132         struct target *target;
 133         struct arm *armv4_5_common;
 134 };
 135
 136 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
 137                 struct arm *armv4_5_common);
 138
 139 /* map psr mode bits to linear number */
 140 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 141 {
 142         switch (mode)
 143         {
 144                 case ARMV4_5_MODE_USR: return 0; break;
 145                 case ARMV4_5_MODE_FIQ: return 1; break;
 146                 case ARMV4_5_MODE_IRQ: return 2; break;
 147                 case ARMV4_5_MODE_SVC: return 3; break;
 148                 case ARMV4_5_MODE_ABT: return 4; break;
 149                 case ARMV4_5_MODE_UND: return 5; break;
 150                 case ARMV4_5_MODE_SYS: return 6; break;
 151                 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
 152                 default:
 153                         LOG_ERROR("invalid mode value encountered %d", mode);
 154                         return -1;
 155         }
 156 }
 157
 158 /* map linear number to mode bits */
 159 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 160 {
 161         switch (number)
 162         {
 163                 case 0: return ARMV4_5_MODE_USR; break;
 164                 case 1: return ARMV4_5_MODE_FIQ; break;
 165                 case 2: return ARMV4_5_MODE_IRQ; break;
 166                 case 3: return ARMV4_5_MODE_SVC; break;
 167                 case 4: return ARMV4_5_MODE_ABT; break;
 168                 case 5: return ARMV4_5_MODE_UND; break;
 169                 case 6: return ARMV4_5_MODE_SYS; break;
 170                 default:
 171                         LOG_ERROR("mode index out of bounds %d", number);
 172                         return ARMV4_5_MODE_ANY;
 173         }
 174 };
 175
 176 int armv4_5_arch_state(struct target *target);
 177 int armv4_5_get_gdb_reg_list(struct target *target,
 178                 struct reg **reg_list[], int *reg_list_size);
 179
 180 int armv4_5_register_commands(struct command_context *cmd_ctx);
 181 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 182
 183 int armv4_5_run_algorithm(struct target *target,
 184                 int num_mem_params, struct mem_param *mem_params,
 185                 int num_reg_params, struct reg_param *reg_params,
 186                 uint32_t entry_point, uint32_t exit_point,
 187                 int timeout_ms, void *arch_info);
 188
 189 int armv4_5_invalidate_core_regs(struct target *target);
 190
 191 int arm_checksum_memory(struct target *target,
 192                 uint32_t address, uint32_t count, uint32_t *checksum);
 193 int arm_blank_check_memory(struct target *target,
 194                 uint32_t address, uint32_t count, uint32_t *blank);
 195
 196
 197 /* ARM mode instructions
 198  */
 199
 200 /* Store multiple increment after
 201  * Rn: base register
 202  * List: for each bit in list: store register
 203  * S: in priviledged mode: store user-mode registers
 204  * W = 1: update the base register. W = 0: leave the base register untouched
 205  */
 206 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 207
 208 /* Load multiple increment after
 209  * Rn: base register
 210  * List: for each bit in list: store register
 211  * S: in priviledged mode: store user-mode registers
 212  * W = 1: update the base register. W = 0: leave the base register untouched
 213  */
 214 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 215
 216 /* MOV r8, r8 */
 217 #define ARMV4_5_NOP                                     (0xe1a08008)
 218
 219 /* Move PSR to general purpose register
 220  * R = 1: SPSR R = 0: CPSR
 221  * Rn: target register
 222  */
 223 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 224
 225 /* Store register
 226  * Rd: register to store
 227  * Rn: base register
 228  */
 229 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 230
 231 /* Load register
 232  * Rd: register to load
 233  * Rn: base register
 234  */
 235 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 236
 237 /* Move general purpose register to PSR
 238  * R = 1: SPSR R = 0: CPSR
 239  * Field: Field mask
 240  * 1: control field 2: extension field 4: status field 8: flags field
 241  * Rm: source register
 242  */
 243 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 244 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 245
 246 /* Load Register Halfword Immediate Post-Index
 247  * Rd: register to load
 248  * Rn: base register
 249  */
 250 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 251
 252 /* Load Register Byte Immediate Post-Index
 253  * Rd: register to load
 254  * Rn: base register
 255  */
 256 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 257
 258 /* Store register Halfword Immediate Post-Index
 259  * Rd: register to store
 260  * Rn: base register
 261  */
 262 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 263
 264 /* Store register Byte Immediate Post-Index
 265  * Rd: register to store
 266  * Rn: base register
 267  */
 268 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 269
 270 /* Branch (and Link)
 271  * Im: Branch target (left-shifted by 2 bits, added to PC)
 272  * L: 1: branch and link 0: branch only
 273  */
 274 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 275
 276 /* Branch and exchange (ARM state)
 277  * Rm: register holding branch target address
 278  */
 279 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 280
 281 /* Move to ARM register from coprocessor
 282  * CP: Coprocessor number
 283  * op1: Coprocessor opcode
 284  * Rd: destination register
 285  * CRn: first coprocessor operand
 286  * CRm: second coprocessor operand
 287  * op2: Second coprocessor opcode
 288  */
 289 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 290
 291 /* Move to coprocessor from ARM register
 292  * CP: Coprocessor number
 293  * op1: Coprocessor opcode
 294  * Rd: destination register
 295  * CRn: first coprocessor operand
 296  * CRm: second coprocessor operand
 297  * op2: Second coprocessor opcode
 298  */
 299 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 300
 301 /* Breakpoint instruction (ARMv5)
 302  * Im: 16-bit immediate
 303  */
 304 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 305
 306
 307 /* Thumb mode instructions
 308  */
 309
 310 /* Store register (Thumb mode)
 311  * Rd: source register
 312  * Rn: base register
 313  */
 314 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 315
 316 /* Load register (Thumb state)
 317  * Rd: destination register
 318  * Rn: base register
 319  */
 320 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 321
 322 /* Load multiple (Thumb state)
 323  * Rn: base register
 324  * List: for each bit in list: store register
 325  */
 326 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 327
 328 /* Load register with PC relative addressing
 329  * Rd: register to load
 330  */
 331 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 332
 333 /* Move hi register (Thumb mode)
 334  * Rd: destination register
 335  * Rm: source register
 336  */
 337 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 338
 339 /* No operation (Thumb mode)
 340  */
 341 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 342
 343 /* Move immediate to register (Thumb state)
 344  * Rd: destination register
 345  * Im: 8-bit immediate value
 346  */
 347 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 348
 349 /* Branch and Exchange
 350  * Rm: register containing branch target
 351  */
 352 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 353
 354 /* Branch (Thumb state)
 355  * Imm: Branch target
 356  */
 357 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 358
 359 /* Breakpoint instruction (ARMv5) (Thumb state)
 360  * Im: 8-bit immediate
 361  */
 362 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 363
 364 /* build basic mrc/mcr opcode */
 365
 366 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 367 {
 368         uint32_t t = 0;
 369         t|=op1<<21;
 370         t|=op2<<5;
 371         t|=CRn<<16;
 372         t|=CRm<<0;
 373         return t;
 374 }
 375
 376 #endif /* ARMV4_5_H */