1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 typedef enum armv4_5_mode
33 ARMV4_5_MODE_USR
= 16,
34 ARMV4_5_MODE_FIQ
= 17,
35 ARMV4_5_MODE_IRQ
= 18,
36 ARMV4_5_MODE_SVC
= 19,
37 ARMV4_5_MODE_ABT
= 23,
39 ARMV4_5_MODE_UND
= 27,
40 ARMV4_5_MODE_SYS
= 31,
44 const char *arm_mode_name(unsigned psr_mode
);
45 bool is_arm_mode(unsigned psr_mode
);
47 int armv4_5_mode_to_number(enum armv4_5_mode mode
);
48 enum armv4_5_mode
armv4_5_number_to_mode(int number
);
50 typedef enum armv4_5_state
54 ARMV4_5_STATE_JAZELLE
,
57 extern char* armv4_5_state_strings
[];
59 extern const int armv4_5_core_reg_map
[8][17];
61 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
62 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
64 /* offsets into armv4_5 core register cache */
68 ARMV4_5_SPSR_FIQ
= 32,
69 ARMV4_5_SPSR_IRQ
= 33,
70 ARMV4_5_SPSR_SVC
= 34,
71 ARMV4_5_SPSR_ABT
= 35,
72 ARMV4_5_SPSR_UND
= 36,
76 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
78 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
79 #define armv4_5_common_s arm
82 * Represents a generic ARM core, with standard application registers.
84 * There are sixteen application registers (including PC, SP, LR) and a PSR.
85 * Cortex-M series cores do not support as many core states or shadowed
86 * registers as traditional ARM cores, and only support Thumb2 instructions.
91 struct reg_cache
*core_cache
;
94 * Indicates what registers are in the ARM state core register set.
95 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
96 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
97 * more registers are shadowed, for "Secure Monitor" mode.
99 enum armv4_5_mode core_type
;
101 enum armv4_5_mode core_mode
;
102 enum armv4_5_state core_state
;
104 /** Flag reporting unavailability of the BKPT instruction. */
107 /** Handle for the Embedded Trace Module, if one is present. */
108 struct etm_context
*etm
;
110 int (*full_context
)(struct target
*target
);
111 int (*read_core_reg
)(struct target
*target
,
112 int num
, enum armv4_5_mode mode
);
113 int (*write_core_reg
)(struct target
*target
,
114 int num
, enum armv4_5_mode mode
, uint32_t value
);
118 #define target_to_armv4_5 target_to_arm
120 /** Convert target handle to generic ARM target state handle. */
121 static inline struct arm
*target_to_arm(struct target
*target
)
123 return target
->arch_info
;
126 static inline bool is_arm(struct arm
*arm
)
128 return arm
&& arm
->common_magic
== ARMV4_5_COMMON_MAGIC
;
131 struct armv4_5_algorithm
135 enum armv4_5_mode core_mode
;
136 enum armv4_5_state core_state
;
139 struct armv4_5_core_reg
142 enum armv4_5_mode mode
;
143 struct target
*target
;
144 struct arm
*armv4_5_common
;
147 struct reg_cache
* armv4_5_build_reg_cache(struct target
*target
,
148 struct arm
*armv4_5_common
);
150 int armv4_5_arch_state(struct target
*target
);
151 int armv4_5_get_gdb_reg_list(struct target
*target
,
152 struct reg
**reg_list
[], int *reg_list_size
);
154 int armv4_5_register_commands(struct command_context
*cmd_ctx
);
155 int armv4_5_init_arch_info(struct target
*target
, struct arm
*armv4_5
);
157 int armv4_5_run_algorithm(struct target
*target
,
158 int num_mem_params
, struct mem_param
*mem_params
,
159 int num_reg_params
, struct reg_param
*reg_params
,
160 uint32_t entry_point
, uint32_t exit_point
,
161 int timeout_ms
, void *arch_info
);
163 int armv4_5_invalidate_core_regs(struct target
*target
);
165 int arm_checksum_memory(struct target
*target
,
166 uint32_t address
, uint32_t count
, uint32_t *checksum
);
167 int arm_blank_check_memory(struct target
*target
,
168 uint32_t address
, uint32_t count
, uint32_t *blank
);
170 extern struct reg arm_gdb_dummy_fp_reg
;
171 extern struct reg arm_gdb_dummy_fps_reg
;
173 /* ARM mode instructions
176 /* Store multiple increment after
178 * List: for each bit in list: store register
179 * S: in priviledged mode: store user-mode registers
180 * W = 1: update the base register. W = 0: leave the base register untouched
182 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
184 /* Load multiple increment after
186 * List: for each bit in list: store register
187 * S: in priviledged mode: store user-mode registers
188 * W = 1: update the base register. W = 0: leave the base register untouched
190 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
193 #define ARMV4_5_NOP (0xe1a08008)
195 /* Move PSR to general purpose register
196 * R = 1: SPSR R = 0: CPSR
197 * Rn: target register
199 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
202 * Rd: register to store
205 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
208 * Rd: register to load
211 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
213 /* Move general purpose register to PSR
214 * R = 1: SPSR R = 0: CPSR
216 * 1: control field 2: extension field 4: status field 8: flags field
217 * Rm: source register
219 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
220 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
222 /* Load Register Halfword Immediate Post-Index
223 * Rd: register to load
226 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
228 /* Load Register Byte Immediate Post-Index
229 * Rd: register to load
232 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
234 /* Store register Halfword Immediate Post-Index
235 * Rd: register to store
238 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
240 /* Store register Byte Immediate Post-Index
241 * Rd: register to store
244 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
247 * Im: Branch target (left-shifted by 2 bits, added to PC)
248 * L: 1: branch and link 0: branch only
250 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
252 /* Branch and exchange (ARM state)
253 * Rm: register holding branch target address
255 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
257 /* Move to ARM register from coprocessor
258 * CP: Coprocessor number
259 * op1: Coprocessor opcode
260 * Rd: destination register
261 * CRn: first coprocessor operand
262 * CRm: second coprocessor operand
263 * op2: Second coprocessor opcode
265 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
267 /* Move to coprocessor from ARM register
268 * CP: Coprocessor number
269 * op1: Coprocessor opcode
270 * Rd: destination register
271 * CRn: first coprocessor operand
272 * CRm: second coprocessor operand
273 * op2: Second coprocessor opcode
275 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
277 /* Breakpoint instruction (ARMv5)
278 * Im: 16-bit immediate
280 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
283 /* Thumb mode instructions
286 /* Store register (Thumb mode)
287 * Rd: source register
290 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
292 /* Load register (Thumb state)
293 * Rd: destination register
296 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
298 /* Load multiple (Thumb state)
300 * List: for each bit in list: store register
302 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
304 /* Load register with PC relative addressing
305 * Rd: register to load
307 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
309 /* Move hi register (Thumb mode)
310 * Rd: destination register
311 * Rm: source register
313 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
315 /* No operation (Thumb mode)
317 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
319 /* Move immediate to register (Thumb state)
320 * Rd: destination register
321 * Im: 8-bit immediate value
323 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
325 /* Branch and Exchange
326 * Rm: register containing branch target
328 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
330 /* Branch (Thumb state)
333 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
335 /* Breakpoint instruction (ARMv5) (Thumb state)
336 * Im: 8-bit immediate
338 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
340 /* build basic mrc/mcr opcode */
342 static inline uint32_t mrc_opcode(int cpnum
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
)
352 #endif /* ARMV4_5_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)