src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include "register.h"
  30 #include "target.h"
  31 #include "log.h"
  32
  33 typedef enum armv4_5_mode
  34 {
  35         ARMV4_5_MODE_USR = 16,
  36         ARMV4_5_MODE_FIQ = 17,
  37         ARMV4_5_MODE_IRQ = 18,
  38         ARMV4_5_MODE_SVC = 19,
  39         ARMV4_5_MODE_ABT = 23,
  40         ARMV4_5_MODE_UND = 27,
  41         ARMV4_5_MODE_SYS = 31,
  42         ARMV4_5_MODE_ANY = -1
  43 } armv4_5_mode_t;
  44
  45 extern char** armv4_5_mode_strings;
  46
  47 typedef enum armv4_5_state
  48 {
  49         ARMV4_5_STATE_ARM,
  50         ARMV4_5_STATE_THUMB,
  51         ARMV4_5_STATE_JAZELLE,
  52 } armv4_5_state_t;
  53
  54 extern char* armv4_5_state_strings[];
  55
  56 extern int armv4_5_core_reg_map[7][17];
  57
  58 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  59                 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
  60 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
  61                 cache->reg_list[armv4_5_core_reg_map[mode][num]]
  62
  63 /* offsets into armv4_5 core register cache */
  64 enum
  65 {
  66         ARMV4_5_CPSR = 31,
  67         ARMV4_5_SPSR_FIQ = 32,
  68         ARMV4_5_SPSR_IRQ = 33,
  69         ARMV4_5_SPSR_SVC = 34,
  70         ARMV4_5_SPSR_ABT = 35,
  71         ARMV4_5_SPSR_UND = 36
  72 };
  73
  74 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
  75
  76 typedef struct armv4_5_common_s
  77 {
  78         int common_magic;
  79         reg_cache_t *core_cache;
  80         int /* armv4_5_mode */ core_mode;
  81         enum armv4_5_state core_state;
  82         bool is_armv4;
  83         int (*full_context)(struct target_s *target);
  84         int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
  85         int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
  86         void *arch_info;
  87 } armv4_5_common_t;
  88
  89 typedef struct armv4_5_algorithm_s
  90 {
  91         int common_magic;
  92
  93         enum armv4_5_mode core_mode;
  94         enum armv4_5_state core_state;
  95 } armv4_5_algorithm_t;
  96
  97 typedef struct armv4_5_core_reg_s
  98 {
  99         int num;
 100         enum armv4_5_mode mode;
 101         target_t *target;
 102         armv4_5_common_t *armv4_5_common;
 103 } armv4_5_core_reg_t;
 104
 105 extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
 106
 107 /* map psr mode bits to linear number */
 108 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 109 {
 110         switch (mode)
 111         {
 112                 case ARMV4_5_MODE_USR: return 0; break;
 113                 case ARMV4_5_MODE_FIQ: return 1; break;
 114                 case ARMV4_5_MODE_IRQ: return 2; break;
 115                 case ARMV4_5_MODE_SVC: return 3; break;
 116                 case ARMV4_5_MODE_ABT: return 4; break;
 117                 case ARMV4_5_MODE_UND: return 5; break;
 118                 case ARMV4_5_MODE_SYS: return 6; break;
 119                 case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
 120                 default:
 121                         LOG_ERROR("invalid mode value encountered %d", mode);
 122                         return -1;
 123         }
 124 }
 125
 126 /* map linear number to mode bits */
 127 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 128 {
 129         switch (number)
 130         {
 131                 case 0: return ARMV4_5_MODE_USR; break;
 132                 case 1: return ARMV4_5_MODE_FIQ; break;
 133                 case 2: return ARMV4_5_MODE_IRQ; break;
 134                 case 3: return ARMV4_5_MODE_SVC; break;
 135                 case 4: return ARMV4_5_MODE_ABT; break;
 136                 case 5: return ARMV4_5_MODE_UND; break;
 137                 case 6: return ARMV4_5_MODE_SYS; break;
 138                 default:
 139                         LOG_ERROR("mode index out of bounds %d", number);
 140                         return ARMV4_5_MODE_ANY;
 141         }
 142 };
 143
 144 extern int armv4_5_arch_state(struct target_s *target);
 145 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
 146
 147 extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
 148 extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 149
 150 extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 151
 152 extern int armv4_5_invalidate_core_regs(target_t *target);
 153
 154 /* ARM mode instructions
 155  */
 156
 157 /* Store multiple increment after
 158  * Rn: base register
 159  * List: for each bit in list: store register
 160  * S: in priviledged mode: store user-mode registers
 161  * W = 1: update the base register. W = 0: leave the base register untouched
 162  */
 163 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 164
 165 /* Load multiple increment after
 166  * Rn: base register
 167  * List: for each bit in list: store register
 168  * S: in priviledged mode: store user-mode registers
 169  * W = 1: update the base register. W = 0: leave the base register untouched
 170  */
 171 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 172
 173 /* MOV r8, r8 */
 174 #define ARMV4_5_NOP                                     (0xe1a08008)
 175
 176 /* Move PSR to general purpose register
 177  * R = 1: SPSR R = 0: CPSR
 178  * Rn: target register
 179  */
 180 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 181
 182 /* Store register
 183  * Rd: register to store
 184  * Rn: base register
 185  */
 186 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 187
 188 /* Load register
 189  * Rd: register to load
 190  * Rn: base register
 191  */
 192 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 193
 194 /* Move general purpose register to PSR
 195  * R = 1: SPSR R = 0: CPSR
 196  * Field: Field mask
 197  * 1: control field 2: extension field 4: status field 8: flags field
 198  * Rm: source register
 199  */
 200 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 201 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 202
 203 /* Load Register Halfword Immediate Post-Index
 204  * Rd: register to load
 205  * Rn: base register
 206  */
 207 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 208
 209 /* Load Register Byte Immediate Post-Index
 210  * Rd: register to load
 211  * Rn: base register
 212  */
 213 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 214
 215 /* Store register Halfword Immediate Post-Index
 216  * Rd: register to store
 217  * Rn: base register
 218  */
 219 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 220
 221 /* Store register Byte Immediate Post-Index
 222  * Rd: register to store
 223  * Rn: base register
 224  */
 225 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 226
 227 /* Branch (and Link)
 228  * Im: Branch target (left-shifted by 2 bits, added to PC)
 229  * L: 1: branch and link 0: branch only
 230  */
 231 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 232
 233 /* Branch and exchange (ARM state)
 234  * Rm: register holding branch target address
 235  */
 236 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 237
 238 /* Move to ARM register from coprocessor
 239  * CP: Coprocessor number
 240  * op1: Coprocessor opcode
 241  * Rd: destination register
 242  * CRn: first coprocessor operand
 243  * CRm: second coprocessor operand
 244  * op2: Second coprocessor opcode
 245  */
 246 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 247
 248 /* Move to coprocessor from ARM register
 249  * CP: Coprocessor number
 250  * op1: Coprocessor opcode
 251  * Rd: destination register
 252  * CRn: first coprocessor operand
 253  * CRm: second coprocessor operand
 254  * op2: Second coprocessor opcode
 255  */
 256 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 257
 258 /* Breakpoint instruction (ARMv5)
 259  * Im: 16-bit immediate
 260  */
 261 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 262
 263
 264 /* Thumb mode instructions
 265  */
 266
 267 /* Store register (Thumb mode)
 268  * Rd: source register
 269  * Rn: base register
 270  */
 271 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 272
 273 /* Load register (Thumb state)
 274  * Rd: destination register
 275  * Rn: base register
 276  */
 277 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 278
 279 /* Load multiple (Thumb state)
 280  * Rn: base register
 281  * List: for each bit in list: store register
 282  */
 283 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 284
 285 /* Load register with PC relative addressing
 286  * Rd: register to load
 287  */
 288 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 289
 290 /* Move hi register (Thumb mode)
 291  * Rd: destination register
 292  * Rm: source register
 293  */
 294 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 295
 296 /* No operation (Thumb mode)
 297  */
 298 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 299
 300 /* Move immediate to register (Thumb state)
 301  * Rd: destination register
 302  * Im: 8-bit immediate value
 303  */
 304 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 305
 306 /* Branch and Exchange
 307  * Rm: register containing branch target
 308  */
 309 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 310
 311 /* Branch (Thumb state)
 312  * Imm: Branch target
 313  */
 314 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 315
 316 /* Breakpoint instruction (ARMv5) (Thumb state)
 317  * Im: 8-bit immediate
 318  */
 319 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 320
 321 /* build basic mrc/mcr opcode */
 322
 323 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 324 {
 325         uint32_t t = 0;
 326         t|=op1<<21;
 327         t|=op2<<5;
 328         t|=CRn<<16;
 329         t|=CRm<<0;
 330         return t;
 331 }
 332
 333
 334
 335
 336 #endif /* ARMV4_5_H */