src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include <target/target.h>
  30 #include <helper/command.h>
  31
  32
  33 /**
  34  * These numbers match the five low bits of the *PSR registers on
  35  * "classic ARM" processors, which build on the ARMv4 processor
  36  * modes and register set.
  37  */
  38 enum arm_mode {
  39         ARM_MODE_USR = 16,
  40         ARM_MODE_FIQ = 17,
  41         ARM_MODE_IRQ = 18,
  42         ARM_MODE_SVC = 19,
  43         ARM_MODE_ABT = 23,
  44         ARM_MODE_MON = 26,
  45         ARM_MODE_UND = 27,
  46         ARM_MODE_SYS = 31,
  47         ARM_MODE_ANY = -1
  48 };
  49
  50 const char *arm_mode_name(unsigned psr_mode);
  51 bool is_arm_mode(unsigned psr_mode);
  52
  53 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
  54 enum arm_state {
  55         ARM_STATE_ARM,
  56         ARM_STATE_THUMB,
  57         ARM_STATE_JAZELLE,
  58         ARM_STATE_THUMB_EE,
  59 };
  60
  61 extern const char *arm_state_strings[];
  62
  63 /* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
  64  * index into the armv4_5_core_reg_map array.  Its remaining users are
  65  * remnants which could as easily walk * the register cache directly as
  66  * use the expensive ARMV4_5_CORE_REG_MODE() macro.
  67  */
  68 int arm_mode_to_number(enum arm_mode mode);
  69 enum arm_mode armv4_5_number_to_mode(int number);
  70
  71 extern const int armv4_5_core_reg_map[8][17];
  72
  73 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  74                 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
  75
  76 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
  77 enum { ARMV4_5_CPSR = 31, };
  78
  79 #define ARM_COMMON_MAGIC 0x0A450A45
  80
  81 /**
  82  * Represents a generic ARM core, with standard application registers.
  83  *
  84  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  85  * Cortex-M series cores do not support as many core states or shadowed
  86  * registers as traditional ARM cores, and only support Thumb2 instructions.
  87  */
  88 struct arm
  89 {
  90         int common_magic;
  91         struct reg_cache *core_cache;
  92
  93         /** Handle to the CPSR; valid in all core modes. */
  94         struct reg *cpsr;
  95
  96         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  97         struct reg *spsr;
  98
  99         /** Support for arm_reg_current() */
 100         const int *map;
 101
 102         /**
 103          * Indicates what registers are in the ARM state core register set.
 104          * ARM_MODE_ANY indicates the standard set of 37 registers,
 105          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 106          * more registers are shadowed, for "Secure Monitor" mode.
 107          */
 108         enum arm_mode core_type;
 109
 110         /** Record the current core mode: SVC, USR, or some other mode. */
 111         enum arm_mode core_mode;
 112
 113         /** Record the current core state: ARM, Thumb, or otherwise. */
 114         enum arm_state core_state;
 115
 116         /** Flag reporting unavailability of the BKPT instruction. */
 117         bool is_armv4;
 118
 119         /** Flag reporting whether semihosting is active. */
 120         bool is_semihosting;
 121
 122         /** Value to be returned by semihosting SYS_ERRNO request. */
 123         int semihosting_errno;
 124
 125         /** Backpointer to the target. */
 126         struct target *target;
 127
 128         /** Handle for the debug module, if one is present. */
 129         struct arm_dpm *dpm;
 130
 131         /** Handle for the Embedded Trace Module, if one is present. */
 132         struct etm_context *etm;
 133
 134         /* FIXME all these methods should take "struct arm *" not target */
 135
 136         /** Retrieve all core registers, for display. */
 137         int (*full_context)(struct target *target);
 138
 139         /** Retrieve a single core register. */
 140         int (*read_core_reg)(struct target *target, struct reg *reg,
 141                         int num, enum arm_mode mode);
 142         int (*write_core_reg)(struct target *target, struct reg *reg,
 143                         int num, enum arm_mode mode, uint32_t value);
 144
 145         /** Read coprocessor register.  */
 146         int (*mrc)(struct target *target, int cpnum,
 147                         uint32_t op1, uint32_t op2,
 148                         uint32_t CRn, uint32_t CRm,
 149                         uint32_t *value);
 150
 151         /** Write coprocessor register.  */
 152         int (*mcr)(struct target *target, int cpnum,
 153                         uint32_t op1, uint32_t op2,
 154                         uint32_t CRn, uint32_t CRm,
 155                         uint32_t value);
 156
 157         void *arch_info;
 158 };
 159
 160 /** Convert target handle to generic ARM target state handle. */
 161 static inline struct arm *target_to_arm(struct target *target)
 162 {
 163         return target->arch_info;
 164 }
 165
 166 static inline bool is_arm(struct arm *arm)
 167 {
 168         return arm && arm->common_magic == ARM_COMMON_MAGIC;
 169 }
 170
 171 struct arm_algorithm
 172 {
 173         int common_magic;
 174
 175         enum arm_mode core_mode;
 176         enum arm_state core_state;
 177 };
 178
 179 struct arm_reg
 180 {
 181         int num;
 182         enum arm_mode mode;
 183         struct target *target;
 184         struct arm *armv4_5_common;
 185         uint32_t value;
 186 };
 187
 188 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 189
 190 int arm_arch_state(struct target *target);
 191 int arm_get_gdb_reg_list(struct target *target,
 192                 struct reg **reg_list[], int *reg_list_size);
 193
 194 extern const struct command_registration arm_command_handlers[];
 195
 196 int arm_init_arch_info(struct target *target, struct arm *arm);
 197
 198 int armv4_5_run_algorithm(struct target *target,
 199                 int num_mem_params, struct mem_param *mem_params,
 200                 int num_reg_params, struct reg_param *reg_params,
 201                 uint32_t entry_point, uint32_t exit_point,
 202                 int timeout_ms, void *arch_info);
 203
 204 int arm_checksum_memory(struct target *target,
 205                 uint32_t address, uint32_t count, uint32_t *checksum);
 206 int arm_blank_check_memory(struct target *target,
 207                 uint32_t address, uint32_t count, uint32_t *blank);
 208
 209 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 210 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 211
 212 extern struct reg arm_gdb_dummy_fp_reg;
 213 extern struct reg arm_gdb_dummy_fps_reg;
 214
 215 #endif /* ARMV4_5_H */