1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
29 #include <target/target.h>
30 #include <helper/command.h>
33 /* These numbers match the five low bits of the *PSR registers on
34 * "classic ARM" processors, which build on the ARMv4 processor
35 * modes and register set.
49 const char *arm_mode_name(unsigned psr_mode
);
50 bool is_arm_mode(unsigned psr_mode
);
52 /* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
60 extern const char *arm_state_strings
[];
62 /* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
63 * index into the armv4_5_core_reg_map array. Its remaining users are
64 * remnants which could as easily walk * the register cache directly as
65 * use the expensive ARMV4_5_CORE_REG_MODE() macro.
67 int arm_mode_to_number(enum arm_mode mode
);
68 enum arm_mode
armv4_5_number_to_mode(int number
);
70 extern const int armv4_5_core_reg_map
[8][17];
72 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
73 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
75 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
76 enum { ARMV4_5_CPSR
= 31, };
78 #define ARM_COMMON_MAGIC 0x0A450A45
81 * Represents a generic ARM core, with standard application registers.
83 * There are sixteen application registers (including PC, SP, LR) and a PSR.
84 * Cortex-M series cores do not support as many core states or shadowed
85 * registers as traditional ARM cores, and only support Thumb2 instructions.
90 struct reg_cache
*core_cache
;
92 /** Handle to the CPSR; valid in all core modes. */
95 /** Handle to the SPSR; valid only in core modes with an SPSR. */
101 * Indicates what registers are in the ARM state core register set.
102 * ARM_MODE_ANY indicates the standard set of 37 registers,
103 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
104 * more registers are shadowed, for "Secure Monitor" mode.
106 enum arm_mode core_type
;
108 enum arm_mode core_mode
;
109 enum arm_state core_state
;
111 /** Flag reporting unavailability of the BKPT instruction. */
114 /** Flag reporting whether semihosting is active. */
117 /** Value to be returned by semihosting SYS_ERRNO request. */
118 int semihosting_errno
;
120 /** Backpointer to the target. */
121 struct target
*target
;
123 /** Handle for the debug module, if one is present. */
126 /** Handle for the Embedded Trace Module, if one is present. */
127 struct etm_context
*etm
;
129 /* FIXME all these methods should take "struct arm *" not target */
131 int (*full_context
)(struct target
*target
);
132 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
133 int num
, enum arm_mode mode
);
134 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
135 int num
, enum arm_mode mode
, uint32_t value
);
137 /** Read coprocessor register. */
138 int (*mrc
)(struct target
*target
, int cpnum
,
139 uint32_t op1
, uint32_t op2
,
140 uint32_t CRn
, uint32_t CRm
,
143 /* Write coprocessor register. */
144 int (*mcr
)(struct target
*target
, int cpnum
,
145 uint32_t op1
, uint32_t op2
,
146 uint32_t CRn
, uint32_t CRm
,
152 /** Convert target handle to generic ARM target state handle. */
153 static inline struct arm
*target_to_arm(struct target
*target
)
155 return target
->arch_info
;
158 static inline bool is_arm(struct arm
*arm
)
160 return arm
&& arm
->common_magic
== ARM_COMMON_MAGIC
;
167 enum arm_mode core_mode
;
168 enum arm_state core_state
;
175 struct target
*target
;
176 struct arm
*armv4_5_common
;
180 struct reg_cache
* armv4_5_build_reg_cache(struct target
*target
,
181 struct arm
*armv4_5_common
);
183 int armv4_5_arch_state(struct target
*target
);
184 int armv4_5_get_gdb_reg_list(struct target
*target
,
185 struct reg
**reg_list
[], int *reg_list_size
);
187 extern const struct command_registration arm_command_handlers
[];
189 int armv4_5_init_arch_info(struct target
*target
, struct arm
*armv4_5
);
191 int armv4_5_run_algorithm(struct target
*target
,
192 int num_mem_params
, struct mem_param
*mem_params
,
193 int num_reg_params
, struct reg_param
*reg_params
,
194 uint32_t entry_point
, uint32_t exit_point
,
195 int timeout_ms
, void *arch_info
);
197 int arm_checksum_memory(struct target
*target
,
198 uint32_t address
, uint32_t count
, uint32_t *checksum
);
199 int arm_blank_check_memory(struct target
*target
,
200 uint32_t address
, uint32_t count
, uint32_t *blank
);
202 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
203 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
205 extern struct reg arm_gdb_dummy_fp_reg
;
206 extern struct reg arm_gdb_dummy_fps_reg
;
208 /* ARM mode instructions
211 /* Store multiple increment after
213 * List: for each bit in list: store register
214 * S: in priviledged mode: store user-mode registers
215 * W = 1: update the base register. W = 0: leave the base register untouched
217 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
219 /* Load multiple increment after
221 * List: for each bit in list: store register
222 * S: in priviledged mode: store user-mode registers
223 * W = 1: update the base register. W = 0: leave the base register untouched
225 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
228 #define ARMV4_5_NOP (0xe1a08008)
230 /* Move PSR to general purpose register
231 * R = 1: SPSR R = 0: CPSR
232 * Rn: target register
234 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
237 * Rd: register to store
240 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
243 * Rd: register to load
246 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
248 /* Move general purpose register to PSR
249 * R = 1: SPSR R = 0: CPSR
251 * 1: control field 2: extension field 4: status field 8: flags field
252 * Rm: source register
254 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
255 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
257 /* Load Register Halfword Immediate Post-Index
258 * Rd: register to load
261 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
263 /* Load Register Byte Immediate Post-Index
264 * Rd: register to load
267 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
269 /* Store register Halfword Immediate Post-Index
270 * Rd: register to store
273 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
275 /* Store register Byte Immediate Post-Index
276 * Rd: register to store
279 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
282 * Im: Branch target (left-shifted by 2 bits, added to PC)
283 * L: 1: branch and link 0: branch only
285 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
287 /* Branch and exchange (ARM state)
288 * Rm: register holding branch target address
290 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
292 /* Move to ARM register from coprocessor
293 * CP: Coprocessor number
294 * op1: Coprocessor opcode
295 * Rd: destination register
296 * CRn: first coprocessor operand
297 * CRm: second coprocessor operand
298 * op2: Second coprocessor opcode
300 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
302 /* Move to coprocessor from ARM register
303 * CP: Coprocessor number
304 * op1: Coprocessor opcode
305 * Rd: destination register
306 * CRn: first coprocessor operand
307 * CRm: second coprocessor operand
308 * op2: Second coprocessor opcode
310 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
312 /* Breakpoint instruction (ARMv5)
313 * Im: 16-bit immediate
315 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
318 /* Thumb mode instructions
321 /* Store register (Thumb mode)
322 * Rd: source register
325 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
327 /* Load register (Thumb state)
328 * Rd: destination register
331 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
333 /* Load multiple (Thumb state)
335 * List: for each bit in list: store register
337 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
339 /* Load register with PC relative addressing
340 * Rd: register to load
342 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
344 /* Move hi register (Thumb mode)
345 * Rd: destination register
346 * Rm: source register
348 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
350 /* No operation (Thumb mode)
352 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
354 /* Move immediate to register (Thumb state)
355 * Rd: destination register
356 * Im: 8-bit immediate value
358 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
360 /* Branch and Exchange
361 * Rm: register containing branch target
363 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
365 /* Branch (Thumb state)
368 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
370 /* Breakpoint instruction (ARMv5) (Thumb state)
371 * Im: 8-bit immediate
373 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
375 /* build basic mrc/mcr opcode */
377 static inline uint32_t mrc_opcode(int cpnum
, uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
)
387 #endif /* ARMV4_5_H */
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